[RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension

[mtsamis]

Summary

The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache management instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:

https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:

https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c

[mtsamis]

Move predicates and decoder namespace to instruction definitions.
The same classes are also wanted for the XTHeadSync extension and are shared.

[craig.topper]

LGTM

llvm/docs/RISCVUsage.rst

``XTHeadBa``
   LLVM implements `the THeadBa (address-generation) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
 
 ``XTHeadBb``
   LLVM implements `the THeadBb (basic bit-manipulation) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
 
 ``XTHeadBs``
   LLVM implements `the THeadBs (single-bit operations) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
 
+``XTHeadCmo``
+  LLVM implements `the THeadCmo (cache management operations) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
+
 ``XTheadMac``
   LLVM implements `the XTheadMac (multiply-accumulate instructions) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
 
 ``XTHeadMemPair``
   LLVM implements `the THeadMemPair (two-GPR memory operations) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
 
 ``XTHeadVdot``
   LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf>`_ by T-HEAD of Alibaba.  All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above.

llvm/docs/ReleaseNotes.rst

* vsetvli intrinsics no longer have side effects. They may now be combined,
   moved, deleted, etc. by optimizations.
 * Adds support for the vendor-defined XTHeadBa (address-generation) extension.
 * Adds support for the vendor-defined XTHeadBb (basic bit-manipulation) extension.
 * Adds support for the vendor-defined XTHeadBs (single-bit) extension.
 * Adds support for the vendor-defined XTHeadMac (multiply-accumulate instructions) extension.
 * Added support for the vendor-defined XTHeadMemPair (two-GPR memory operations)
   extension disassembler/assembler.
 * Support for the now-ratified Zawrs extension is no longer experimental.
+* Adds support for the vendor-defined XTHeadCmo (cache management operations) extension.
 
 Changes to the WebAssembly Backend
 ----------------------------------
 
 * ...
 
 Changes to the Windows Target
 -----------------------------

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"svnapot", RISCVExtensionVersion{1, 0}},
     {"svpbmt", RISCVExtensionVersion{1, 0}},
     {"svinval", RISCVExtensionVersion{1, 0}},
 
     // vendor-defined ('X') extensions
     {"xtheadba", RISCVExtensionVersion{1, 0}},
     {"xtheadbb", RISCVExtensionVersion{1, 0}},
     {"xtheadbs", RISCVExtensionVersion{1, 0}},
+    {"xtheadcmo", RISCVExtensionVersion{1, 0}},
     {"xtheadmac", RISCVExtensionVersion{1, 0}},
     {"xtheadmempair", RISCVExtensionVersion{1, 0}},
     {"xtheadvdot", RISCVExtensionVersion{1, 0}},
     {"xventanacondops", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zihintntl", RISCVExtensionVersion{0, 2}},

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

if ((Bytes[0] & 0x3) == 0x3) {
     }
     if (STI.hasFeature(RISCV::FeatureVendorXTHeadBs)) {
       LLVM_DEBUG(dbgs() << "Trying XTHeadBs custom opcode table:\n");
       Result = decodeInstruction(DecoderTableTHeadBs32, MI, Insn, Address, this,
                                  STI);
       if (Result != MCDisassembler::Fail)
         return Result;
     }
+    if (STI.hasFeature(RISCV::FeatureVendorXTHeadCmo)) {
+      LLVM_DEBUG(dbgs() << "Trying XTHeadCmo custom opcode table:\n");
+      Result = decodeInstruction(DecoderTableTHeadCmo32, MI, Insn, Address,
+                                 this, STI);
+      if (Result != MCDisassembler::Fail)
+        return Result;
+    }
     if (STI.hasFeature(RISCV::FeatureVendorXTHeadMac)) {
       LLVM_DEBUG(dbgs() << "Trying XTHeadMac custom opcode table:\n");
       Result = decodeInstruction(DecoderTableTHeadMac32, MI, Insn, Address,
                                  this, STI);
       if (Result != MCDisassembler::Fail)
         return Result;
     }
     if (STI.hasFeature(RISCV::FeatureVendorXTHeadMemPair)) {

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureVendorXTHeadBs
     : SubtargetFeature<"xtheadbs", "HasVendorXTHeadBs", "true",
                        "'xtheadbs' (T-Head single-bit instructions)">;
 def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
                                   AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
                                   "'xtheadbs' (T-Head single-bit instructions)">;
 
+def FeatureVendorXTHeadCmo
+    : SubtargetFeature<"xtheadcmo", "HasVendorXTHeadCmo", "true",
+                       "'xtheadcmo' (T-Head cache management instructions)">;
+def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
+                                   AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),
+                                   "'xtheadcmo' (T-Head cache management instructions)">;
+
 def FeatureVendorXTHeadMac
     : SubtargetFeature<"xtheadmac", "HasVendorXTHeadMac", "true",
                        "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
 def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
                                    AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
                                    "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
 
 def FeatureVendorXTHeadMemPair

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

: RVInstR<!shl(funct5, 2), 0b101, OPC_CUSTOM_0,
             (outs),
             (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
             opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
   bits<2> uimm2;
   let Inst{26-25} = uimm2;
   let DecoderMethod = "decodeXTHeadMemPair";
 }
 
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+class THCacheInst_r<bits<5> funct5, string opcodestr>
+    : RVInstR<0b0000001, 0, OPC_CUSTOM_0, (outs), (ins GPR:$rs1),
+              opcodestr, "$rs1"> {
+  let rd = 0;
+  let rs2 = funct5;
+}
+
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+class THCacheInst_void<bits<5> funct5, string opcodestr>
+    : RVInstR<0b0000000, 0, OPC_CUSTOM_0, (outs), (ins), opcodestr, ""> {
+  let rd = 0;
+  let rs1 = 0;
+  let rs2 = funct5;
+}
 
 //===----------------------------------------------------------------------===//
 // Combination of instruction classes.
 // Use these multiclasses to define instructions more easily.
 //===----------------------------------------------------------------------===//
 multiclass THVdotVMAQA_VX<string opcodestr, bits<6> funct6> {
   def _VX : THVdotALUrVX<funct6, OPMVX, opcodestr # ".vx">;
 }
def : Pat<(th_sdd i64:$rd1, i64:$rd2, i64:$rs1, uimm2_4:$uimm2_4),
           (TH_SDD i64:$rd1, i64:$rd2, i64:$rs1, uimm2_4:$uimm2_4, 4)>;
 }
 
 let Predicates = [HasVendorXTHeadMemPair] in {
   def : Pat<(th_lwd GPR:$rs1, uimm2_3:$uimm2_3), (TH_LWD GPR:$rs1, uimm2_3:$uimm2_3, 3)>;
   def : Pat<(th_swd GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3),
             (TH_SWD GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3, 3)>;
 }
+
+let Predicates = [HasVendorXTHeadCmo], DecoderNamespace = "THeadCmo" in {
+def TH_DCACHE_CSW    : THCacheInst_r<0b00001, "th.dcache.csw">;
+def TH_DCACHE_ISW    : THCacheInst_r<0b00010, "th.dcache.isw">;
+def TH_DCACHE_CISW   : THCacheInst_r<0b00011, "th.dcache.cisw">;
+def TH_DCACHE_CVAL1  : THCacheInst_r<0b00100, "th.dcache.cval1">;
+def TH_DCACHE_CVA    : THCacheInst_r<0b00101, "th.dcache.cva">;
+def TH_DCACHE_IVA    : THCacheInst_r<0b00110, "th.dcache.iva">;
+def TH_DCACHE_CIVA   : THCacheInst_r<0b00111, "th.dcache.civa">;
+def TH_DCACHE_CPAL1  : THCacheInst_r<0b01000, "th.dcache.cpal1">;
+def TH_DCACHE_CPA    : THCacheInst_r<0b01001, "th.dcache.cpa">;
+def TH_DCACHE_IPA    : THCacheInst_r<0b01010, "th.dcache.ipa">;
+def TH_DCACHE_CIPA   : THCacheInst_r<0b01011, "th.dcache.cipa">;
+def TH_ICACHE_IVA    : THCacheInst_r<0b10000, "th.icache.iva">;
+def TH_ICACHE_IPA    : THCacheInst_r<0b11000, "th.icache.ipa">;
+
+def TH_DCACHE_CALL   : THCacheInst_void<0b00001, "th.dcache.call">;
+def TH_DCACHE_IALL   : THCacheInst_void<0b00010, "th.dcache.iall">;
+def TH_DCACHE_CIALL  : THCacheInst_void<0b00011, "th.dcache.ciall">;
+def TH_ICACHE_IALL   : THCacheInst_void<0b10000, "th.icache.iall">;
+def TH_ICACHE_IALLS  : THCacheInst_void<0b10001, "th.icache.ialls">;
+def TH_L2CACHE_CALL  : THCacheInst_void<0b10101, "th.l2cache.call">;
+def TH_L2CACHE_IALL  : THCacheInst_void<0b10110, "th.l2cache.iall">;
+def TH_L2CACHE_CIALL : THCacheInst_void<0b10111, "th.l2cache.ciall">;
+}

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefixes=CHECK,RV32COMBINEINTOZKN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefixes=CHECK,RV32COMBINEINTOZKS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOZ %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOP %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
+; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac %s -o - | FileCheck --check-prefixes=CHECK,RV32XTHEADMAC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCD %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s

 ; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOP %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadba %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADBA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADBB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadbs %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADBS %s
+; RUN: llc -mtriple=riscv64 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV64XTHEADCMO %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADMAC %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV64XTHEADMEMPAIR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s

 ; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
 ; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
 ; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
 ; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
 ; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
 ; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
 ; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
 ; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
+; RV32XTHEADCMO: .attribute 5, "rv32i2p0_xtheadcmo1p0"
 ; RV32XTHEADMAC: .attribute 5, "rv32i2p0_xtheadmac1p0"
 ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p0_xtheadmempair1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p0_zca1p0"
 ; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
 ; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"

 ; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
 ; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
 ; RV64SVPBMT: .attribute 5, "rv64i2p0_svpbmt1p0"
 ; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
 ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
 ; RV64XTHEADBA: .attribute 5, "rv64i2p0_xtheadba1p0"
 ; RV64XTHEADBB: .attribute 5, "rv64i2p0_xtheadbb1p0"
 ; RV64XTHEADBS: .attribute 5, "rv64i2p0_xtheadbs1p0"
+; RV64XTHEADCMO: .attribute 5, "rv64i2p0_xtheadcmo1p0"
 ; RV64XTHEADMAC: .attribute 5, "rv64i2p0_xtheadmac1p0"
 ; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p0_xtheadmempair1p0"
 ; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 ; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
 ; RV64ZCB: .attribute 5, "rv64i2p0_zca1p0_zcb1p0"
 ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
 ; RV64ZFA: .attribute 5, "rv64i2p0_f2p0_zfa0p1"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/xtheadcmo-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+xtheadcmo < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+xtheadcmo < %s 2>&1 | FileCheck %s
+
+th.dcache.csw # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.isw # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.cisw # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.cval1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.cva # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.iva # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.civa # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.cpal1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.cpa # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.ipa # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.dcache.cipa # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.icache.iva # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+th.icache.ipa # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+
+th.dcache.call t0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+th.dcache.iall t0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+th.dcache.ciall t0 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+th.icache.iall t0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+th.icache.ialls t0 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+th.l2cache.call t0 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+th.l2cache.iall t0 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+th.l2cache.ciall t0 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction

llvm/test/MC/RISCV/xtheadcmo-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xtheadcmo -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xtheadcmo < %s \
+# RUN:     | llvm-objdump --mattr=+xtheadcmo -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xtheadcmo -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xtheadcmo < %s \
+# RUN:     | llvm-objdump --mattr=+xtheadcmo -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: th.dcache.csw a6
+# CHECK-ASM: encoding: [0x0b,0x00,0x18,0x02]
+th.dcache.csw a6
+
+# CHECK-ASM-AND-OBJ: th.dcache.isw t0
+# CHECK-ASM: encoding: [0x0b,0x80,0x22,0x02]
+th.dcache.isw t0
+
+# CHECK-ASM-AND-OBJ: th.dcache.cisw a7
+# CHECK-ASM: encoding: [0x0b,0x80,0x38,0x02]
+th.dcache.cisw a7
+
+# CHECK-ASM-AND-OBJ: th.dcache.cval1 t2
+# CHECK-ASM: encoding: [0x0b,0x80,0x43,0x02]
+th.dcache.cval1 t2
+
+# CHECK-ASM-AND-OBJ: th.dcache.cva a3
+# CHECK-ASM: encoding: [0x0b,0x80,0x56,0x02]
+th.dcache.cva a3
+
+# CHECK-ASM-AND-OBJ: th.dcache.iva a5
+# CHECK-ASM: encoding: [0x0b,0x80,0x67,0x02]
+th.dcache.iva a5
+
+# CHECK-ASM-AND-OBJ: th.dcache.civa a4
+# CHECK-ASM: encoding: [0x0b,0x00,0x77,0x02]
+th.dcache.civa a4
+
+# CHECK-ASM-AND-OBJ: th.dcache.cpal1 t1
+# CHECK-ASM: encoding: [0x0b,0x00,0x83,0x02]
+th.dcache.cpal1 t1
+
+# CHECK-ASM-AND-OBJ: th.dcache.cpa a0
+# CHECK-ASM: encoding: [0x0b,0x00,0x95,0x02]
+th.dcache.cpa a0
+
+# CHECK-ASM-AND-OBJ: th.dcache.ipa a2
+# CHECK-ASM: encoding: [0x0b,0x00,0xa6,0x02]
+th.dcache.ipa a2
+
+# CHECK-ASM-AND-OBJ: th.dcache.cipa a1
+# CHECK-ASM: encoding: [0x0b,0x80,0xb5,0x02]
+th.dcache.cipa a1
+
+# CHECK-ASM-AND-OBJ: th.icache.iva t4
+# CHECK-ASM: encoding: [0x0b,0x80,0x0e,0x03]
+th.icache.iva t4
+
+# CHECK-ASM-AND-OBJ: th.icache.ipa t3
+# CHECK-ASM: encoding: [0x0b,0x00,0x8e,0x03]
+th.icache.ipa t3
+
+# CHECK-ASM-AND-OBJ: th.dcache.call
+# CHECK-ASM: encoding: [0x0b,0x00,0x10,0x00]
+th.dcache.call
+
+# CHECK-ASM-AND-OBJ: th.dcache.iall
+# CHECK-ASM: encoding: [0x0b,0x00,0x20,0x00]
+th.dcache.iall
+
+# CHECK-ASM-AND-OBJ: th.dcache.ciall
+# CHECK-ASM: encoding: [0x0b,0x00,0x30,0x00]
+th.dcache.ciall
+
+# CHECK-ASM-AND-OBJ: th.icache.iall
+# CHECK-ASM: encoding: [0x0b,0x00,0x00,0x01]
+th.icache.iall
+
+# CHECK-ASM-AND-OBJ: th.icache.ialls
+# CHECK-ASM: encoding: [0x0b,0x00,0x10,0x01]
+th.icache.ialls
+
+# CHECK-ASM-AND-OBJ: th.l2cache.call
+# CHECK-ASM: encoding: [0x0b,0x00,0x50,0x01]
+th.l2cache.call
+
+# CHECK-ASM-AND-OBJ: th.l2cache.iall
+# CHECK-ASM: encoding: [0x0b,0x00,0x60,0x01]
+th.l2cache.iall
+
+# CHECK-ASM-AND-OBJ: th.l2cache.ciall
+# CHECK-ASM: encoding: [0x0b,0x00,0x70,0x01]
+th.l2cache.ciall