[MLIR][RISCV] Emit target-abi info for RISC-V

[sunshaoce]

Summary

Similar to D72755.

[ftynse]

Could we have a test?

[dcaballe]

I'm missing context here but do we want to restrict the ABIs to only those two? We are using ilp32, for example, and there are others (e.g., ilp32f, lp64, lp64f etc.).

[sunshaoce]

Address @ftynse's comment

[sunshaoce]

In D144330#4143007, @dcaballe wrote:

I'm missing context here but do we want to restrict the ABIs to only those two? We are using ilp32, for example, and there are others (e.g., ilp32f, lp64, lp64f etc.).

Thanks! I'm working on this.

[sunshaoce]

update

[kito-cheng]

mlir/lib/Target/LLVMIR/DebugTranslation.cpp

59

IIRC we are using lower case for -target-abi?

https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp#L74

[sunshaoce]

mlir/lib/Target/LLVMIR/DebugTranslation.cpp

59

I noticed that flang is experiencing linking errors due to the lack of code similar to clang D72755, such as llvm.module.flags like !{i32 1, !"target-abi", !"lp64"}.

[kito-cheng]

mlir/lib/Target/LLVMIR/DebugTranslation.cpp

59

I mean it should be ilp32/lp64 instead of ILP32/LP64?

62

f instead of F.

65

d instead of D.

[sunshaoce]

Address @kito-cheng's comment

[sunshaoce]

Gently ping

[sunshaoce]

ping

[jrtc27]

mlir/lib/Target/LLVMIR/DebugTranslation.cpp

61

You can have hard floats without using a hard float calling convention; the ABI is distinct from the ISA choice (other than the obvious dependencies on registers existing if you want to use them). Defaulting to using a hard-float calling convention is fine (and IIRC the psABI even recommends that) but it must be possible to have, say, ilp32 rv32if. In the Clang world this is configured with -mabi.

[sunshaoce]

@jrtc27 Thanks for your comment. I found the solution.

mlir/lib/Target/LLVMIR/DebugTranslation.cpp

61

You can have hard floats without using a hard float calling convention; the ABI is distinct from the ISA choice (other than the obvious dependencies on registers existing if you want to use them). Defaulting to using a hard-float calling convention is fine (and IIRC the psABI even recommends that) but it must be possible to have, say, ilp32 rv32if. In the Clang world this is configured with -mabi.

mlir/lib/Target/LLVMIR/DebugTranslation.cpp

 //===- DebugTranslation.cpp - MLIR to LLVM Debug conversion ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "DebugTranslation.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
+#include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/TypeSwitch.h"
 #include "llvm/IR/Metadata.h"
 #include "llvm/IR/Module.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
 
 using namespace mlir;
 using namespace mlir::LLVM;
if (auto targetTripleAttr =
           module->getAttr(LLVM::LLVMDialect::getTargetTripleAttrName())) {
     auto targetTriple =
         llvm::Triple(targetTripleAttr.cast<StringAttr>().getValue());
     if (targetTriple.isKnownWindowsMSVCEnvironment()) {
       // Dwarf debugging files will be generated by default, unless "CodeView"
       // is set explicitly. Windows/MSVC should use CodeView instead.
       llvmModule.addModuleFlag(llvm::Module::Warning, "CodeView", 1);
     }
+
+    if (targetTriple.isRISCV()) {
+      auto dataLayout = llvmModule.getDataLayout();
+      llvm::SmallString<7> dataModelStr;
+      dataModelStr = targetTriple.isRISCV32() ? "ILP32" : "LP64";
+
+      if (dataLayout.getABITypeAlign(llvm::Type::getFloatTy(llvmCtx)) == 32) {
+        dataModelStr += 'F';
+      }
+      if (dataLayout.getABITypeAlign(llvm::Type::getDoubleTy(llvmCtx)) == 32) {
+        dataModelStr += 'D';
+      }
+
+      llvmModule.addModuleFlag(llvm::Module::Warning, "target-abi",
+                               llvm::MDString::get(llvmCtx, dataModelStr));
+    }
   }
 }
 
 /// Finalize the translation of debug information.
 void DebugTranslation::finalize() {}
 
 /// Translate the debug information for the given function.
 void DebugTranslation::translate(LLVMFuncOp func, llvm::Function &llvmFunc) {

mlir/test/Dialect/LLVMIR/riscv32-abi.mlir

+// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
+
+// CHECK: target triple = "riscv32"
+// 
+// CHECK: llvm.module.flags
+// CHECK: !"target-abi", !"ILP32{{.*}}"
+module attributes {llvm.target_triple = "riscv32"} {
+  llvm.func @func() -> () {
+    llvm.return
+  } 
+}

mlir/test/Dialect/LLVMIR/riscv64-abi.mlir

+// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
+
+// CHECK: target triple = "riscv64"
+// 
+// CHECK: llvm.module.flags
+// CHECK: !"target-abi", !"LP64{{.*}}"
+module attributes {llvm.target_triple = "riscv64"} {
+  llvm.func @func() -> () {
+    llvm.return
+  } 
+}