[RISCV] Optimize (select (x in [0,1] != 0), y, (z ^ y) ) -> ((x-1) & z ) ^ y

[craig.topper]

Summary

This is the inverted case of
(select (x in [0,1] == 0), y, (z ^ y) ) -> (-x & z ) ^ y

Instead of -x we need -(x ^ 1) which simplifies to -(1-x) or (x-1).

[asb]

Reviewing this in isolation, LGTM. It's going to conflict with D140465 though so I'm not sure what your plan is there?

[craig.topper]

In D140454#4010211, @asb wrote:

Reviewing this in isolation, LGTM. It's going to conflict with D140465 though so I'm not sure what your plan is there?

I will abandon this patch. The select rabbit hole kept getting deeper after I wrote this patch. I'll extract the new tests from it though.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
case RISCVISD::SELECT_CC: {
     // If the True and False values are the same, we don't need a select_cc.
     if (TrueV == FalseV)
       return TrueV;
 
     // (select (x in [0,1] == 0), y, (z ^ y) ) -> (-x & z ) ^ y
     // (select (x in [0,1] != 0), (z ^ y), y ) -> (-x & z ) ^ y
     // (select (x in [0,1] == 0), y, (z | y) ) -> (-x & z ) | y
     // (select (x in [0,1] != 0), (z | y), y ) -> (-x & z ) | y
+    // (select (x in [0,1] != 0), y, (z ^ y) ) -> ((x-1) & z ) ^ y
+    // (select (x in [0,1] == 0), (z ^ y), y ) -> ((x-1) & z ) ^ y
+    // (select (x in [0,1] != 0), y, (z | y) ) -> ((x-1) & z ) | y
+    // (select (x in [0,1] == 0), (z | y), y ) -> ((x-1) & z ) | y
     // NOTE: We only do this if the target does not have the short forward
     // branch optimization.
     APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1);
     if (!Subtarget.hasShortForwardBranchOpt() && isNullConstant(RHS) &&
         ISD::isIntEqualitySetCC(CCVal) && DAG.MaskedValueIsZero(LHS, Mask)) {
+      bool Invert;
       unsigned Opcode;
       SDValue Src1, Src2;
       // true if FalseV is XOR or OR operator and one of its operands
       // is equal to Op1
       // ( a , a op b) || ( b , a op b)
       auto isOrXorPattern = [&]() {
-        if (CCVal == ISD::SETEQ &&
-            (FalseV.getOpcode() == ISD::XOR || FalseV.getOpcode() == ISD::OR) &&
+        if ((FalseV.getOpcode() == ISD::XOR || FalseV.getOpcode() == ISD::OR) &&
             (FalseV.getOperand(0) == TrueV || FalseV.getOperand(1) == TrueV)) {
           Src1 = FalseV.getOperand(0) == TrueV ?
             FalseV.getOperand(1) : FalseV.getOperand(0);
           Src2 = TrueV;
           Opcode = FalseV.getOpcode();
+          Invert = CCVal == ISD::SETNE;
           return true;
         }
-        if (CCVal == ISD::SETNE &&
-            (TrueV.getOpcode() == ISD::XOR || TrueV.getOpcode() == ISD::OR) &&
+        if ((TrueV.getOpcode() == ISD::XOR || TrueV.getOpcode() == ISD::OR) &&
             (TrueV.getOperand(0) == FalseV || TrueV.getOperand(1) == FalseV)) {
           Src1 = TrueV.getOperand(0) == FalseV ?
             TrueV.getOperand(1) : TrueV.getOperand(0);
           Src2 = FalseV;
           Opcode = TrueV.getOpcode();
+          Invert = CCVal == ISD::SETEQ;
           return true;
         }
 
         return false;
       };
 
       if (isOrXorPattern()) {
         assert(LHS.getValueType() == VT && "Unexpected VT!");
-        SDValue Mask = DAG.getNegative(LHS, DL, VT);             // -x
+        SDValue Mask;
+        if (Invert) {
+          // We need to -(x^1) which is equivalent to -(1-x) or x-1.
+          Mask = DAG.getNode(ISD::ADD, DL, VT, LHS,
+                             DAG.getAllOnesConstant(DL, VT));
+        } else {
+          Mask = DAG.getNegative(LHS, DL, VT); // -x
+        }
         SDValue And = DAG.getNode(ISD::AND, DL, VT, Mask, Src1); // Mask & z
         return DAG.getNode(Opcode, DL, VT, And, Src2);           // And Op y
       }
     }
 
     // (select (x < 0), y, z)  -> x >> (XLEN - 1) & (y - z) + z
     // (select (x >= 0), y, z) -> x >> (XLEN - 1) & (z - y) + y
     if (!Subtarget.hasShortForwardBranchOpt() && isa<ConstantSDNode>(TrueV) &&

llvm/test/CodeGen/RISCV/select.ll

 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
+define i16 @select_xor_3(i16 %A, i8 %cond) {
+; RV32-LABEL: select_xor_3:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a1, a1, 1
+; RV32-NEXT:    addi a1, a1, -1
+; RV32-NEXT:    andi a1, a1, 43
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_xor_3:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a1, a1, 1
+; NOCONDOPS-NEXT:    addiw a1, a1, -1
+; NOCONDOPS-NEXT:    andi a1, a1, 43
+; NOCONDOPS-NEXT:    xor a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_xor_3:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a1, a1, 1
+; CONDOPS-NEXT:    seqz a1, a1
+; CONDOPS-NEXT:    li a2, 43
+; CONDOPS-NEXT:    vt.maskc a1, a2, a1
+; CONDOPS-NEXT:    xor a0, a0, a1
+; CONDOPS-NEXT:    ret
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp eq i8 %and, 0
+ %0 = xor i16 %A, 43
+ %1 = select i1 %cmp10, i16 %0, i16 %A
+ ret i16 %1
+}
+
+; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
+; icmp eq (and %cond, 1), 0
+define i16 @select_xor_3b(i16 %A, i8 %cond) {
+; RV32-LABEL: select_xor_3b:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a1, a1, 1
+; RV32-NEXT:    addi a1, a1, -1
+; RV32-NEXT:    andi a1, a1, 43
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_xor_3b:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a1, a1, 1
+; NOCONDOPS-NEXT:    addiw a1, a1, -1
+; NOCONDOPS-NEXT:    andi a1, a1, 43
+; NOCONDOPS-NEXT:    xor a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_xor_3b:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a1, a1, 1
+; CONDOPS-NEXT:    li a2, 43
+; CONDOPS-NEXT:    vt.maskcn a1, a2, a1
+; CONDOPS-NEXT:    xor a0, a0, a1
+; CONDOPS-NEXT:    ret
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp ne i8 %and, 1
+ %0 = xor i16 %A, 43
+ %1 = select i1 %cmp10, i16 %0, i16 %A
+ ret i16 %1
+}
+
+define i32 @select_xor_4(i32 %A, i32 %B, i8 %cond) {
+; RV32-LABEL: select_xor_4:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    addi a2, a2, -1
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_xor_4:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    addi a2, a2, -1
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    xor a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_xor_4:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    seqz a2, a2
+; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    xor a0, a0, a1
+; CONDOPS-NEXT:    ret
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp eq i8 %and, 0
+ %0 = xor i32 %B, %A
+ %1 = select i1 %cmp10, i32 %0, i32 %A
+ ret i32 %1
+}
+
+; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
+; icmp eq (and %cond, 1), 0
+define i32 @select_xor_4b(i32 %A, i32 %B, i8 %cond) {
+; RV32-LABEL: select_xor_4b:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    addi a2, a2, -1
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_xor_4b:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    addi a2, a2, -1
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    xor a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_xor_4b:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
+; CONDOPS-NEXT:    xor a0, a0, a1
+; CONDOPS-NEXT:    ret
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp ne i8 %and, 1
+ %0 = xor i32 %B, %A
+ %1 = select i1 %cmp10, i32 %0, i32 %A
+ ret i32 %1
+}
+
 define i32 @select_or(i32 %A, i32 %B, i8 %cond) {
 ; RV32-LABEL: select_or:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    slli a2, a2, 31
 ; RV32-NEXT:    srai a2, a2, 31
 ; RV32-NEXT:    and a1, a2, a1
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    ret

 entry:
  %and = and i32 %cond, 1
  %cmp10 = icmp ne i32 %and, 1
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
+define i32 @select_or_2(i32 %A, i32 %B, i8 %cond) {
+; RV32-LABEL: select_or_2:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    addi a2, a2, -1
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_or_2:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    addi a2, a2, -1
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    or a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_or_2:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    seqz a2, a2
+; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    or a0, a0, a1
+; CONDOPS-NEXT:    ret
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp eq i8 %and, 0
+ %0 = or i32 %B, %A
+ %1 = select i1 %cmp10, i32 %0, i32 %A
+ ret i32 %1
+}
+
+; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
+; icmp eq (and %cond, 1), 0
+define i32 @select_or_2b(i32 %A, i32 %B, i8 %cond) {
+; RV32-LABEL: select_or_2b:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    addi a2, a2, -1
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_or_2b:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    addi a2, a2, -1
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    or a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_or_2b:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
+; CONDOPS-NEXT:    or a0, a0, a1
+; CONDOPS-NEXT:    ret
+entry:
+ %and = and i8 %cond, 1
+ %cmp10 = icmp ne i8 %and, 1
+ %0 = or i32 %B, %A
+ %1 = select i1 %cmp10, i32 %0, i32 %A
+ ret i32 %1
+}
+
+define i32 @select_or_3(i32 %A, i32 %B, i32 %cond) {
+; RV32-LABEL: select_or_3:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    addi a2, a2, -1
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_or_3:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    addi a2, a2, -1
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    or a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_or_3:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    seqz a2, a2
+; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    or a0, a0, a1
+; CONDOPS-NEXT:    ret
+entry:
+ %and = and i32 %cond, 1
+ %cmp10 = icmp eq i32 %and, 0
+ %0 = or i32 %B, %A
+ %1 = select i1 %cmp10, i32 %0, i32 %A
+ ret i32 %1
+}
+
+; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
+; icmp eq (and %cond, 1), 0
+define i32 @select_or_3b(i32 %A, i32 %B, i32 %cond) {
+; RV32-LABEL: select_or_3b:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    addi a2, a2, -1
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_or_3b:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    addi a2, a2, -1
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    or a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_or_3b:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
+; CONDOPS-NEXT:    or a0, a0, a1
+; CONDOPS-NEXT:    ret
+entry:
+ %and = and i32 %cond, 1
+ %cmp10 = icmp ne i32 %and, 1
+ %0 = or i32 %B, %A
+ %1 = select i1 %cmp10, i32 %0, i32 %A
+ ret i32 %1
+}
+
 define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_add_1:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    beqz a0, .LBB8_2
+; RV32-NEXT:    beqz a0, .LBB16_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    add a2, a1, a2
-; RV32-NEXT:  .LBB8_2: # %entry
+; RV32-NEXT:  .LBB16_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_add_1:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    beqz a0, .LBB8_2
+; NOCONDOPS-NEXT:    beqz a0, .LBB16_2
 ; NOCONDOPS-NEXT:  # %bb.1:
 ; NOCONDOPS-NEXT:    addw a2, a1, a2
-; NOCONDOPS-NEXT:  .LBB8_2: # %entry
+; NOCONDOPS-NEXT:  .LBB16_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a2
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_add_1:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    addw a1, a1, a2
 ; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; CONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; CONDOPS-NEXT:    or a0, a0, a2
 ; CONDOPS-NEXT:    ret
 entry:
   %c = add i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_add_2:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB9_2
+; RV32-NEXT:    bnez a0, .LBB17_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    add a1, a1, a2
-; RV32-NEXT:  .LBB9_2: # %entry
+; RV32-NEXT:  .LBB17_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_add_2:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB9_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB17_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    addw a1, a1, a2
-; NOCONDOPS-NEXT:  .LBB9_2: # %entry
+; NOCONDOPS-NEXT:  .LBB17_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_add_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    addw a2, a1, a2
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; CONDOPS-NEXT:    or a0, a1, a0
 ; CONDOPS-NEXT:    ret
 entry:
   %c = add i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_add_3(i1 zeroext %cond, i32 %a) {
 ; RV32-LABEL: select_add_3:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB10_2
+; RV32-NEXT:    bnez a0, .LBB18_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    addi a1, a1, 42
-; RV32-NEXT:  .LBB10_2: # %entry
+; RV32-NEXT:  .LBB18_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_add_3:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB10_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB18_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    addiw a1, a1, 42
-; NOCONDOPS-NEXT:  .LBB10_2: # %entry
+; NOCONDOPS-NEXT:  .LBB18_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_add_3:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    addiw a2, a1, 42
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; CONDOPS-NEXT:    or a0, a1, a0
 ; CONDOPS-NEXT:    ret
 entry:
   %c = add i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_sub_1:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    beqz a0, .LBB11_2
+; RV32-NEXT:    beqz a0, .LBB19_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sub a2, a1, a2
-; RV32-NEXT:  .LBB11_2: # %entry
+; RV32-NEXT:  .LBB19_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_sub_1:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    beqz a0, .LBB11_2
+; NOCONDOPS-NEXT:    beqz a0, .LBB19_2
 ; NOCONDOPS-NEXT:  # %bb.1:
 ; NOCONDOPS-NEXT:    subw a2, a1, a2
-; NOCONDOPS-NEXT:  .LBB11_2: # %entry
+; NOCONDOPS-NEXT:  .LBB19_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a2
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_sub_1:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    subw a1, a1, a2
 ; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; CONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; CONDOPS-NEXT:    or a0, a0, a2
 ; CONDOPS-NEXT:    ret
 entry:
   %c = sub i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_sub_2:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB12_2
+; RV32-NEXT:    bnez a0, .LBB20_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sub a1, a1, a2
-; RV32-NEXT:  .LBB12_2: # %entry
+; RV32-NEXT:  .LBB20_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_sub_2:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB12_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB20_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    subw a1, a1, a2
-; NOCONDOPS-NEXT:  .LBB12_2: # %entry
+; NOCONDOPS-NEXT:  .LBB20_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_sub_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    subw a2, a1, a2
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; CONDOPS-NEXT:    or a0, a1, a0
 ; CONDOPS-NEXT:    ret
 entry:
   %c = sub i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_sub_3(i1 zeroext %cond, i32 %a) {
 ; RV32-LABEL: select_sub_3:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB13_2
+; RV32-NEXT:    bnez a0, .LBB21_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    addi a1, a1, -42
-; RV32-NEXT:  .LBB13_2: # %entry
+; RV32-NEXT:  .LBB21_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_sub_3:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB13_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB21_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    addiw a1, a1, -42
-; NOCONDOPS-NEXT:  .LBB13_2: # %entry
+; NOCONDOPS-NEXT:  .LBB21_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_sub_3:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    addiw a2, a1, -42
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; CONDOPS-NEXT:    or a0, a1, a0
 ; CONDOPS-NEXT:    ret
 entry:
   %c = sub i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_and_1:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    beqz a0, .LBB14_2
+; RV32-NEXT:    beqz a0, .LBB22_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    and a2, a1, a2
-; RV32-NEXT:  .LBB14_2: # %entry
+; RV32-NEXT:  .LBB22_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_and_1:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    beqz a0, .LBB14_2
+; NOCONDOPS-NEXT:    beqz a0, .LBB22_2
 ; NOCONDOPS-NEXT:  # %bb.1:
 ; NOCONDOPS-NEXT:    and a2, a1, a2
-; NOCONDOPS-NEXT:  .LBB14_2: # %entry
+; NOCONDOPS-NEXT:  .LBB22_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a2
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_and_1:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; CONDOPS-NEXT:    and a1, a2, a1
 ; CONDOPS-NEXT:    or a0, a1, a0
 ; CONDOPS-NEXT:    ret
 entry:
   %c = and i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_and_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_and_2:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB15_2
+; RV32-NEXT:    bnez a0, .LBB23_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:  .LBB15_2: # %entry
+; RV32-NEXT:  .LBB23_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_and_2:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB15_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB23_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    and a1, a1, a2
-; NOCONDOPS-NEXT:  .LBB15_2: # %entry
+; NOCONDOPS-NEXT:  .LBB23_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_and_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; CONDOPS-NEXT:    and a1, a1, a2
 ; CONDOPS-NEXT:    or a0, a1, a0
 ; CONDOPS-NEXT:    ret
 entry:
   %c = and i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_and_3(i1 zeroext %cond, i32 %a) {
 ; RV32-LABEL: select_and_3:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB16_2
+; RV32-NEXT:    bnez a0, .LBB24_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    andi a1, a1, 42
-; RV32-NEXT:  .LBB16_2: # %entry
+; RV32-NEXT:  .LBB24_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_and_3:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB16_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB24_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    andi a1, a1, 42
-; NOCONDOPS-NEXT:  .LBB16_2: # %entry
+; NOCONDOPS-NEXT:  .LBB24_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_and_3:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; CONDOPS-NEXT:    li a2, 42
 ; CONDOPS-NEXT:    and a1, a1, a2
 ; CONDOPS-NEXT:    or a0, a1, a0
 ; CONDOPS-NEXT:    ret
 entry:
   %c = and i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_udiv_1:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    beqz a0, .LBB17_2
+; RV32-NEXT:    beqz a0, .LBB25_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    divu a2, a1, a2
-; RV32-NEXT:  .LBB17_2: # %entry
+; RV32-NEXT:  .LBB25_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_udiv_1:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    beqz a0, .LBB17_2
+; NOCONDOPS-NEXT:    beqz a0, .LBB25_2
 ; NOCONDOPS-NEXT:  # %bb.1:
 ; NOCONDOPS-NEXT:    divuw a2, a1, a2
-; NOCONDOPS-NEXT:  .LBB17_2: # %entry
+; NOCONDOPS-NEXT:  .LBB25_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a2
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_udiv_1:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    divuw a1, a1, a2
 ; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; CONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; CONDOPS-NEXT:    or a0, a0, a2
 ; CONDOPS-NEXT:    ret
 entry:
   %c = udiv i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_udiv_2:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB18_2
+; RV32-NEXT:    bnez a0, .LBB26_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    divu a1, a1, a2
-; RV32-NEXT:  .LBB18_2: # %entry
+; RV32-NEXT:  .LBB26_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_udiv_2:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB18_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB26_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    divuw a1, a1, a2
-; NOCONDOPS-NEXT:  .LBB18_2: # %entry
+; NOCONDOPS-NEXT:  .LBB26_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_udiv_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    divuw a2, a1, a2
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; CONDOPS-NEXT:    or a0, a1, a0
 ; CONDOPS-NEXT:    ret
 entry:
   %c = udiv i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) {
 ; RV32-LABEL: select_udiv_3:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB19_2
+; RV32-NEXT:    bnez a0, .LBB27_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    srli a1, a1, 1
 ; RV32-NEXT:    lui a0, 199729
 ; RV32-NEXT:    addi a0, a0, -975
 ; RV32-NEXT:    mulhu a1, a1, a0
 ; RV32-NEXT:    srli a1, a1, 2
-; RV32-NEXT:  .LBB19_2: # %entry
+; RV32-NEXT:  .LBB27_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_udiv_3:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB19_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB27_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    srliw a0, a1, 1
 ; NOCONDOPS-NEXT:    lui a1, 199729
 ; NOCONDOPS-NEXT:    addiw a1, a1, -975
 ; NOCONDOPS-NEXT:    mul a1, a0, a1
 ; NOCONDOPS-NEXT:    srli a1, a1, 34
-; NOCONDOPS-NEXT:  .LBB19_2: # %entry
+; NOCONDOPS-NEXT:  .LBB27_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_udiv_3:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    srliw a2, a1, 1
 ; CONDOPS-NEXT:    lui a3, 199729
 ; CONDOPS-NEXT:    addiw a3, a3, -975
 ; CONDOPS-NEXT:    mul a2, a2, a3
 ; CONDOPS-NEXT:    srli a2, a2, 34
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
 ; CONDOPS-NEXT:    or a0, a1, a0
 ; CONDOPS-NEXT:    ret
 entry:
   %c = udiv i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_shl_1:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    beqz a0, .LBB20_2
+; RV32-NEXT:    beqz a0, .LBB28_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sll a2, a1, a2
-; RV32-NEXT:  .LBB20_2: # %entry
+; RV32-NEXT:  .LBB28_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_shl_1:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    beqz a0, .LBB20_2
+; NOCONDOPS-NEXT:    beqz a0, .LBB28_2
 ; NOCONDOPS-NEXT:  # %bb.1:
 ; NOCONDOPS-NEXT:    sllw a2, a1, a2
-; NOCONDOPS-NEXT:  .LBB20_2: # %entry
+; NOCONDOPS-NEXT:  .LBB28_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a2
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_shl_1:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    sllw a1, a1, a2
 ; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; CONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; CONDOPS-NEXT:    or a0, a0, a2
 ; CONDOPS-NEXT:    ret
 entry:
   %c = shl i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_shl_2:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB21_2
+; RV32-NEXT:    bnez a0, .LBB29_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sll a1, a1, a2
-; RV32-NEXT:  .LBB21_2: # %entry
+; RV32-NEXT:  .LBB29_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_shl_2:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB21_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB29_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    sllw a1, a1, a2
-; NOCONDOPS-NEXT:  .LBB21_2: # %entry
+; NOCONDOPS-NEXT:  .LBB29_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_shl_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    sllw a2, a1, a2
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
entry:
   %c = shl i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_ashr_1:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    beqz a0, .LBB23_2
+; RV32-NEXT:    beqz a0, .LBB31_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sra a2, a1, a2
-; RV32-NEXT:  .LBB23_2: # %entry
+; RV32-NEXT:  .LBB31_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_ashr_1:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    beqz a0, .LBB23_2
+; NOCONDOPS-NEXT:    beqz a0, .LBB31_2
 ; NOCONDOPS-NEXT:  # %bb.1:
 ; NOCONDOPS-NEXT:    sraw a2, a1, a2
-; NOCONDOPS-NEXT:  .LBB23_2: # %entry
+; NOCONDOPS-NEXT:  .LBB31_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a2
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_ashr_1:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    sraw a1, a1, a2
 ; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; CONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; CONDOPS-NEXT:    or a0, a0, a2
 ; CONDOPS-NEXT:    ret
 entry:
   %c = ashr i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_ashr_2:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB24_2
+; RV32-NEXT:    bnez a0, .LBB32_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sra a1, a1, a2
-; RV32-NEXT:  .LBB24_2: # %entry
+; RV32-NEXT:  .LBB32_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_ashr_2:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB24_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB32_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    sraw a1, a1, a2
-; NOCONDOPS-NEXT:  .LBB24_2: # %entry
+; NOCONDOPS-NEXT:  .LBB32_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_ashr_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    sraw a2, a1, a2
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
entry:
   %c = ashr i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_lshr_1:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    beqz a0, .LBB26_2
+; RV32-NEXT:    beqz a0, .LBB34_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    srl a2, a1, a2
-; RV32-NEXT:  .LBB26_2: # %entry
+; RV32-NEXT:  .LBB34_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_lshr_1:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    beqz a0, .LBB26_2
+; NOCONDOPS-NEXT:    beqz a0, .LBB34_2
 ; NOCONDOPS-NEXT:  # %bb.1:
 ; NOCONDOPS-NEXT:    srlw a2, a1, a2
-; NOCONDOPS-NEXT:  .LBB26_2: # %entry
+; NOCONDOPS-NEXT:  .LBB34_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a2
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_lshr_1:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    srlw a1, a1, a2
 ; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
 ; CONDOPS-NEXT:    vt.maskc a0, a1, a0
 ; CONDOPS-NEXT:    or a0, a0, a2
 ; CONDOPS-NEXT:    ret
 entry:
   %c = lshr i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_lshr_2:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    bnez a0, .LBB27_2
+; RV32-NEXT:    bnez a0, .LBB35_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    srl a1, a1, a2
-; RV32-NEXT:  .LBB27_2: # %entry
+; RV32-NEXT:  .LBB35_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; NOCONDOPS-LABEL: select_lshr_2:
 ; NOCONDOPS:       # %bb.0: # %entry
-; NOCONDOPS-NEXT:    bnez a0, .LBB27_2
+; NOCONDOPS-NEXT:    bnez a0, .LBB35_2
 ; NOCONDOPS-NEXT:  # %bb.1: # %entry
 ; NOCONDOPS-NEXT:    srlw a1, a1, a2
-; NOCONDOPS-NEXT:  .LBB27_2: # %entry
+; NOCONDOPS-NEXT:  .LBB35_2: # %entry
 ; NOCONDOPS-NEXT:    mv a0, a1
 ; NOCONDOPS-NEXT:    ret
 ;
 ; CONDOPS-LABEL: select_lshr_2:
 ; CONDOPS:       # %bb.0: # %entry
 ; CONDOPS-NEXT:    srlw a2, a1, a2
 ; CONDOPS-NEXT:    vt.maskc a1, a1, a0
 ; CONDOPS-NEXT:    vt.maskcn a0, a2, a0