InstCombine: Fold and (fcmp), (is.fpclass) into is.fpclass

[arsenm]

Summary

Fold class test performed by an fcmp into another class. For now this
avoids introducing new class calls then there isn't one that already
exists.

[foad]

Looks pretty clean to me overall.

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1243 ↗

(On Diff #479367)

Using != in the comment is misleading since that is true for nans. Maybe use <> instead or just spell out what you mean.

1276 ↗

(On Diff #479367)

fcNan | is redundant here.

1351 ↗

(On Diff #479367)

Do you need to worry about IsLogicalSelect here? (@nikic, @craig.topper?)

[arsenm]

Resplit the patches differently. For now, only handle fcmp+is.fpclass case, such that it will not introduce is.fpclass in situations it didn't already exist. If we have 2 or more compares that can turn into a class, I think we should introduce them after codegen is improved a bit for it.

[arsenm]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1243 ↗

(On Diff #479367)

It's not misleading, that this is true for nans is the point. It's the negation of the usual syntactic ordered compare

[foad]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1243 ↗

(On Diff #479367)

This comment is misleading: case FCmpInst::FCMP_UEQ: // match !(x != 0.0)

!(x != 0.0) (in C) is the same as x == 0.0 (in C) which is OEQ not UEQ.

[arsenm]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1243 ↗

(On Diff #479367)

No, they aren't the same in C. This whole conversation is why this comment is necessary

https://alive2.llvm.org/ce/z/gtzLUh

[arsenm]

Add more comments

[foad]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1243 ↗

(On Diff #479367)

Yes they are the same in C: https://godbolt.org/z/1rq9GTjEM

!= in C is UNE not ONE.

[arsenm]

Comments

[sepavloff]

Some mechanism must exists that applies this transformation or not depending on target. If instruction FCLASS is available, the transformation is profitable. But on targets that do not have such instruction, the replacement may produce inefficient code.

Also it is desirable to have a codegen test for target without FCLASS instruction (like x86), to check if the code generated for such comparisons does not become worse.

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1231–1236 ↗

(On Diff #482498)

These checks should be made for more general case:

• LHS is same as RHS,
• RHS is a constant,

as you mention is the comment above.

1257 ↗

(On Diff #482498)

Is this comment relevant? This block executes for une, not ueq?

1263 ↗

(On Diff #482498)

Is this comparison always false?

1282 ↗

(On Diff #482498)

oeq seems irrelevant in this block.

1323–1324 ↗

(On Diff #482498)

1325–1326 ↗

(On Diff #482498)

1340 ↗

(On Diff #482498)

1342 ↗

(On Diff #482498)

[arsenm]

Comment fixes

[arsenm]

In D139130#3995198, @sepavloff wrote:

Some mechanism must exists that applies this transformation or not depending on target. If instruction FCLASS is available, the transformation is profitable. But on targets that do not have such instruction, the replacement may produce inefficient code.

If you're doing 2 or more checks I think is.fpclass is a better canonical form so it doesn't matter what the target prefers, that's a lowering issue. This patch holds off on introducing new classes because we have a bit of codegen improvement to do. I don't think that should block this patch,
since if you're already using class you've already signed up for not-ideal codegen.

Also it is desirable to have a codegen test for target without FCLASS instruction (like x86), to check if the code generated for such comparisons does not become worse.

We already have fpclass legalization tests. I'll add more when I get to the codegen improvements (mostly we're missing all the cases where it can be converted back to FP compares, it only handles a couple of them. Plus it's mishandling denormals with DAZ)

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1231–1236 ↗

(On Diff #482498)

I don't know if it really should. The more non-canonical forms we try to match, the more edge cases that we won't actually encounter and won't have testing for.

1263 ↗

(On Diff #482498)

No, this is the same as fcmp ord

[arsenm]

Rebase

[sepavloff]

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

829–843

Replacement of llvm.is_fpclass with comparison hides class checks and make analysis of code passes harder. Does it have any benefit over creation of the comparison in selector?

[arsenm]

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

829–843

Using fcmp makes analysis easier. fcmp has fewer constraints, and will always be better understood by generic passes than a special case intrinsic. It's a better canonical form; otherwise every single place that considers compares would have to perform the exact same checks for a class that performs a compare.

I also just noticed when I rebased I attached the wrong patch here.

[arsenm]

Attach correct patch

[arsenm]

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

829–843

fcmp also supports fast math flags, class does not

[sepavloff]

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

829–835

is_fpclass should not be replaced by compare instruction otherwise it can break valid programs. Consider the code:

define i1 @check_isnan(float %x) strictfp {
  %call = call i1 @func_isnan(float %x)
  ret i1 %call
}

define i1 @func_isnan(float %x) "always_inline" {
entry:
  %call = i1 call @llvm.is.fpclass.f32(float %x, i32 3)
  ret i1 %call
}

if InstCombiner replaces the call of @llvm.is.fpclass.f32 with fcmp uno, then during inlining fcmp is replaced with a call to @llvm.experimental.constrained.fcmp.f32, which has different behavior than is_fpclass.

[sepavloff]

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

829–843

is_fpclass does not produce float value, fast math flags does not make sense for it.

[arsenm]

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

829–835

How is it different? If there's a difference in behavior, there's an inliner bug. We have separate constrained.fcmp and constrained.fcmps for compares which may or may not signal

829–843

Fast math flags apply to the inputs and outputs, which is one of the problems with them. fcmp nnan can trivially fold to true/false for example

[jcranmer-intel]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1300–1303 ↗

(On Diff #484213)

This block is handling fcmp une, so these latter 4 cases should be using fcmp une.

1319–1321 ↗

(On Diff #484213)

1323 ↗

(On Diff #484213)

You're missing 4 examples here--one with +inf and ueq with -inf.

[arsenm]

Try to get the comments right again

[arsenm]

ping

[foad]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1259 ↗

(On Diff #484388)

Remove the #if 0 block, just leave a TODO.

1271 ↗

(On Diff #484388)

What does "would" mean here?

1298 ↗

(On Diff #484388)

Should be is_fpclass x, 0 aka false.

1303 ↗

(On Diff #484388)

Should be is_fpclass x, ~0 aka true.

1308 ↗

(On Diff #484388)

Should be Mask = 0.

Can you imagine any way of fixing the FIXME? If not I wouldn't bother marking it as FIXME.

1349 ↗

(On Diff #484388)

Simpler to write this as fcFinite|fcNegInf, as on the line below.

1522–1523 ↗

(On Diff #484388)

Can remove one of the many sets of parens here.

1319–1321 ↗

(On Diff #484213)

Agree with @jcranmer-intel. It looks like you might have "fixed" the wrong line here?

[arsenm]

Address comments

[arsenm]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1308 ↗

(On Diff #484388)

This was mostly for me when I was trying to make sure all the paths were tested. I think it's even harder now that I did the fneg/fabs fold into the test mask combine

1282 ↗

(On Diff #482498)

it's relevant but now moved to the other patch for zero handling

[foad]

LGTM with comment fixes

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1310–1313 ↗

(On Diff #495186)

1339 ↗

(On Diff #495186)

Simplify like the line below

[arsenm]

9ad6bdd7470aba542a7599ef9845d17d84fb7ed6

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1349 ↗

(On Diff #484388)

Not sure where this comment is pointing anymore

[foad]

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

1349 ↗

(On Diff #484388)

Line 1339 in the current patch. I left a later comment saying the same thing with suggested diff.

llvm/include/llvm/IR/IRBuilder.h

public:
   }
 
   /// Return a boolean value testing if \p Arg > -1.
   Value *CreateIsNotNeg(Value *Arg, const Twine &Name = "") {
     return CreateICmpSGT(Arg, ConstantInt::getAllOnesValue(Arg->getType()),
                          Name);
   }
 
+  /// Return a boolean value testing if \p Arg is a NaN.
+  Value *CreateIsNaN(Value *Arg, const Twine &Name = "") {
+    return CreateFCmpUNO(Arg, ConstantFP::getZero(Arg->getType()), Name);
+  }
+
   /// Return the i64 difference between two pointer values, dividing out
   /// the size of the pointed-to objects.
   ///
   /// This is intended to implement C-style pointer subtraction. As such, the
   /// pointers must be appropriately aligned for their element types and
   /// pointing into the same object.
   Value *CreatePtrDiff(Type *ElemTy, Value *LHS, Value *RHS,
                        const Twine &Name = "");

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

InstCombinerImpl::foldIntrinsicWithOverflowCommon(IntrinsicInst *II) {
   Value *OperationResult = nullptr;
   Constant *OverflowResult = nullptr;
   if (OptimizeOverflowCheck(WO->getBinaryOp(), WO->isSigned(), WO->getLHS(),
                             WO->getRHS(), *WO, OperationResult, OverflowResult))
     return createOverflowTuple(WO, OperationResult, OverflowResult);
   return nullptr;
 }
 
+Instruction *InstCombinerImpl::foldIntrinsicIsFPClass(IntrinsicInst &II) {
+  Value *Src0 = II.getArgOperand(0);
+  Value *Src1 = II.getArgOperand(1);
+  const ConstantInt *CMask = cast<ConstantInt>(Src1);
+  uint32_t Mask = CMask->getZExtValue();
+  const bool IsStrict = II.isStrictFP();
+
+  if (Mask == fcNan && !IsStrict) {
+    // Equivalent of isnan. Replace with standard fcmp if we don't care about FP
+    // exceptions.
+    Value *FCmp = Builder.CreateIsNaN(Src0);
+    FCmp->takeName(&II);
+    return replaceInstUsesWith(II, FCmp);
+  }
+
+  if (Mask == (~fcNan & fcAllFlags) && !IsStrict) {
+    // Equivalent of !isnan. Replace with standard fcmp.
+    Value *FCmp =
+        Builder.CreateFCmpORD(Src0, ConstantFP::getZero(Src0->getType()));
+    FCmp->takeName(&II);
+    return replaceInstUsesWith(II, FCmp);
+  }
+
+  // fp_class (nnan x), qnan|snan|other -> fp_class (nnan x), other
+  if ((Mask & fcNan) && isKnownNeverNaN(Src0, &getTargetLibraryInfo())) {
+    II.setArgOperand(1, ConstantInt::get(Src1->getType(), Mask & ~fcNan));
+    return &II;
+  }
+
+  // fp_class (nnan x), ~(qnan|snan) -> true
+  if (Mask == (~fcNan & fcAllFlags) &&
+      isKnownNeverNaN(Src0, &getTargetLibraryInfo())) {
+    return replaceInstUsesWith(II, ConstantInt::get(II.getType(), true));
+  }
+
+  return nullptr;
+}
+
 static std::optional<bool> getKnownSign(Value *Op, Instruction *CxtI,
-                                        const DataLayout &DL,
-                                        AssumptionCache *AC,
-                                        DominatorTree *DT) {
+                                   const DataLayout &DL, AssumptionCache *AC,
   KnownBits Known = computeKnownBits(Op, DL, 0, AC, CxtI, DT);
   if (Known.isNonNegative())
     return false;
   if (Known.isNegative())
     return true;
 
   Value *X, *Y;
   if (match(Op, m_NSWSub(m_Value(X), m_Value(Y))))
case Intrinsic::vector_reduce_fmul: {
     // Can remove shuffle iff just shuffled elements, no repeats, undefs, or
     // other changes.
     if (UsedIndices.all()) {
       replaceUse(II->getOperandUse(ArgIdx), V);
       return nullptr;
     }
     break;
   }
+  case Intrinsic::is_fpclass: {
+    if (Instruction *I = foldIntrinsicIsFPClass(*II))
+      return I;
+    break;
+  }
   default: {
     // Handle target specific intrinsics
     std::optional<Instruction *> V = targetInstCombineIntrinsic(*II);
     if (V)
       return *V;
     break;
   }
   }

llvm/lib/Transforms/InstCombine/InstCombineInternal.h

private:
   Value *foldAndOrOfICmpsOfAndWithPow2(ICmpInst *LHS, ICmpInst *RHS,
                                        Instruction *CxtI, bool IsAnd,
                                        bool IsLogical = false);
   Value *matchSelectFromAndOr(Value *A, Value *B, Value *C, Value *D);
   Value *getSelectCondition(Value *A, Value *B);
 
   Instruction *foldExtractOfOverflowIntrinsic(ExtractValueInst &EV);
   Instruction *foldIntrinsicWithOverflowCommon(IntrinsicInst *II);
+  Instruction *foldIntrinsicIsFPClass(IntrinsicInst &II);
   Instruction *foldFPSignBitOps(BinaryOperator &I);
   Instruction *foldFDivConstantDivisor(BinaryOperator &I);
 
   // Optimize one of these forms:
   //   and i1 Op, SI / select i1 Op, i1 SI, i1 false (if IsAnd = true)
   //   or i1 Op, SI  / select i1 Op, i1 true, i1 SI  (if IsAnd = false)
   // into simplier select instruction using isImpliedCondition.
   Instruction *foldAndOrOfSelectUsingImpliedCond(Value *Op, SelectInst &SI,

llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll

;
   store i1 %class, ptr %ptr
   %or = or i1 %oeq.inf, %class
   ret i1 %or
 }
 
 ; -> true
 define i1 @fcmp_ord_or_class_isnan(half %x) {
 ; CHECK-LABEL: @fcmp_ord_or_class_isnan(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 3)
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[ORD]], [[CLASS]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    ret i1 true
 ;
   %ord = fcmp ord half %x, 0.0
   %class = call i1 @llvm.is.fpclass.f16(half %x, i32 3)
   %or = or i1 %ord, %class
   ret i1 %or
 }
 
 define i1 @fcmp_ord_or_class_isnan_wrong_operand(half %x, half %y) {
 ; CHECK-LABEL: @fcmp_ord_or_class_isnan_wrong_operand(
 ; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[Y:%.*]], i32 3)
+; CHECK-NEXT:    [[CLASS:%.*]] = fcmp uno half [[Y:%.*]], 0xH0000
 ; CHECK-NEXT:    [[OR:%.*]] = or i1 [[ORD]], [[CLASS]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %ord = fcmp ord half %x, 0.0
   %class = call i1 @llvm.is.fpclass.f16(half %y, i32 3)
   %or = or i1 %ord, %class
   ret i1 %or
 }
 
 ; -> false
 define i1 @fcmp_ord_and_class_isnan(half %x) {
 ; CHECK-LABEL: @fcmp_ord_and_class_isnan(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X]], i32 3)
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[CLASS]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    ret i1 false
 ;
   %ord = fcmp ord half %x, 0.0
   %class = call i1 @llvm.is.fpclass.f16(half %x, i32 3)
   %and = and i1 %ord, %class
   ret i1 %and
 }
 
 ; -> true
 define i1 @fcmp_ord_or_class_isnan_commute(half %x) {
 ; CHECK-LABEL: @fcmp_ord_or_class_isnan_commute(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 3)
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[CLASS]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[OR]]
+; CHECK-NEXT:    ret i1 true
 ;
   %class = call i1 @llvm.is.fpclass.f16(half %x, i32 3)
   %ord = fcmp ord half %x, 0.0
   %or = or i1 %class, %ord
   ret i1 %or
 }
 
 ; -> false
 define i1 @fcmp_ord_and_class_isnan_commute(half %x) {
 ; CHECK-LABEL: @fcmp_ord_and_class_isnan_commute(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 3)
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; CHECK-NEXT:    [[AND:%.*]] = and i1 [[CLASS]], [[ORD]]
-; CHECK-NEXT:    ret i1 [[AND]]
+; CHECK-NEXT:    ret i1 false
 ;
   %class = call i1 @llvm.is.fpclass.f16(half %x, i32 3)
   %ord = fcmp ord half %x, 0.0
   %and = and i1 %class, %ord
   ret i1 %and
 }
 
 define i1 @fcmp_isfinite_and_class_subnormal(half %x) {

llvm/test/Transforms/InstCombine/is_fpclass.ll

 ; FIXME: Should this really be immarg?
 ; define i1 @test_class_var_mask_f32(float %x, i32 %mask) {
 ;   %val = call i1 @llvm.is.fpclass.f32(float %x, i32 %mask)
 ;   ret i1 %val
 ; }
 
 define i1 @test_class_isnan_f32(float %x) {
 ; CHECK-LABEL: @test_class_isnan_f32(
-; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3)
+; CHECK-NEXT:    [[VAL:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[VAL]]
 ;
   %val = call i1 @llvm.is.fpclass.f32(float %x, i32 3)
   ret i1 %val
 }
 
+define <2 x i1> @test_class_isnan_v2f32(<2 x float> %x) {
+; CHECK-LABEL: @test_class_isnan_v2f32(
+; CHECK-NEXT:    [[VAL:%.*]] = fcmp uno <2 x float> [[X:%.*]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[VAL]]
+;
+  %val = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 3)
+  ret <2 x i1> %val
+}
+
 define i1 @test_class_isnan_f32_strict(float %x) {
 ; CHECK-LABEL: @test_class_isnan_f32_strict(
 ; CHECK-NEXT:    [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3) #[[ATTR2:[0-9]+]]
 ; CHECK-NEXT:    ret i1 [[VAL]]
 ;
   %val = call i1 @llvm.is.fpclass.f32(float %x, i32 3) strictfp
   ret i1 %val
 }

 ; CHECK-NEXT:    ret i1 false
 ;
   %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 512)
   ret i1 %val
 }
 
 define i1 @test_class_is_snan_nnan_src(float %x) {
 ; CHECK-LABEL: @test_class_is_snan_nnan_src(
-; CHECK-NEXT:    [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 1)
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    ret i1 false
 ;
   %nnan = fadd nnan float %x, 1.0
   %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 1)
   ret i1 %class
 }
 
 define i1 @test_class_is_qnan_nnan_src(float %x) {
 ; CHECK-LABEL: @test_class_is_qnan_nnan_src(
-; CHECK-NEXT:    [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 2)
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    ret i1 false
 ;
   %nnan = fadd nnan float %x, 1.0
   %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 2)
   ret i1 %class
 }
 
 define i1 @test_class_is_nan_nnan_src(float %x) {
 ; CHECK-LABEL: @test_class_is_nan_nnan_src(
-; CHECK-NEXT:    [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 3)
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    ret i1 false
 ;
   %nnan = fadd nnan float %x, 1.0
   %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 3)
   ret i1 %class
 }
 
 define i1 @test_class_is_nan_other_nnan_src(float %x) {
 ; CHECK-LABEL: @test_class_is_nan_other_nnan_src(
 ; CHECK-NEXT:    [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 267)
+; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 264)
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %nnan = fadd nnan float %x, 1.0
   %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 267)
   ret i1 %class
 }
 
 ; Fold test of is not nan
 define i1 @test_class_is_not_nan_nnan_src(float %x) {
 ; CHECK-LABEL: @test_class_is_not_nan_nnan_src(
-; CHECK-NEXT:    [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 1020)
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    ret i1 true
 ;
   %nnan = fadd nnan float %x, 1.0
   %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 1020) ; ~fcNan & fcAllFlags
   ret i1 %class
 }
 
 define i1 @test_class_is_not_nan_nnan_src_strict(float %x) {
 ; CHECK-LABEL: @test_class_is_not_nan_nnan_src_strict(
-; CHECK-NEXT:    [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 1020) #[[ATTR2]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
+; CHECK-NEXT:    ret i1 true
 ;
   %nnan = fadd nnan float %x, 1.0
   %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 1020) strictfp ; ~fcNan & fcAllFlags
   ret i1 %class
 }
 
 ; --------------------------------------------------------------------
 ; llvm.is.fpclass with ninf sources

 }
 
 ; --------------------------------------------------------------------
 ; Negation of llvm.is.fpclass
 ; --------------------------------------------------------------------
 
 define i1 @test_class_not_is_nan(float %x) {
 ; CHECK-LABEL: @test_class_not_is_nan(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 1020)
+; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord float [[X:%.*]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %class = call i1 @llvm.is.fpclass.f32(float %x, i32 3)
   %not = xor i1 %class, true
   ret i1 %not
 }
 
 define i1 @test_class_not_is_nan_multi_use(float %x, ptr %ptr) {
 ; CHECK-LABEL: @test_class_not_is_nan_multi_use(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3)
+; CHECK-NEXT:    [[CLASS:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
 ; CHECK-NEXT:    store i1 [[CLASS]], ptr [[PTR:%.*]], align 1
 ; CHECK-NEXT:    [[NOT:%.*]] = xor i1 [[CLASS]], true
 ; CHECK-NEXT:    ret i1 [[NOT]]
 ;
   %class = call i1 @llvm.is.fpclass.f32(float %x, i32 3)
   store i1 %class, ptr %ptr
   %not = xor i1 %class, true
   ret i1 %not
;
   %class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
   %class1 = fcmp uno float %a, 0.000000e+00
   %or = or i1 %class0, %class1
   ret i1 %or
 }
 
 define i1 @test_fold_or3_class_f32_0(float %a) {
 ; CHECK-LABEL: @test_fold_or3_class_f32_0(
-; CHECK-NEXT:    [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 7)
-; CHECK-NEXT:    ret i1 [[CLASS0]]
+; CHECK-NEXT:    [[CLASS0:%.*]] = fcmp uno float [[A:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CLASS2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 4)
+; CHECK-NEXT:    [[OR_1:%.*]] = or i1 [[CLASS0]], [[CLASS2]]
+; CHECK-NEXT:    ret i1 [[OR_1]]
 ;
   %class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
   %class1 = call i1 @llvm.is.fpclass.f32(float %a, i32 2)
   %class2 = call i1 @llvm.is.fpclass.f32(float %a, i32 4)
   %or.0 = or i1 %class0, %class1
   %or.1 = or i1 %or.0, %class2
   ret i1 %or.1
 }
 
 define i1 @test_fold_or_all_tests_class_f32_0(float %a) {
 ; CHECK-LABEL: @test_fold_or_all_tests_class_f32_0(
-; CHECK-NEXT:    ret i1 true
+; CHECK-NEXT:    [[CLASS0:%.*]] = fcmp uno float [[A:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CLASS2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 4)
+; CHECK-NEXT:    [[CLASS3:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
+; CHECK-NEXT:    [[CLASS4:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 16)
+; CHECK-NEXT:    [[CLASS5:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 32)
+; CHECK-NEXT:    [[CLASS6:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 64)
+; CHECK-NEXT:    [[CLASS7:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 128)
+; CHECK-NEXT:    [[CLASS8:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 256)
+; CHECK-NEXT:    [[CLASS9:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 512)
+; CHECK-NEXT:    [[OR_1:%.*]] = or i1 [[CLASS0]], [[CLASS2]]
+; CHECK-NEXT:    [[OR_2:%.*]] = or i1 [[OR_1]], [[CLASS3]]
+; CHECK-NEXT:    [[OR_3:%.*]] = or i1 [[OR_2]], [[CLASS4]]
+; CHECK-NEXT:    [[OR_4:%.*]] = or i1 [[OR_3]], [[CLASS5]]
+; CHECK-NEXT:    [[OR_5:%.*]] = or i1 [[OR_4]], [[CLASS6]]
+; CHECK-NEXT:    [[OR_6:%.*]] = or i1 [[OR_5]], [[CLASS7]]
+; CHECK-NEXT:    [[OR_7:%.*]] = or i1 [[OR_6]], [[CLASS8]]
+; CHECK-NEXT:    [[OR_8:%.*]] = or i1 [[OR_7]], [[CLASS9]]
+; CHECK-NEXT:    ret i1 [[OR_8]]
 ;
   %class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
   %class1 = call i1 @llvm.is.fpclass.f32(float %a, i32 2)
   %class2 = call i1 @llvm.is.fpclass.f32(float %a, i32 4)
   %class3 = call i1 @llvm.is.fpclass.f32(float %a, i32 8)
   %class4 = call i1 @llvm.is.fpclass.f32(float %a, i32 16)
   %class5 = call i1 @llvm.is.fpclass.f32(float %a, i32 32)
   %class6 = call i1 @llvm.is.fpclass.f32(float %a, i32 64)
;
   %class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
   %class1 = fcmp uno float %a, 0.000000e+00
   %and = and i1 %class0, %class1
   ret i1 %and
 }
 
 define i1 @test_fold_and3_class_f32_0(float %a) {
 ; CHECK-LABEL: @test_fold_and3_class_f32_0(
-; CHECK-NEXT:    [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 2)
-; CHECK-NEXT:    ret i1 [[CLASS0]]
+; CHECK-NEXT:    [[CLASS0:%.*]] = fcmp uno float [[A:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CLASS1:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 2)
+; CHECK-NEXT:    [[CLASS2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 7)
+; CHECK-NEXT:    [[AND_0:%.*]] = and i1 [[CLASS0]], [[CLASS1]]
+; CHECK-NEXT:    [[AND_1:%.*]] = and i1 [[AND_0]], [[CLASS2]]
+; CHECK-NEXT:    ret i1 [[AND_1]]
 ;
   %class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 3)
   %class1 = call i1 @llvm.is.fpclass.f32(float %a, i32 2)
   %class2 = call i1 @llvm.is.fpclass.f32(float %a, i32 7)
   %and.0 = and i1 %class0, %class1
   %and.1 = and i1 %and.0, %class2
   ret i1 %and.1
 }
;
   %and.6 = and i1 %and.5, %class7
   %and.7 = and i1 %and.6, %class8
   %and.8 = and i1 %and.7, %class9
   ret i1 %and.8
 }
 
 define i1 @test_fold_and_not_all_tests_class_f32_0(float %a) {
 ; CHECK-LABEL: @test_fold_and_not_all_tests_class_f32_0(
-; CHECK-NEXT:    ret i1 false
+; CHECK-NEXT:    [[CLASS0:%.*]] = fcmp ord float [[A:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CLASS2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 1019)
+; CHECK-NEXT:    [[CLASS3:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 1015)
+; CHECK-NEXT:    [[CLASS4:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 1007)
+; CHECK-NEXT:    [[CLASS5:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 991)
+; CHECK-NEXT:    [[CLASS6:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 959)
+; CHECK-NEXT:    [[CLASS7:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 895)
+; CHECK-NEXT:    [[CLASS8:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 767)
+; CHECK-NEXT:    [[CLASS9:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 511)
+; CHECK-NEXT:    [[AND_1:%.*]] = and i1 [[CLASS0]], [[CLASS2]]
+; CHECK-NEXT:    [[AND_2:%.*]] = and i1 [[AND_1]], [[CLASS3]]
+; CHECK-NEXT:    [[AND_3:%.*]] = and i1 [[AND_2]], [[CLASS4]]
+; CHECK-NEXT:    [[AND_4:%.*]] = and i1 [[AND_3]], [[CLASS5]]
+; CHECK-NEXT:    [[AND_5:%.*]] = and i1 [[AND_4]], [[CLASS6]]
+; CHECK-NEXT:    [[AND_6:%.*]] = and i1 [[AND_5]], [[CLASS7]]
+; CHECK-NEXT:    [[AND_7:%.*]] = and i1 [[AND_6]], [[CLASS8]]
+; CHECK-NEXT:    [[AND_8:%.*]] = and i1 [[AND_7]], [[CLASS9]]
+; CHECK-NEXT:    ret i1 [[AND_8]]
 ;
   %class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1022)
   %class1 = call i1 @llvm.is.fpclass.f32(float %a, i32 1021)
   %class2 = call i1 @llvm.is.fpclass.f32(float %a, i32 1019)
   %class3 = call i1 @llvm.is.fpclass.f32(float %a, i32 1015)
   %class4 = call i1 @llvm.is.fpclass.f32(float %a, i32 1007)
   %class5 = call i1 @llvm.is.fpclass.f32(float %a, i32 991)
   %class6 = call i1 @llvm.is.fpclass.f32(float %a, i32 959)
;
   %class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
   %class1 = fcmp uno float %a, 0.000000e+00
   %xor = xor i1 %class0, %class1
   ret i1 %xor
 }
 
 define i1 @test_fold_xor3_class_f32_0(float %a) {
 ; CHECK-LABEL: @test_fold_xor3_class_f32_0(
-; CHECK-NEXT:    [[CLASS0:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A:%.*]], i32 7)
-; CHECK-NEXT:    ret i1 [[CLASS0]]
+; CHECK-NEXT:    [[CLASS0:%.*]] = fcmp uno float [[A:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CLASS2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 4)
+; CHECK-NEXT:    [[XOR_1:%.*]] = xor i1 [[CLASS0]], [[CLASS2]]
+; CHECK-NEXT:    ret i1 [[XOR_1]]
 ;
   %class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
   %class1 = call i1 @llvm.is.fpclass.f32(float %a, i32 2)
   %class2 = call i1 @llvm.is.fpclass.f32(float %a, i32 4)
   %xor.0 = xor i1 %class0, %class1
   %xor.1 = xor i1 %xor.0, %class2
   ret i1 %xor.1
 }
 
 define i1 @test_fold_xor_all_tests_class_f32_0(float %a) {
 ; CHECK-LABEL: @test_fold_xor_all_tests_class_f32_0(
-; CHECK-NEXT:    ret i1 true
+; CHECK-NEXT:    [[CLASS0:%.*]] = fcmp uno float [[A:%.*]], 0.000000e+00
+; CHECK-NEXT:    [[CLASS2:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 4)
+; CHECK-NEXT:    [[CLASS3:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 8)
+; CHECK-NEXT:    [[CLASS4:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 16)
+; CHECK-NEXT:    [[CLASS5:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 32)
+; CHECK-NEXT:    [[CLASS6:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 64)
+; CHECK-NEXT:    [[CLASS7:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 128)
+; CHECK-NEXT:    [[CLASS8:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 256)
+; CHECK-NEXT:    [[CLASS9:%.*]] = call i1 @llvm.is.fpclass.f32(float [[A]], i32 512)
+; CHECK-NEXT:    [[XOR_1:%.*]] = xor i1 [[CLASS0]], [[CLASS2]]
+; CHECK-NEXT:    [[XOR_2:%.*]] = xor i1 [[XOR_1]], [[CLASS3]]
+; CHECK-NEXT:    [[XOR_3:%.*]] = xor i1 [[XOR_2]], [[CLASS4]]
+; CHECK-NEXT:    [[XOR_4:%.*]] = xor i1 [[XOR_3]], [[CLASS5]]
+; CHECK-NEXT:    [[XOR_5:%.*]] = xor i1 [[XOR_4]], [[CLASS6]]
+; CHECK-NEXT:    [[XOR_6:%.*]] = xor i1 [[XOR_5]], [[CLASS7]]
+; CHECK-NEXT:    [[XOR_7:%.*]] = xor i1 [[XOR_6]], [[CLASS8]]
+; CHECK-NEXT:    [[XOR_8:%.*]] = xor i1 [[XOR_7]], [[CLASS9]]
+; CHECK-NEXT:    ret i1 [[XOR_8]]
 ;
   %class0 = call i1 @llvm.is.fpclass.f32(float %a, i32 1)
   %class1 = call i1 @llvm.is.fpclass.f32(float %a, i32 2)
   %class2 = call i1 @llvm.is.fpclass.f32(float %a, i32 4)
   %class3 = call i1 @llvm.is.fpclass.f32(float %a, i32 8)
   %class4 = call i1 @llvm.is.fpclass.f32(float %a, i32 16)
   %class5 = call i1 @llvm.is.fpclass.f32(float %a, i32 32)
   %class6 = call i1 @llvm.is.fpclass.f32(float %a, i32 64)
;
   %fneg = fneg float %arg
   %class = call i1 @llvm.is.fpclass.f32(float %fneg, i32 512)
   ret i1 %class
 }
 
 ; -> qnan|snan
 define i1 @test_class_fneg_isnan(float %arg) {
 ; CHECK-LABEL: @test_class_fneg_isnan(
-; CHECK-NEXT:    [[FNEG:%.*]] = fneg float [[ARG:%.*]]
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[FNEG]], i32 3)
+; CHECK-NEXT:    [[CLASS:%.*]] = fcmp uno float [[ARG:%.*]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fneg = fneg float %arg
   %class = call i1 @llvm.is.fpclass.f32(float %fneg, i32 3)
   ret i1 %class
 }
 
 ; -> ~nan
 define i1 @test_class_fneg_nnan(float %arg) {
 ; CHECK-LABEL: @test_class_fneg_nnan(
-; CHECK-NEXT:    [[FNEG:%.*]] = fneg float [[ARG:%.*]]
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[FNEG]], i32 1020)
+; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord float [[ARG:%.*]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fneg = fneg float %arg
   %class = call i1 @llvm.is.fpclass.f32(float %fneg, i32 1020)
   ret i1 %class
 }
 
 ; -> normal
;
   %fabs = call float @llvm.fabs.f32(float %arg)
   %class = call i1 @llvm.is.fpclass.f32(float %fabs, i32 512)
   ret i1 %class
 }
 
 ; -> qnan|snan
 define i1 @test_class_fabs_isnan(float %arg) {
 ; CHECK-LABEL: @test_class_fabs_isnan(
-; CHECK-NEXT:    [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[FABS]], i32 3)
+; CHECK-NEXT:    [[CLASS:%.*]] = fcmp uno float [[ARG:%.*]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call float @llvm.fabs.f32(float %arg)
   %class = call i1 @llvm.is.fpclass.f32(float %fabs, i32 3)
   ret i1 %class
 }
 
 ; -> fcPositive
 define i1 @test_class_fabs_nnan(float %arg) {
 ; CHECK-LABEL: @test_class_fabs_nnan(
-; CHECK-NEXT:    [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[FABS]], i32 1020)
+; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord float [[ARG:%.*]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call float @llvm.fabs.f32(float %arg)
   %class = call i1 @llvm.is.fpclass.f32(float %fabs, i32 1020)
   ret i1 %class
 }
 
 ; -> posnormal
;
   %fabs = call float @llvm.fabs.f32(float %arg)
   %fneg.fabs = fneg float %fabs
   %class = call i1 @llvm.is.fpclass.f32(float %fneg.fabs, i32 512)
   ret i1 %class
 }
 
 define i1 @test_class_fneg_fabs_isnan(float %arg) {
 ; CHECK-LABEL: @test_class_fneg_fabs_isnan(
-; CHECK-NEXT:    [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
-; CHECK-NEXT:    [[FNEG_FABS:%.*]] = fneg float [[FABS]]
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[FNEG_FABS]], i32 3)
+; CHECK-NEXT:    [[CLASS:%.*]] = fcmp uno float [[ARG:%.*]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call float @llvm.fabs.f32(float %arg)
   %fneg.fabs = fneg float %fabs
   %class = call i1 @llvm.is.fpclass.f32(float %fneg.fabs, i32 3)
   ret i1 %class
 }
 
 define i1 @test_class_fneg_fabs_nnan(float %arg) {
 ; CHECK-LABEL: @test_class_fneg_fabs_nnan(
-; CHECK-NEXT:    [[FABS:%.*]] = call float @llvm.fabs.f32(float [[ARG:%.*]])
-; CHECK-NEXT:    [[FNEG_FABS:%.*]] = fneg float [[FABS]]
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[FNEG_FABS]], i32 1020)
+; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord float [[ARG:%.*]], 0.000000e+00
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call float @llvm.fabs.f32(float %arg)
   %fneg.fabs = fneg float %fabs
   %class = call i1 @llvm.is.fpclass.f32(float %fneg.fabs, i32 1020)
   ret i1 %class
 }