DAG: Lower is.fpclass fcInf to fcmp of fabs

[arsenm]

Summary

InstCombine should have taken care of this, but I think
this is more useful in the future when the expansion
tries to handle multiple cases at a time with fcmp.

x87 looks worse to me but the only thing I know about it is that
I aggressively do not care about it.

[arsenm]

Fix nan handling in inverted case

[arsenm]

ping

[nemanjai]

The PPC changes look fine to me. I believe that the new TOC loads will likely go away with https://reviews.llvm.org/D140381. Is that assumption correct @qiucf?

[qiucf]

In D143198#4171646, @nemanjai wrote:

The PPC changes look fine to me. I believe that the new TOC loads will likely go away with https://reviews.llvm.org/D140381. Is that assumption correct @qiucf?

Yes, for ISA 3.0+.

[arsenm]

Rebase

[nemanjai]

LGTM.

[arsenm]

310f83961269a574d753932dc5f0c8fd44027781

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (Flags.hasNoFPExcept() &&
     }
 
     if (Test == fcNan &&
         isCondCodeLegalOrCustom(IsInverted ? ISD::SETO : ISD::SETUO,
                                 OperandVT.getScalarType().getSimpleVT())) {
       return DAG.getSetCC(DL, ResultVT, Op, Op,
                           IsInverted ? ISD::SETO : ISD::SETUO);
     }
+
+    if (Test == fcInf &&
+        isCondCodeLegalOrCustom(IsInverted ? ISD::SETUNE : ISD::SETOEQ,
+                                OperandVT.getScalarType().getSimpleVT()) &&
+        isOperationLegalOrCustom(ISD::FABS, OperandVT.getScalarType())) {
+      // isinf(x) --> fabs(x) == inf
+      SDValue Abs = DAG.getNode(ISD::FABS, DL, OperandVT, Op);
+      SDValue Inf =
+          DAG.getConstantFP(APFloat::getInf(Semantics), DL, OperandVT);
+      return DAG.getSetCC(DL, ResultVT, Abs, Inf,
+                          IsInverted ? ISD::SETUNE : ISD::SETOEQ);
+    }
   }
 
   // In the general case use integer operations.
   unsigned BitSize = OperandVT.getScalarSizeInBits();
   EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), BitSize);
   if (OperandVT.isVector())
     IntVT = EVT::getVectorVT(*DAG.getContext(), IntVT,
                              OperandVT.getVectorElementCount());

llvm/test/CodeGen/PowerPC/is_fpclass.ll

 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516)  ; 0x204 = "inf"
   ret i1 %1
 }
 
 define i1 @isinf_ppc_fp128(ppc_fp128 %x) nounwind {
 ; CHECK-LABEL: isinf_ppc_fp128:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    mffprd 3, 1
-; CHECK-NEXT:    li 4, 2047
-; CHECK-NEXT:    clrldi 3, 3, 1
-; CHECK-NEXT:    rldic 4, 4, 52, 1
-; CHECK-NEXT:    cmpd 3, 4
-; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
+; CHECK-NEXT:    xsabsdp 0, 1
 ; CHECK-NEXT:    li 4, 1
+; CHECK-NEXT:    lfs 1, .LCPI9_0@toc@l(3)
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    fcmpu 0, 0, 1
 ; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 516)  ; 0x204 = "inf"
   ret i1 %1
 }
 
 define i1 @isinf_f128(fp128 %x) nounwind {
 ; CHECK-LABEL: isinf_f128: