DAG: Expand legalization of is.fpclass to fcmp for DAZ

[arsenm]

Summary

Try to use a compare with 0 if DAZ is assumed.
FPClassTest really needs to be marked as a bimask enum, but the API
for that is currently broken.

[arsenm]

ping

[arsenm]

ping

[arsenm]

ping

[sepavloff]

Could you please rebase the patch? Some changes for FPClassTest are already committed.

[arsenm]

Rebase with FPClassTest changes

[sepavloff]

llvm/include/llvm/ADT/FloatingPointMode.h

148 ↗

(On Diff #505311)

The function name is not verb-based. Maybe treatInputAsZero or something like that?

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8055

It looks like this function should return boolean value.

[arsenm]

Return bool

[arsenm]

ping

llvm/include/llvm/ADT/FloatingPointMode.h

148 ↗

(On Diff #505311)

Are is the verb? I think it reads fine

[sepavloff]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8104

What prevents to put the check here?

[arsenm]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8104

Expanded logic which I have no way of testing. If I can't write a test I'm not writing the handling for it

[sepavloff]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8104

To test isCondCodeLegal here we need a target in which SETOEQ is not legal. It is hard to imagine that a target supports FP numbers natively but comparison of them for equality is absent. Probably this TODO is not useful and could be removed. Alternatively, you could put the call to isCondCodeLegal and leave it untested just because there is no way to test it.

[arsenm]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8104

Checking isCondCodeLegal actually results in some x86 codegen diffs, so I'll do that separately

[arsenm]

Rebase

[arsenm]

ping

[sepavloff]

LGTM.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8107–8108

It looks like this comment is misplaced.

llvm/unittests/ADT/FloatingPointMode.cpp

222–228

This test is not related to the legalization, it could be committed separately.

[arsenm]

18b93562cfcf0fb728e6fc985855f3e74aac438d

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

8107–8108

Don't really see what you mean by this

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
   }
 
   if (SDValue SelCC = createSelectForFMINNUM_FMAXNUM(Node, DAG))
     return SelCC;
 
   return SDValue();
 }
 
+/// If this FPClassTest can be performed with a fcmp to 0, return the test mask
+/// for the floating-point mode.
+static bool isFCmpEqualZero(FPClassTest Test, const fltSemantics &Semantics,
+                            const MachineFunction &MF) {
+  if (Test == fcZero &&
+      MF.getDenormalMode(Semantics).Input == DenormalMode::IEEE)
+    return true;
+  if (Test == (fcZero | fcSubnormal) &&
+      MF.getDenormalMode(Semantics).inputsAreZero())
+    return true;
+  return false;
+}
+
 SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
                                          FPClassTest Test, SDNodeFlags Flags,
                                          const SDLoc &DL,
                                          SelectionDAG &DAG) const {
   EVT OperandVT = Op.getValueType();
   assert(OperandVT.isFloatingPoint());
 
   // Degenerated cases.
-  if (Test == 0)
+  if (Test == fcNone)
     return DAG.getBoolConstant(false, DL, ResultVT, OperandVT);
   if ((Test & fcAllFlags) == fcAllFlags)
     return DAG.getBoolConstant(true, DL, ResultVT, OperandVT);
 
   // PPC double double is a pair of doubles, of which the higher part determines
   // the value class.
   if (OperandVT == MVT::ppcf128) {
     Op = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::f64, Op,
SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
   EVT ScalarFloatVT = OperandVT.getScalarType();
   const Type *FloatTy = ScalarFloatVT.getTypeForEVT(*DAG.getContext());
   const llvm::fltSemantics &Semantics = FloatTy->getFltSemantics();
   bool IsF80 = (ScalarFloatVT == MVT::f80);
 
   // Some checks can be implemented using float comparisons, if floating point
   // exceptions are ignored.
   if (Flags.hasNoFPExcept() &&
+      // TODO: Should check isCondCodeLegal
       isOperationLegalOrCustom(ISD::SETCC, OperandVT.getScalarType())) {
-    if (Test == fcZero) {
-      DenormalMode Mode = DAG.getMachineFunction().getDenormalMode(Semantics);
-      if (Mode.Input == DenormalMode::IEEE) {
-        // If denormals could be implicitly treated as 0, this is not equivalent
-        // to a compare with 0 since it will also be true for denormals.
-        //
-        // TODO: With DAZ, check == fcZero | fcSubnormal
-        return DAG.getSetCC(DL, ResultVT, Op,
-                            DAG.getConstantFP(0.0, DL, OperandVT),
-                            IsInverted ? ISD::SETUNE : ISD::SETOEQ);
-      }
-    }
+    if (isFCmpEqualZero(Test, Semantics, DAG.getMachineFunction())) {
 
     if (Test == fcNan)
       return DAG.getSetCC(DL, ResultVT, Op, Op,
                           IsInverted ? ISD::SETO : ISD::SETUO);
   }
 
   // In the general case use integer operations.
   unsigned BitSize = OperandVT.getScalarSizeInBits();

llvm/test/CodeGen/X86/is_fpclass.ll

 entry:
   %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240)  ; 0xf0 = "subnormal|zero"
   ret i1 %0
 }
 
 define i1 @issubnormal_or_zero_f_daz(float %x) #0 {
 ; CHECK-32-LABEL: issubnormal_or_zero_f_daz:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    movl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-32-NEXT:    andl {{[0-9]+}}(%esp), %eax
-; CHECK-32-NEXT:    sete %cl
-; CHECK-32-NEXT:    decl %eax
-; CHECK-32-NEXT:    cmpl $8388607, %eax # imm = 0x7FFFFF
-; CHECK-32-NEXT:    setb %al
-; CHECK-32-NEXT:    orb %cl, %al
+; CHECK-32-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-32-NEXT:    fldz
+; CHECK-32-NEXT:    fucompp
+; CHECK-32-NEXT:    fnstsw %ax
+; CHECK-32-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-32-NEXT:    sahf
+; CHECK-32-NEXT:    setnp %cl
+; CHECK-32-NEXT:    sete %al
+; CHECK-32-NEXT:    andb %cl, %al
 ; CHECK-32-NEXT:    retl
 ;
 ; CHECK-64-LABEL: issubnormal_or_zero_f_daz:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    movd %xmm0, %eax
-; CHECK-64-NEXT:    andl $2147483647, %eax # imm = 0x7FFFFFFF
-; CHECK-64-NEXT:    sete %cl
-; CHECK-64-NEXT:    decl %eax
-; CHECK-64-NEXT:    cmpl $8388607, %eax # imm = 0x7FFFFF
-; CHECK-64-NEXT:    setb %al
-; CHECK-64-NEXT:    orb %cl, %al
+; CHECK-64-NEXT:    xorps %xmm1, %xmm1
+; CHECK-64-NEXT:    cmpeqss %xmm0, %xmm1
+; CHECK-64-NEXT:    movd %xmm1, %eax
+; CHECK-64-NEXT:    andl $1, %eax
+; CHECK-64-NEXT:    # kill: def $al killed $al killed $eax
 ; CHECK-64-NEXT:    retq
 entry:
   %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 240)  ; 0xf0 = "subnormal|zero"
   ret i1 %0
 }
 
 define i1 @issubnormal_or_zero_f_maybe_daz(float %x) #1 {
 ; CHECK-32-LABEL: issubnormal_or_zero_f_maybe_daz:

llvm/unittests/ADT/FloatingPointMode.cpp

EXPECT_EQ(
       DenormalMode::getIEEE().mergeCalleeMode(DenormalMode::getPreserveSign()));
   EXPECT_EQ(
       DenormalMode::getIEEE(),
       DenormalMode::getPreserveSign().mergeCalleeMode(DenormalMode::getIEEE()));
   EXPECT_EQ(
       DenormalMode::getIEEE(),
       DenormalMode::getPreserveSign().mergeCalleeMode(DenormalMode::getIEEE()));
 }
+
+TEST(FloatingPointModeTest, DenormalModePredicates) {
+  EXPECT_TRUE(DenormalMode::getPreserveSign().inputsAreZero());
+  EXPECT_TRUE(DenormalMode::getPositiveZero().inputsAreZero());
+  EXPECT_FALSE(DenormalMode::getIEEE().inputsAreZero());
+  EXPECT_FALSE(DenormalMode::getDynamic().inputsAreZero());
+}
 }