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[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment

Authored by kachkov98 on Oct 19 2022, 8:50 AM.



Cannonical frame address after RVV stack adjustment is sp + StackSize +
RVVStackSize * vlenb, and since vlenb is unknown at compile-time (but it
is a constant for particular HW implementation), emit
.cfi_def_cfa_expression so libunwind can read VLENB CSR register at
run-time and obtain correct frame address.

Fixes (but additional
run-time support for reading CSR may be required)

Diff Detail

Event Timeline

kachkov98 created this revision.Oct 19 2022, 8:50 AM
kachkov98 requested review of this revision.Oct 19 2022, 8:50 AM

Similar approach is used in AArch64 backend for SVE registers:
VLENB support in libunwind:

kito-cheng accepted this revision.Oct 24 2022, 1:53 AM

LGTM with a nit, verified with -march=rv64gcv/-mabi=lp64d


nit: one empty line between functions.

This revision is now accepted and ready to land.Oct 24 2022, 1:53 AM
kachkov98 updated this revision to Diff 470499.Oct 25 2022, 8:01 AM

Review changes

Thank you, I will merge this patch after is landed (to be sure there are no some fundamental issues with this approach from run-time side).

Few minor comments.


Register Reg rather than unsigned Reg


uint64_t rather than unsigned here, since RVVStackSize and getStackSizeWithRVVPadding are both uint64_t

kachkov98 updated this revision to Diff 472888.Nov 3 2022, 3:37 AM

Review changes + rebase

This revision was landed with ongoing or failed builds.Dec 6 2022, 1:46 AM
This revision was automatically updated to reflect the committed changes.