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Differential D136263

[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
ClosedPublic

Authored by kachkov98 on Oct 19 2022, 8:50 AM.

Details

Reviewers
kito-cheng
craig.topper
asb
Commits
rG132dc442ba3c: [RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
Summary

Cannonical frame address after RVV stack adjustment is sp + StackSize +
RVVStackSize * vlenb, and since vlenb is unknown at compile-time (but it
is a constant for particular HW implementation), emit
.cfi_def_cfa_expression so libunwind can read VLENB CSR register at
run-time and obtain correct frame address.

Fixes https://github.com/llvm/llvm-project/issues/58356 (but additional
run-time support for reading CSR may be required)

Diff Detail

Event Timeline

kachkov98 created this revision.Oct 19 2022, 8:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 19 2022, 8:50 AM
Herald added subscribers: sunshaoce, VincentWu, armkevincheng and 33 others. · View Herald Transcript
kachkov98 requested review of this revision.Oct 19 2022, 8:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 19 2022, 8:50 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
kachkov98 added reviewers: kito-cheng, craig.topper, asb.Oct 19 2022, 8:51 AM
kachkov98 added a subscriber: anton-afanasyev.
Herald added a subscriber: StephenFan. · View Herald TranscriptOct 19 2022, 8:51 AM
kachkov98 added a comment.Oct 19 2022, 9:03 AM

Similar approach is used in AArch64 backend for SVE registers: https://reviews.llvm.org/D84044
VLENB support in libunwind: https://reviews.llvm.org/D136264

Harbormaster completed remote builds in B193019: Diff 468935.Oct 19 2022, 9:27 AM
kito-cheng accepted this revision.Oct 24 2022, 1:53 AM

LGTM with a nit, verified with -march=rv64gcv/-mabi=lp64d

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
394

nit: one empty line between functions.

This revision is now accepted and ready to land.Oct 24 2022, 1:53 AM
kachkov98 updated this revision to Diff 470499.Oct 25 2022, 8:01 AM

Review changes

kachkov98 added a comment.Oct 25 2022, 8:04 AM

Thank you, I will merge this patch after https://reviews.llvm.org/D136264 is landed (to be sure there are no some fundamental issues with this approach from run-time side).

Harbormaster completed remote builds in B194187: Diff 470499.Oct 25 2022, 9:54 AM
kito-cheng added a comment.Nov 2 2022, 6:37 PM

Few minor comments.

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
348

Register Reg rather than unsigned Reg

350

uint64_t rather than unsigned here, since RVVStackSize and getStackSizeWithRVVPadding are both uint64_t

kachkov98 updated this revision to Diff 472888.Nov 3 2022, 3:37 AM

Review changes + rebase

Harbormaster completed remote builds in B195900: Diff 472888.Nov 3 2022, 4:31 AM
This revision was landed with ongoing or failed builds.Dec 6 2022, 1:46 AM
Closed by commit rG132dc442ba3c: [RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment (authored by kachkov98). · Explain Why
This revision was automatically updated to reflect the committed changes.
kachkov98 added a commit: rG132dc442ba3c: [RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment.
fakepaper56 mentioned this in D139509: [VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support.".Dec 6 2022, 11:10 PM
fakepaper56 mentioned this in rG0f8c761c4874: [VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support.".Dec 6 2022, 11:58 PM

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Diff 480389

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

//===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===// //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file contains the RISCV implementation of TargetFrameLowering class. // This file contains the RISCV implementation of TargetFrameLowering class.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "RISCVFrameLowering.h" #include "RISCVFrameLowering.h"
#include "RISCVMachineFunctionInfo.h" #include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h" #include "RISCVSubtarget.h"
#include "llvm/BinaryFormat/Dwarf.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/DiagnosticInfo.h"
#include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCDwarf.h"
#include "llvm/Support/LEB128.h"
#include <algorithm> #include <algorithm>
using namespace llvm; using namespace llvm;
// For now we use x18, a.k.a s2, as pointer to shadow call stack. // For now we use x18, a.k.a s2, as pointer to shadow call stack.
// User should explicitly set -ffixed-x18 and not use x18 in their asm. // User should explicitly set -ffixed-x18 and not use x18 in their asm.
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
▲ Show 20 Lines • Show All 306 Lines • ▼ Show 20 Linesvoid RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
const RISCVRegisterInfo &RI = *STI.getRegisterInfo(); const RISCVRegisterInfo &RI = *STI.getRegisterInfo();
// We must keep the stack pointer aligned through any intermediate // We must keep the stack pointer aligned through any intermediate
// updates. // updates.
RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset, RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset,
Flag, getStackAlign()); Flag, getStackAlign());
} }
static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI,
Register Reg,
kito-chengUnsubmitted
Not Done
ReplyInline Actions

Register Reg rather than unsigned Reg

kito-cheng: `Register Reg` rather than `unsigned Reg`
uint64_t FixedOffset,
uint64_t ScalableOffset) {
kito-chengUnsubmitted
Not Done
ReplyInline Actions

uint64_t rather than unsigned here, since RVVStackSize and getStackSizeWithRVVPadding are both uint64_t

kito-cheng: `uint64_t` rather than `unsigned` here, since `RVVStackSize` and `getStackSizeWithRVVPadding`…
assert(ScalableOffset != 0 && "Did not need to adjust CFA for RVV");
SmallString<64> Expr;
std::string CommentBuffer;
llvm::raw_string_ostream Comment(CommentBuffer);
// Build up the expression (Reg + FixedOffset + ScalableOffset * VLENB).
unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true);
Expr.push_back((uint8_t)(dwarf::DW_OP_breg0 + DwarfReg));
Expr.push_back(0);
if (Reg == RISCV::X2)
Comment << "sp";
else
Comment << printReg(Reg, &TRI);
uint8_t buffer[16];
if (FixedOffset) {
Expr.push_back(dwarf::DW_OP_consts);
Expr.append(buffer, buffer + encodeSLEB128(FixedOffset, buffer));
Expr.push_back((uint8_t)dwarf::DW_OP_plus);
Comment << " + " << FixedOffset;
}
Expr.push_back((uint8_t)dwarf::DW_OP_consts);
Expr.append(buffer, buffer + encodeSLEB128(ScalableOffset, buffer));
unsigned DwarfVlenb = TRI.getDwarfRegNum(RISCV::VLENB, true);
Expr.push_back((uint8_t)dwarf::DW_OP_bregx);
Expr.append(buffer, buffer + encodeULEB128(DwarfVlenb, buffer));
Expr.push_back(0);
Expr.push_back((uint8_t)dwarf::DW_OP_mul);
Expr.push_back((uint8_t)dwarf::DW_OP_plus);
Comment << " + " << ScalableOffset << " * vlenb";
SmallString<64> DefCfaExpr;
DefCfaExpr.push_back(dwarf::DW_CFA_def_cfa_expression);
DefCfaExpr.append(buffer, buffer + encodeULEB128(Expr.size(), buffer));
DefCfaExpr.append(Expr.str());
return MCCFIInstruction::createEscape(nullptr, DefCfaExpr.str(),
Comment.str());
}
void RISCVFrameLowering::emitPrologue(MachineFunction &MF, void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
kito-chengUnsubmitted
Not Done
ReplyInline Actions

nit: one empty line between functions.

kito-cheng: nit: one empty line between functions.
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>(); auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
const RISCVRegisterInfo *RI = STI.getRegisterInfo(); const RISCVRegisterInfo *RI = STI.getRegisterInfo();
const RISCVInstrInfo *TII = STI.getInstrInfo(); const RISCVInstrInfo *TII = STI.getInstrInfo();
MachineBasicBlock::iterator MBBI = MBB.begin(); MachineBasicBlock::iterator MBBI = MBB.begin();
Register FPReg = getFPReg(STI); Register FPReg = getFPReg(STI);
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines if (!hasFP(MF)) {
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(
nullptr, getStackSizeWithRVVPadding(MF))); nullptr, getStackSizeWithRVVPadding(MF)));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameSetup); .setMIFlag(MachineInstr::FrameSetup);
} }
} }
if (RVVStackSize) if (RVVStackSize) {
adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize, adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize,
MachineInstr::FrameSetup); MachineInstr::FrameSetup);
if (!hasFP(MF)) {
// Emit .cfi_def_cfa_expression "sp + StackSize + RVVStackSize * vlenb".
unsigned CFIIndex = MF.addFrameInst(createDefCFAExpression(
*RI, SPReg, getStackSizeWithRVVPadding(MF), RVVStackSize / 8));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex)
.setMIFlag(MachineInstr::FrameSetup);
}
}
if (hasFP(MF)) { if (hasFP(MF)) {
// Realign Stack // Realign Stack
const RISCVRegisterInfo *RI = STI.getRegisterInfo(); const RISCVRegisterInfo *RI = STI.getRegisterInfo();
if (RI->hasStackRealignment(MF)) { if (RI->hasStackRealignment(MF)) {
Align MaxAlignment = MFI.getMaxAlign(); Align MaxAlignment = MFI.getMaxAlign();
const RISCVInstrInfo *TII = STI.getInstrInfo(); const RISCVInstrInfo *TII = STI.getInstrInfo();
▲ Show 20 Lines • Show All 792 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

Show All 14 Lines
; CHECK-LABEL: _Z3foov: ; CHECK-LABEL: _Z3foov:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 10 ; CHECK-NEXT: li a1, 10
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x0a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 10 * vlenb
; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_49) ; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_49)
; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_49) ; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_49)
; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_48) ; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_48)
; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_48) ; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_48)
; CHECK-NEXT: vle8.v v10, (a0) ; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,145 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixunsdfti@plt ; CHECK-V-NEXT: call __fixunsdfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s1, a0
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s0, a1
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixunssfti@plt ; CHECK-V-NEXT: call __fixunssfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
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; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s1, a0
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s0, a1
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; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
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; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixunsdfti@plt ; CHECK-V-NEXT: call __fixunsdfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
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; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s1, a0
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s0, a1
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; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
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; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixunssfti@plt ; CHECK-V-NEXT: call __fixunssfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
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; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 48 ; CHECK-V-NEXT: addi a0, sp, 48
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s1, a0
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s0, a1
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llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

Show All 17 Lines
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24 ; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 24 * vlenb
; CHECK-NEXT: li a0, 55 ; CHECK-NEXT: li a0, 55
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vloxseg2ei32.v v8, (a0), v8 ; CHECK-NEXT: vloxseg2ei32.v v8, (a0), v8
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
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; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 32 ; SUBREGLIVENESS-NEXT: .cfi_def_cfa_offset 32
; SUBREGLIVENESS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; SUBREGLIVENESS-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; SUBREGLIVENESS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; SUBREGLIVENESS-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; SUBREGLIVENESS-NEXT: .cfi_offset ra, -8 ; SUBREGLIVENESS-NEXT: .cfi_offset ra, -8
; SUBREGLIVENESS-NEXT: .cfi_offset s0, -16 ; SUBREGLIVENESS-NEXT: .cfi_offset s0, -16
; SUBREGLIVENESS-NEXT: csrr a0, vlenb ; SUBREGLIVENESS-NEXT: csrr a0, vlenb
; SUBREGLIVENESS-NEXT: slli a0, a0, 4 ; SUBREGLIVENESS-NEXT: slli a0, a0, 4
; SUBREGLIVENESS-NEXT: sub sp, sp, a0 ; SUBREGLIVENESS-NEXT: sub sp, sp, a0
; SUBREGLIVENESS-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb
; SUBREGLIVENESS-NEXT: li a0, 55 ; SUBREGLIVENESS-NEXT: li a0, 55
; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v8, (a0), v8 ; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v8, (a0), v8
; SUBREGLIVENESS-NEXT: csrr a0, vlenb ; SUBREGLIVENESS-NEXT: csrr a0, vlenb
; SUBREGLIVENESS-NEXT: slli a0, a0, 3 ; SUBREGLIVENESS-NEXT: slli a0, a0, 3
; SUBREGLIVENESS-NEXT: add a0, sp, a0 ; SUBREGLIVENESS-NEXT: add a0, sp, a0
; SUBREGLIVENESS-NEXT: addi a0, a0, 16 ; SUBREGLIVENESS-NEXT: addi a0, a0, 16
; SUBREGLIVENESS-NEXT: csrr a1, vlenb ; SUBREGLIVENESS-NEXT: csrr a1, vlenb
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

Show All 30 Lines
define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) { define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) {
; RV64IV-LABEL: access_fixed_and_vector_objects: ; RV64IV-LABEL: access_fixed_and_vector_objects:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -528 ; RV64IV-NEXT: addi sp, sp, -528
; RV64IV-NEXT: .cfi_def_cfa_offset 528 ; RV64IV-NEXT: .cfi_def_cfa_offset 528
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x90, 0x04, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 528 + 2 * vlenb
; RV64IV-NEXT: addi a0, sp, 8 ; RV64IV-NEXT: addi a0, sp, 8
; RV64IV-NEXT: vl1re64.v v8, (a0) ; RV64IV-NEXT: vl1re64.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 528 ; RV64IV-NEXT: addi a0, sp, 528
; RV64IV-NEXT: ld a1, 520(sp) ; RV64IV-NEXT: ld a1, 520(sp)
; RV64IV-NEXT: vl1re64.v v9, (a0) ; RV64IV-NEXT: vl1re64.v v9, (a0)
; RV64IV-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; RV64IV-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; RV64IV-NEXT: vadd.vv v8, v8, v9 ; RV64IV-NEXT: vadd.vv v8, v8, v9
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll

Show First 20 Lines • Show All 1,350 Lines • ▼ Show 20 Lines
define <vscale x 8 x i64> @bitreverse_nxv8i64(<vscale x 8 x i64> %va) { define <vscale x 8 x i64> @bitreverse_nxv8i64(<vscale x 8 x i64> %va) {
; RV32-LABEL: bitreverse_nxv8i64: ; RV32-LABEL: bitreverse_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: sub sp, sp, a0 ; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 61681 ; RV32-NEXT: lui a0, 61681
; RV32-NEXT: addi a0, a0, -241 ; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: sw a0, 12(sp) ; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: lui a0, 209715 ; RV32-NEXT: lui a0, 209715
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llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll

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define <vscale x 8 x i64> @bswap_nxv8i64(<vscale x 8 x i64> %va) { define <vscale x 8 x i64> @bswap_nxv8i64(<vscale x 8 x i64> %va) {
; RV32-LABEL: bswap_nxv8i64: ; RV32-LABEL: bswap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: sub sp, sp, a0 ; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a0 ; RV32-NEXT: vsrl.vx v16, v8, a0
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: vsrl.vx v24, v8, a1 ; RV32-NEXT: vsrl.vx v24, v8, a1
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llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll

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; RV32-LABEL: vp_bswap_nxv7i64: ; RV32-LABEL: vp_bswap_nxv7i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
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; ;
; RV64-LABEL: vp_bswap_nxv7i64: ; RV64-LABEL: vp_bswap_nxv7i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t ; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t ; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: li a0, 255 ; RV64-NEXT: li a0, 255
; RV64-NEXT: slli a0, a0, 24 ; RV64-NEXT: slli a0, a0, 24
; RV64-NEXT: vand.vx v24, v8, a0, v0.t ; RV64-NEXT: vand.vx v24, v8, a0, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t ; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
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define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) { define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_nxv7i64_unmasked: ; RV32-LABEL: vp_bswap_nxv7i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
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; RV32-LABEL: vp_bswap_nxv8i64: ; RV32-LABEL: vp_bswap_nxv8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
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; ;
; RV64-LABEL: vp_bswap_nxv8i64: ; RV64-LABEL: vp_bswap_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t ; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t ; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: li a0, 255 ; RV64-NEXT: li a0, 255
; RV64-NEXT: slli a0, a0, 24 ; RV64-NEXT: slli a0, a0, 24
; RV64-NEXT: vand.vx v24, v8, a0, v0.t ; RV64-NEXT: vand.vx v24, v8, a0, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t ; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
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define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) { define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_nxv8i64_unmasked: ; RV32-LABEL: vp_bswap_nxv8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
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define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) { define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv64i16: ; CHECK-LABEL: vp_bswap_nxv64i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1 ; CHECK-NEXT: srli a2, a1, 1
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llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

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define fastcc <vscale x 128 x i32> @ret_split_nxv128i32(<vscale x 128 x i32>* %x) { define fastcc <vscale x 128 x i32> @ret_split_nxv128i32(<vscale x 128 x i32>* %x) {
; CHECK-LABEL: ret_split_nxv128i32: ; CHECK-LABEL: ret_split_nxv128i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 5 ; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 3 ; CHECK-NEXT: slli a3, a2, 3
; CHECK-NEXT: add a4, a1, a3 ; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl8re32.v v8, (a4) ; CHECK-NEXT: vl8re32.v v8, (a4)
; CHECK-NEXT: csrr a4, vlenb ; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: li a5, 24 ; CHECK-NEXT: li a5, 24
; CHECK-NEXT: mul a4, a4, a5 ; CHECK-NEXT: mul a4, a4, a5
; CHECK-NEXT: add a4, sp, a4 ; CHECK-NEXT: add a4, sp, a4
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define fastcc <vscale x 32 x i32> @ret_nxv32i32_param_nxv32i32_nxv32i32_nxv32i32_i32(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y, <vscale x 32 x i32> %z, i32 %w) { define fastcc <vscale x 32 x i32> @ret_nxv32i32_param_nxv32i32_nxv32i32_nxv32i32_i32(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y, <vscale x 32 x i32> %z, i32 %w) {
; CHECK-LABEL: ret_nxv32i32_param_nxv32i32_nxv32i32_nxv32i32_i32: ; CHECK-LABEL: ret_nxv32i32_param_nxv32i32_nxv32i32_nxv32i32_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vmv8r.v v24, v8 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
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llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll

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define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ceil_vv_nxv16f64: ; CHECK-LABEL: vp_ceil_vv_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3 ; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v2, v0, a2 ; CHECK-NEXT: vslidedown.vx v2, v0, a2
; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: sltu a3, a0, a2
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a3, a3, -1
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llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
define <32 x float> @vfptrunc_v32f32_v32f64(<32 x double> %a, <32 x i1> %m, i32 zeroext %vl) { define <32 x float> @vfptrunc_v32f32_v32f64(<32 x double> %a, <32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfptrunc_v32f32_v32f64: ; CHECK-LABEL: vfptrunc_v32f32_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: sltu a2, a0, a1
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: addi a2, a2, -1
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llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll

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define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zeroext %vl) { define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v128i7_v128i16: ; CHECK-LABEL: vtrunc_v128i7_v128i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 8 ; CHECK-NEXT: vslidedown.vi v0, v0, 8
; CHECK-NEXT: addi a1, a0, -64 ; CHECK-NEXT: addi a1, a0, -64
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: sltu a2, a0, a1
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: addi a2, a2, -1
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; CHECK-LABEL: vtrunc_v128i32_v128i64: ; CHECK-LABEL: vtrunc_v128i32_v128i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 56 ; CHECK-NEXT: li a3, 56
; CHECK-NEXT: mul a2, a2, a3 ; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3 ; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
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define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext %vl) { define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v32i32_v32i64: ; CHECK-LABEL: vtrunc_v32i32_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: sltu a2, a0, a1
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: addi a2, a2, -1
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll

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define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v15i64: ; RV32-LABEL: vp_bswap_v15i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
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; ;
; RV64-LABEL: vp_bswap_v15i64: ; RV64-LABEL: vp_bswap_v15i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t ; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t ; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: li a0, 255 ; RV64-NEXT: li a0, 255
; RV64-NEXT: slli a0, a0, 24 ; RV64-NEXT: slli a0, a0, 24
; RV64-NEXT: vand.vx v24, v8, a0, v0.t ; RV64-NEXT: vand.vx v24, v8, a0, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t ; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
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define <15 x i64> @vp_bswap_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { define <15 x i64> @vp_bswap_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v15i64_unmasked: ; RV32-LABEL: vp_bswap_v15i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
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define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v16i64: ; RV32-LABEL: vp_bswap_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
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; ;
; RV64-LABEL: vp_bswap_v16i64: ; RV64-LABEL: vp_bswap_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a1, v0.t ; RV64-NEXT: vand.vx v16, v8, a1, v0.t
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t ; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
; RV64-NEXT: li a0, 255 ; RV64-NEXT: li a0, 255
; RV64-NEXT: slli a0, a0, 24 ; RV64-NEXT: slli a0, a0, 24
; RV64-NEXT: vand.vx v24, v8, a0, v0.t ; RV64-NEXT: vand.vx v24, v8, a0, v0.t
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t ; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
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define <16 x i64> @vp_bswap_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { define <16 x i64> @vp_bswap_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v16i64_unmasked: ; RV32-LABEL: vp_bswap_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
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define <128 x i16> @vp_bswap_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext %evl) { define <128 x i16> @vp_bswap_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_v128i16: ; CHECK-LABEL: vp_bswap_v128i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vslidedown.vi v24, v0, 8 ; CHECK-NEXT: vslidedown.vi v24, v0, 8
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll

Show First 20 Lines • Show All 660 Lines • ▼ Show 20 Lines
define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ceil_v32f64: ; CHECK-LABEL: vp_ceil_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
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; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB27_2: ; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: lui a2, %hi(.LCPI27_0) ; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2) ; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vfabs.v v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v2, v1 ; CHECK-NEXT: vmv1r.v v2, v1
; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t ; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll

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define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_floor_v32f64: ; CHECK-LABEL: vp_floor_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
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; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB27_2: ; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: lui a2, %hi(.LCPI27_0) ; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2) ; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vfabs.v v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v2, v1 ; CHECK-NEXT: vmv1r.v v2, v1
; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t ; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll

Show First 20 Lines • Show All 257 Lines • ▼ Show 20 Lines
define <64 x float> @interleave_v32f32(<32 x float> %x, <32 x float> %y) { define <64 x float> @interleave_v32f32(<32 x float> %x, <32 x float> %y) {
; RV32-V128-LABEL: interleave_v32f32: ; RV32-V128-LABEL: interleave_v32f32:
; RV32-V128: # %bb.0: ; RV32-V128: # %bb.0:
; RV32-V128-NEXT: addi sp, sp, -16 ; RV32-V128-NEXT: addi sp, sp, -16
; RV32-V128-NEXT: .cfi_def_cfa_offset 16 ; RV32-V128-NEXT: .cfi_def_cfa_offset 16
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: slli a0, a0, 4 ; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: sub sp, sp, a0 ; RV32-V128-NEXT: sub sp, sp, a0
; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV32-V128-NEXT: lui a0, %hi(.LCPI10_0) ; RV32-V128-NEXT: lui a0, %hi(.LCPI10_0)
; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_0) ; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)
; RV32-V128-NEXT: li a1, 32 ; RV32-V128-NEXT: li a1, 32
; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-V128-NEXT: vle32.v v0, (a0) ; RV32-V128-NEXT: vle32.v v0, (a0)
; RV32-V128-NEXT: vmv8r.v v24, v8 ; RV32-V128-NEXT: vmv8r.v v24, v8
; RV32-V128-NEXT: addi a0, sp, 16 ; RV32-V128-NEXT: addi a0, sp, 16
; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
Show All 34 Lines
; ;
; RV64-V128-LABEL: interleave_v32f32: ; RV64-V128-LABEL: interleave_v32f32:
; RV64-V128: # %bb.0: ; RV64-V128: # %bb.0:
; RV64-V128-NEXT: addi sp, sp, -16 ; RV64-V128-NEXT: addi sp, sp, -16
; RV64-V128-NEXT: .cfi_def_cfa_offset 16 ; RV64-V128-NEXT: .cfi_def_cfa_offset 16
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: slli a0, a0, 4 ; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: sub sp, sp, a0 ; RV64-V128-NEXT: sub sp, sp, a0
; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-V128-NEXT: lui a0, %hi(.LCPI10_0) ; RV64-V128-NEXT: lui a0, %hi(.LCPI10_0)
; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_0) ; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)
; RV64-V128-NEXT: li a1, 32 ; RV64-V128-NEXT: li a1, 32
; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV64-V128-NEXT: vle32.v v0, (a0) ; RV64-V128-NEXT: vle32.v v0, (a0)
; RV64-V128-NEXT: vmv8r.v v24, v8 ; RV64-V128-NEXT: vmv8r.v v24, v8
; RV64-V128-NEXT: addi a0, sp, 16 ; RV64-V128-NEXT: addi a0, sp, 16
; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Lines
define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) { define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; RV32-V128-LABEL: interleave_v32i32: ; RV32-V128-LABEL: interleave_v32i32:
; RV32-V128: # %bb.0: ; RV32-V128: # %bb.0:
; RV32-V128-NEXT: addi sp, sp, -16 ; RV32-V128-NEXT: addi sp, sp, -16
; RV32-V128-NEXT: .cfi_def_cfa_offset 16 ; RV32-V128-NEXT: .cfi_def_cfa_offset 16
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: slli a0, a0, 4 ; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: sub sp, sp, a0 ; RV32-V128-NEXT: sub sp, sp, a0
; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV32-V128-NEXT: lui a0, %hi(.LCPI15_0) ; RV32-V128-NEXT: lui a0, %hi(.LCPI15_0)
; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI15_0) ; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI15_0)
; RV32-V128-NEXT: li a1, 32 ; RV32-V128-NEXT: li a1, 32
; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-V128-NEXT: vle32.v v0, (a0) ; RV32-V128-NEXT: vle32.v v0, (a0)
; RV32-V128-NEXT: vmv8r.v v24, v8 ; RV32-V128-NEXT: vmv8r.v v24, v8
; RV32-V128-NEXT: addi a0, sp, 16 ; RV32-V128-NEXT: addi a0, sp, 16
; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
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; ;
; RV64-V128-LABEL: interleave_v32i32: ; RV64-V128-LABEL: interleave_v32i32:
; RV64-V128: # %bb.0: ; RV64-V128: # %bb.0:
; RV64-V128-NEXT: addi sp, sp, -16 ; RV64-V128-NEXT: addi sp, sp, -16
; RV64-V128-NEXT: .cfi_def_cfa_offset 16 ; RV64-V128-NEXT: .cfi_def_cfa_offset 16
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: slli a0, a0, 4 ; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: sub sp, sp, a0 ; RV64-V128-NEXT: sub sp, sp, a0
; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-V128-NEXT: lui a0, %hi(.LCPI15_0) ; RV64-V128-NEXT: lui a0, %hi(.LCPI15_0)
; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI15_0) ; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI15_0)
; RV64-V128-NEXT: li a1, 32 ; RV64-V128-NEXT: li a1, 32
; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV64-V128-NEXT: vle32.v v0, (a0) ; RV64-V128-NEXT: vle32.v v0, (a0)
; RV64-V128-NEXT: vmv8r.v v24, v8 ; RV64-V128-NEXT: vmv8r.v v24, v8
; RV64-V128-NEXT: addi a0, sp, 16 ; RV64-V128-NEXT: addi a0, sp, 16
; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

Show First 20 Lines • Show All 1,586 Lines • ▼ Show 20 Lines
define i64 @vwreduce_add_v64i64(<64 x i32>* %x) { define i64 @vwreduce_add_v64i64(<64 x i32>* %x) {
; RV32-LABEL: vwreduce_add_v64i64: ; RV32-LABEL: vwreduce_add_v64i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV32-NEXT: addi a1, a0, 128 ; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vle32.v v16, (a1) ; RV32-NEXT: vle32.v v16, (a1)
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
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; ;
; RV64-LABEL: vwreduce_add_v64i64: ; RV64-LABEL: vwreduce_add_v64i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: slli a1, a1, 5
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV64-NEXT: addi a1, a0, 128 ; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: li a2, 32 ; RV64-NEXT: li a2, 32
; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-NEXT: vle32.v v16, (a1) ; RV64-NEXT: vle32.v v16, (a1)
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
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define i64 @vwreduce_uadd_v64i64(<64 x i32>* %x) { define i64 @vwreduce_uadd_v64i64(<64 x i32>* %x) {
; RV32-LABEL: vwreduce_uadd_v64i64: ; RV32-LABEL: vwreduce_uadd_v64i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV32-NEXT: addi a1, a0, 128 ; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vle32.v v16, (a1) ; RV32-NEXT: vle32.v v16, (a1)
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
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; ;
; RV64-LABEL: vwreduce_uadd_v64i64: ; RV64-LABEL: vwreduce_uadd_v64i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: slli a1, a1, 5
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; RV64-NEXT: addi a1, a0, 128 ; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: li a2, 32 ; RV64-NEXT: li a2, 32
; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-NEXT: vle32.v v16, (a1) ; RV64-NEXT: vle32.v v16, (a1)
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
▲ Show 20 Lines • Show All 5,759 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll

Show First 20 Lines • Show All 617 Lines • ▼ Show 20 Lines
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB26_2: ; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: lui a2, %hi(.LCPI26_0) ; CHECK-NEXT: lui a2, %hi(.LCPI26_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI26_0)(a2) ; CHECK-NEXT: fld ft0, %lo(.LCPI26_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v2 ; CHECK-NEXT: vmv1r.v v0, v2
; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vfabs.v v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t ; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
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; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB27_2: ; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: lui a2, %hi(.LCPI27_0) ; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2) ; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vfabs.v v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v2, v1 ; CHECK-NEXT: vmv1r.v v2, v1
; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t ; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t
Show All 35 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll

Show First 20 Lines • Show All 660 Lines • ▼ Show 20 Lines
define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_round_v32f64: ; CHECK-LABEL: vp_round_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
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; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB27_2: ; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: lui a2, %hi(.LCPI27_0) ; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2) ; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vfabs.v v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v2, v1 ; CHECK-NEXT: vmv1r.v v2, v1
; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t ; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t
Show All 39 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll

Show First 20 Lines • Show All 660 Lines • ▼ Show 20 Lines
define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_roundeven_v32f64: ; CHECK-LABEL: vp_roundeven_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
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; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB27_2: ; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: lui a2, %hi(.LCPI27_0) ; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2) ; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vfabs.v v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v2, v1 ; CHECK-NEXT: vmv1r.v v2, v1
; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t ; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t
Show All 39 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll

Show First 20 Lines • Show All 660 Lines • ▼ Show 20 Lines
define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_roundtozero_v32f64: ; CHECK-LABEL: vp_roundtozero_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
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; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB27_2: ; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: lui a2, %hi(.LCPI27_0) ; CHECK-NEXT: lui a2, %hi(.LCPI27_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2) ; CHECK-NEXT: fld ft0, %lo(.LCPI27_0)(a2)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vfabs.v v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v2, v1 ; CHECK-NEXT: vmv1r.v v2, v1
; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t ; CHECK-NEXT: vmflt.vf v2, v24, ft0, v0.t
Show All 39 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll

Show First 20 Lines • Show All 542 Lines • ▼ Show 20 Lines
define <128 x i1> @fcmp_oeq_vv_v128f16(<128 x half> %va, <128 x half> %vb, <128 x i1> %m, i32 zeroext %evl) { define <128 x i1> @fcmp_oeq_vv_v128f16(<128 x half> %va, <128 x half> %vb, <128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_oeq_vv_v128f16: ; CHECK-LABEL: fcmp_oeq_vv_v128f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
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define <32 x i1> @fcmp_oeq_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) { define <32 x i1> @fcmp_oeq_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_oeq_vv_v32f64: ; CHECK-LABEL: fcmp_oeq_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v2, v0 ; CHECK-NEXT: vmv1r.v v2, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
Show All 38 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll

Show First 20 Lines • Show All 627 Lines • ▼ Show 20 Lines
define <256 x i1> @icmp_eq_vv_v256i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 zeroext %evl) { define <256 x i1> @icmp_eq_vv_v256i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_eq_vv_v256i8: ; CHECK-LABEL: icmp_eq_vv_v256i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v2, v0 ; CHECK-NEXT: vmv1r.v v2, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: li a1, 128 ; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
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define <64 x i1> @icmp_eq_vv_v64i32(<64 x i32> %va, <64 x i32> %vb, <64 x i1> %m, i32 zeroext %evl) { define <64 x i1> @icmp_eq_vv_v64i32(<64 x i32> %va, <64 x i32> %vb, <64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_eq_vv_v64i32: ; CHECK-LABEL: icmp_eq_vv_v64i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
▲ Show 20 Lines • Show All 943 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll

Show First 20 Lines • Show All 320 Lines • ▼ Show 20 Lines
define <32 x double> @vfsgnj_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfsgnj_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfsgnj_vv_v32f64: ; CHECK-LABEL: vfsgnj_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll

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define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfma_vv_v32f64: ; CHECK-LABEL: vfma_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
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; CHECK-LABEL: vfma_vv_v32f64_unmasked: ; CHECK-LABEL: vfma_vv_v32f64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: addi a1, a2, 128 ; CHECK-NEXT: addi a1, a2, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a1) ; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll

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define <32 x double> @vfmax_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfmax_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfmax_vv_v32f64: ; CHECK-LABEL: vfmax_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll

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define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfmin_vv_v32f64: ; CHECK-LABEL: vfmin_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll

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define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfma_vv_v32f64: ; CHECK-LABEL: vfma_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
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; CHECK-LABEL: vfma_vv_v32f64_unmasked: ; CHECK-LABEL: vfma_vv_v32f64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: addi a1, a2, 128 ; CHECK-NEXT: addi a1, a2, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a1) ; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll

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define <64 x float> @vfwadd_v64f16(<64 x half> *%x, <64 x half> *%y) { define <64 x float> @vfwadd_v64f16(<64 x half> *%x, <64 x half> *%y) {
; CHECK-LABEL: vfwadd_v64f16: ; CHECK-LABEL: vfwadd_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1) ; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
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define <32 x double> @vfwadd_v32f32(<32 x float> *%x, <32 x float> *%y) { define <32 x double> @vfwadd_v32f32(<32 x float> *%x, <32 x float> *%y) {
; CHECK-LABEL: vfwadd_v32f32: ; CHECK-LABEL: vfwadd_v32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1) ; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v16, 16 ; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll

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define <64 x float> @vfwmul_v64f16(<64 x half> *%x, <64 x half> *%y) { define <64 x float> @vfwmul_v64f16(<64 x half> *%x, <64 x half> *%y) {
; CHECK-LABEL: vfwmul_v64f16: ; CHECK-LABEL: vfwmul_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1) ; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
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define <32 x double> @vfwmul_v32f32(<32 x float> *%x, <32 x float> *%y) { define <32 x double> @vfwmul_v32f32(<32 x float> *%x, <32 x float> *%y) {
; CHECK-LABEL: vfwmul_v32f32: ; CHECK-LABEL: vfwmul_v32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1) ; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v16, 16 ; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll

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define <64 x float> @vfwsub_v64f16(<64 x half> *%x, <64 x half> *%y) { define <64 x float> @vfwsub_v64f16(<64 x half> *%x, <64 x half> *%y) {
; CHECK-LABEL: vfwsub_v64f16: ; CHECK-LABEL: vfwsub_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1) ; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
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define <32 x double> @vfwsub_v32f32(<32 x float> *%x, <32 x float> *%y) { define <32 x double> @vfwsub_v32f32(<32 x float> *%x, <32 x float> *%y) {
; CHECK-LABEL: vfwsub_v32f32: ; CHECK-LABEL: vfwsub_v32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1) ; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v16, 16 ; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

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; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 1 ; RV64-NEXT: slli a2, a2, 1
; RV64-NEXT: sub sp, sp, a2 ; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; RV64-NEXT: addi a2, sp, 16 ; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf2 v0, v16 ; RV64-NEXT: vsext.vf2 v0, v16
; RV64-NEXT: vsext.vf2 v24, v8 ; RV64-NEXT: vsext.vf2 v24, v8
; RV64-NEXT: vsll.vi v16, v0, 3 ; RV64-NEXT: vsll.vi v16, v0, 3
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; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 1 ; RV64-NEXT: slli a2, a2, 1
; RV64-NEXT: sub sp, sp, a2 ; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; RV64-NEXT: addi a2, sp, 16 ; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf2 v0, v16 ; RV64-NEXT: vzext.vf2 v0, v16
; RV64-NEXT: vzext.vf2 v24, v8 ; RV64-NEXT: vzext.vf2 v24, v8
; RV64-NEXT: vsll.vi v16, v0, 3 ; RV64-NEXT: vsll.vi v16, v0, 3
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll

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define <32 x double> @vpmerge_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpmerge_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vv_v32f64: ; CHECK-LABEL: vpmerge_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

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; ;
; RV64-LABEL: vpscatter_v32f64: ; RV64-LABEL: vpscatter_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: addi a1, a0, 128 ; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vle64.v v24, (a1) ; RV64-NEXT: vle64.v v24, (a1)
; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vle64.v v24, (a0) ; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: li a1, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: mv a0, a2 ; RV64-NEXT: mv a0, a2
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; RV64-LABEL: vpscatter_baseidx_v32i32_v32f64: ; RV64-LABEL: vpscatter_baseidx_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: li a4, 10 ; RV64-NEXT: li a4, 10
; RV64-NEXT: mul a3, a3, a4 ; RV64-NEXT: mul a3, a3, a4
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x0a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 10 * vlenb
; RV64-NEXT: li a3, 32 ; RV64-NEXT: li a3, 32
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vle32.v v24, (a1) ; RV64-NEXT: vle32.v v24, (a1)
; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
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; RV64-LABEL: vpscatter_baseidx_sext_v32i32_v32f64: ; RV64-LABEL: vpscatter_baseidx_sext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: li a4, 10 ; RV64-NEXT: li a4, 10
; RV64-NEXT: mul a3, a3, a4 ; RV64-NEXT: mul a3, a3, a4
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x0a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 10 * vlenb
; RV64-NEXT: li a3, 32 ; RV64-NEXT: li a3, 32
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vle32.v v24, (a1) ; RV64-NEXT: vle32.v v24, (a1)
; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
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; RV64-LABEL: vpscatter_baseidx_zext_v32i32_v32f64: ; RV64-LABEL: vpscatter_baseidx_zext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: li a4, 10 ; RV64-NEXT: li a4, 10
; RV64-NEXT: mul a3, a3, a4 ; RV64-NEXT: mul a3, a3, a4
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x0a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 10 * vlenb
; RV64-NEXT: li a3, 32 ; RV64-NEXT: li a3, 32
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vle32.v v24, (a1) ; RV64-NEXT: vle32.v v24, (a1)
; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll

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define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i32 zeroext %evl) { define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i32 zeroext %evl) {
; CHECK-LABEL: select_v256i8: ; CHECK-LABEL: select_v256i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: addi a2, sp, 16 ; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vmv1r.v v2, v8 ; CHECK-NEXT: vmv1r.v v2, v8
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: li a2, 128 ; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: addi a0, a1, 128 ; CHECK-NEXT: addi a0, a1, 128
Show All 29 Lines
; CHECK-LABEL: select_evl_v256i8: ; CHECK-LABEL: select_evl_v256i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3 ; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: li a2, 128 ; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
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define <32 x i64> @select_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 zeroext %evl) { define <32 x i64> @select_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 zeroext %evl) {
; CHECK-LABEL: select_v32i64: ; CHECK-LABEL: select_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, a2, -16 ; CHECK-NEXT: addi a1, a2, -16
; CHECK-NEXT: sltu a3, a2, a1 ; CHECK-NEXT: sltu a3, a2, a1
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define <64 x float> @select_v64f32(<64 x i1> %a, <64 x float> %b, <64 x float> %c, i32 zeroext %evl) { define <64 x float> @select_v64f32(<64 x i1> %a, <64 x float> %b, <64 x float> %c, i32 zeroext %evl) {
; CHECK-LABEL: select_v64f32: ; CHECK-LABEL: select_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, a2, -32 ; CHECK-NEXT: addi a1, a2, -32
; CHECK-NEXT: sltu a3, a2, a1 ; CHECK-NEXT: sltu a3, a2, a1
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

Show First 20 Lines • Show All 271 Lines • ▼ Show 20 Lines
define <128 x i16> @vwmul_v128i16(<128 x i8>* %x, <128 x i8>* %y) { define <128 x i16> @vwmul_v128i16(<128 x i8>* %x, <128 x i8>* %y) {
; CHECK-LABEL: vwmul_v128i16: ; CHECK-LABEL: vwmul_v128i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 128 ; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1) ; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64 ; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
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define <64 x i32> @vwmul_v64i32(<64 x i16>* %x, <64 x i16>* %y) { define <64 x i32> @vwmul_v64i32(<64 x i16>* %x, <64 x i16>* %y) {
; CHECK-LABEL: vwmul_v64i32: ; CHECK-LABEL: vwmul_v64i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1) ; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
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define <32 x i64> @vwmul_v32i64(<32 x i32>* %x, <32 x i32>* %y) { define <32 x i64> @vwmul_v32i64(<32 x i32>* %x, <32 x i32>* %y) {
; CHECK-LABEL: vwmul_v32i64: ; CHECK-LABEL: vwmul_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1) ; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v16, 16 ; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll

Show First 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
define <128 x i16> @vwmulsu_v128i16(<128 x i8>* %x, <128 x i8>* %y) { define <128 x i16> @vwmulsu_v128i16(<128 x i8>* %x, <128 x i8>* %y) {
; CHECK-LABEL: vwmulsu_v128i16: ; CHECK-LABEL: vwmulsu_v128i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 128 ; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1) ; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64 ; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
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define <64 x i32> @vwmulsu_v64i32(<64 x i16>* %x, <64 x i16>* %y) { define <64 x i32> @vwmulsu_v64i32(<64 x i16>* %x, <64 x i16>* %y) {
; CHECK-LABEL: vwmulsu_v64i32: ; CHECK-LABEL: vwmulsu_v64i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1) ; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
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define <32 x i64> @vwmulsu_v32i64(<32 x i32>* %x, <32 x i32>* %y) { define <32 x i64> @vwmulsu_v32i64(<32 x i32>* %x, <32 x i32>* %y) {
; CHECK-LABEL: vwmulsu_v32i64: ; CHECK-LABEL: vwmulsu_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1) ; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v16, 16 ; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

Show First 20 Lines • Show All 247 Lines • ▼ Show 20 Lines
define <128 x i16> @vwmulu_v128i16(<128 x i8>* %x, <128 x i8>* %y) { define <128 x i16> @vwmulu_v128i16(<128 x i8>* %x, <128 x i8>* %y) {
; CHECK-LABEL: vwmulu_v128i16: ; CHECK-LABEL: vwmulu_v128i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 128 ; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vle8.v v24, (a1) ; CHECK-NEXT: vle8.v v24, (a1)
; CHECK-NEXT: li a0, 64 ; CHECK-NEXT: li a0, 64
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
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define <64 x i32> @vwmulu_v64i32(<64 x i16>* %x, <64 x i16>* %y) { define <64 x i32> @vwmulu_v64i32(<64 x i16>* %x, <64 x i16>* %y) {
; CHECK-LABEL: vwmulu_v64i32: ; CHECK-LABEL: vwmulu_v64i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vle16.v v24, (a1) ; CHECK-NEXT: vle16.v v24, (a1)
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v8, v16, a0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
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define <32 x i64> @vwmulu_v32i64(<32 x i32>* %x, <32 x i32>* %y) { define <32 x i64> @vwmulu_v32i64(<32 x i32>* %x, <32 x i32>* %y) {
; CHECK-LABEL: vwmulu_v32i64: ; CHECK-LABEL: vwmulu_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vle32.v v24, (a1) ; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v16, 16 ; CHECK-NEXT: vslidedown.vi v8, v16, 16
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
▲ Show 20 Lines • Show All 555 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/floor-vp.ll

Show First 20 Lines • Show All 733 Lines • ▼ Show 20 Lines
define <vscale x 16 x double> @vp_floor_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x double> @vp_floor_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_floor_nxv16f64: ; CHECK-LABEL: vp_floor_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3 ; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v2, v0, a2 ; CHECK-NEXT: vslidedown.vx v2, v0, a2
; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: sltu a3, a0, a2
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a3, a3, -1
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir

Show All 24 Linesbody: |
; CHECK-LABEL: name: foo ; CHECK-LABEL: name: foo
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 0 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 0
; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB ; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB
; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1 ; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1
; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10 ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10
; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB ; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB
; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 1 ; CHECK-NEXT: $x10 = frame-destroy SLLI killed $x10, 1
; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10 ; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10
; CHECK-NEXT: PseudoRET ; CHECK-NEXT: PseudoRET
bb.0: bb.0:
bb.1: bb.1:
PseudoRET PseudoRET

llvm/test/CodeGen/RISCV/rvv/localvar.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+v < %s \
; RUN: | FileCheck %s -check-prefix=RV64IV ; RUN: | FileCheck %s -check-prefix=RV64IV
define void @local_var_mf8() { define void @local_var_mf8() {
; RV64IV-LABEL: local_var_mf8: ; RV64IV-LABEL: local_var_mf8:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; RV64IV-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: vle8.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: vle8.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
Show All 11 Lines
define void @local_var_m1() { define void @local_var_m1() {
; RV64IV-LABEL: local_var_m1: ; RV64IV-LABEL: local_var_m1:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vl1r.v v8, (a0) ; RV64IV-NEXT: vl1r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vl1r.v v8, (a0) ; RV64IV-NEXT: vl1r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
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define void @local_var_m2() { define void @local_var_m2() {
; RV64IV-LABEL: local_var_m2: ; RV64IV-LABEL: local_var_m2:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
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define void @local_var_m2_mix_local_scalar() { define void @local_var_m2_mix_local_scalar() {
; RV64IV-LABEL: local_var_m2_mix_local_scalar: ; RV64IV-LABEL: local_var_m2_mix_local_scalar:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
; RV64IV-NEXT: lw a0, 12(sp) ; RV64IV-NEXT: lw a0, 12(sp)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 16 ; RV64IV-NEXT: addi a0, a0, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16 ; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vl2r.v v8, (a0) ; RV64IV-NEXT: vl2r.v v8, (a0)
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llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

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; ;
; RV64-LABEL: mgather_nxv16i64: ; RV64-LABEL: mgather_nxv16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 3 ; RV64-NEXT: slli a3, a3, 3
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: vl8re64.v v24, (a0) ; RV64-NEXT: vl8re64.v v24, (a0)
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV64-NEXT: vmv8r.v v16, v8 ; RV64-NEXT: vmv8r.v v16, v8
; RV64-NEXT: vl8re64.v v8, (a1) ; RV64-NEXT: vl8re64.v v8, (a1)
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV64-NEXT: vluxei64.v v24, (zero), v16, v0.t ; RV64-NEXT: vluxei64.v v24, (zero), v16, v0.t
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
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llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

Show First 20 Lines • Show All 1,808 Lines • ▼ Show 20 Lines
; ;
; RV64-LABEL: mscatter_nxv16f64: ; RV64-LABEL: mscatter_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3 ; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: sub sp, sp, a2 ; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: vl8re64.v v24, (a0) ; RV64-NEXT: vl8re64.v v24, (a0)
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV64-NEXT: vl8re64.v v16, (a1) ; RV64-NEXT: vl8re64.v v16, (a1)
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64-NEXT: vsoxei64.v v8, (zero), v24, v0.t ; RV64-NEXT: vsoxei64.v v8, (zero), v24, v0.t
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: srli a0, a0, 3 ; RV64-NEXT: srli a0, a0, 3
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llvm/test/CodeGen/RISCV/rvv/rint-vp.ll

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define <vscale x 16 x double> @vp_rint_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x double> @vp_rint_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_rint_nxv16f64: ; CHECK-LABEL: vp_rint_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3 ; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v2, v0, a2 ; CHECK-NEXT: vslidedown.vx v2, v0, a2
; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: sltu a3, a0, a2
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a3, a3, -1
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llvm/test/CodeGen/RISCV/rvv/round-vp.ll

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define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_round_nxv16f64: ; CHECK-LABEL: vp_round_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3 ; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v2, v0, a2 ; CHECK-NEXT: vslidedown.vx v2, v0, a2
; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: sltu a3, a0, a2
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a3, a3, -1
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llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll

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define <vscale x 16 x double> @vp_roundeven_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x double> @vp_roundeven_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_roundeven_nxv16f64: ; CHECK-LABEL: vp_roundeven_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3 ; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v2, v0, a2 ; CHECK-NEXT: vslidedown.vx v2, v0, a2
; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: sltu a3, a0, a2
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a3, a3, -1
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llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll

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define <vscale x 16 x double> @vp_roundtozero_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x double> @vp_roundtozero_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_roundtozero_nxv16f64: ; CHECK-LABEL: vp_roundtozero_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3 ; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v2, v0, a2 ; CHECK-NEXT: vslidedown.vx v2, v0, a2
; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: sltu a3, a0, a2
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a3, a3, -1
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llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

Show First 20 Lines • Show All 1,082 Lines • ▼ Show 20 Lines
define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscale x 64 x half> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) { define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscale x 64 x half> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_oeq_vv_nxv64f16: ; CHECK-LABEL: fcmp_oeq_vv_nxv64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
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; CHECK-LABEL: fcmp_oeq_vv_nxv32f64: ; CHECK-LABEL: fcmp_oeq_vv_nxv32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 48 ; CHECK-NEXT: li a3, 48
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: li a3, 40
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llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll

Show First 20 Lines • Show All 1,157 Lines • ▼ Show 20 Lines
define <vscale x 128 x i1> @icmp_eq_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> %vb, <vscale x 128 x i1> %m, i32 zeroext %evl) { define <vscale x 128 x i1> @icmp_eq_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> %vb, <vscale x 128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_eq_vv_nxv128i8: ; CHECK-LABEL: icmp_eq_vv_nxv128i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
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define <vscale x 32 x i1> @icmp_eq_vv_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i1> @icmp_eq_vv_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_eq_vv_nxv32i32: ; CHECK-LABEL: icmp_eq_vv_nxv32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
▲ Show 20 Lines • Show All 1,734 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll

Show First 20 Lines • Show All 732 Lines • ▼ Show 20 Lines
; CHECK-RV32-NEXT: # %bb.3: ; CHECK-RV32-NEXT: # %bb.3:
; CHECK-RV32-NEXT: mv a7, a4 ; CHECK-RV32-NEXT: mv a7, a4
; CHECK-RV32-NEXT: .LBB36_4: ; CHECK-RV32-NEXT: .LBB36_4:
; CHECK-RV32-NEXT: addi sp, sp, -16 ; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: csrr t0, vlenb ; CHECK-RV32-NEXT: csrr t0, vlenb
; CHECK-RV32-NEXT: slli t0, t0, 3 ; CHECK-RV32-NEXT: slli t0, t0, 3
; CHECK-RV32-NEXT: sub sp, sp, t0 ; CHECK-RV32-NEXT: sub sp, sp, t0
; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-RV32-NEXT: vl8re64.v v0, (a0) ; CHECK-RV32-NEXT: vl8re64.v v0, (a0)
; CHECK-RV32-NEXT: addi a0, sp, 16 ; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill ; CHECK-RV32-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv1r.v v0, v24 ; CHECK-RV32-NEXT: vmv1r.v v0, v24
; CHECK-RV32-NEXT: vsse64.v v8, (a1), a2, v0.t ; CHECK-RV32-NEXT: vsse64.v v8, (a1), a2, v0.t
; CHECK-RV32-NEXT: sub a0, a5, a4 ; CHECK-RV32-NEXT: sub a0, a5, a4
; CHECK-RV32-NEXT: sltu t0, a5, a0 ; CHECK-RV32-NEXT: sltu t0, a5, a0
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; CHECK-RV64-NEXT: # %bb.3: ; CHECK-RV64-NEXT: # %bb.3:
; CHECK-RV64-NEXT: mv a7, a4 ; CHECK-RV64-NEXT: mv a7, a4
; CHECK-RV64-NEXT: .LBB36_4: ; CHECK-RV64-NEXT: .LBB36_4:
; CHECK-RV64-NEXT: addi sp, sp, -16 ; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16 ; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr t0, vlenb ; CHECK-RV64-NEXT: csrr t0, vlenb
; CHECK-RV64-NEXT: slli t0, t0, 3 ; CHECK-RV64-NEXT: slli t0, t0, 3
; CHECK-RV64-NEXT: sub sp, sp, t0 ; CHECK-RV64-NEXT: sub sp, sp, t0
; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-RV64-NEXT: vl8re64.v v0, (a0) ; CHECK-RV64-NEXT: vl8re64.v v0, (a0)
; CHECK-RV64-NEXT: addi a0, sp, 16 ; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill ; CHECK-RV64-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV64-NEXT: vmv1r.v v0, v24 ; CHECK-RV64-NEXT: vmv1r.v v0, v24
; CHECK-RV64-NEXT: vsse64.v v8, (a1), a2, v0.t ; CHECK-RV64-NEXT: vsse64.v v8, (a1), a2, v0.t
; CHECK-RV64-NEXT: sub a0, a5, a4 ; CHECK-RV64-NEXT: sub a0, a5, a4
; CHECK-RV64-NEXT: sltu t0, a5, a0 ; CHECK-RV64-NEXT: sltu t0, a5, a0
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,197 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vfma_vv_nxv16f64: ; CHECK-LABEL: vfma_vv_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: li a3, 40
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: slli a1, a1, 5
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; CHECK-LABEL: vfma_vv_nxv16f64_unmasked: ; CHECK-LABEL: vfma_vv_nxv16f64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
▲ Show 20 Lines • Show All 6,393 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,197 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vfma_vv_nxv16f64: ; CHECK-LABEL: vfma_vv_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: li a3, 40
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: slli a1, a1, 5
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; CHECK-LABEL: vfma_vv_nxv16f64_unmasked: ; CHECK-LABEL: vfma_vv_nxv16f64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
▲ Show 20 Lines • Show All 6,393 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll

Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Lines
define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_nxv32i16_nxv32f32: ; CHECK-LABEL: vfptosi_nxv32i16_nxv32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2 ; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a2 ; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: slli a1, a1, 1 ; CHECK-NEXT: slli a1, a1, 1
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll

Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Lines
define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_nxv32i16_nxv32f32: ; CHECK-LABEL: vfptoui_nxv32i16_nxv32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2 ; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a2 ; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: slli a1, a1, 1 ; CHECK-NEXT: slli a1, a1, 1
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
define <vscale x 16 x float> @vfptrunc_nxv16f32_nxv16f64(<vscale x 16 x double> %a, <vscale x 16 x i1> %m, i32 zeroext %vl) { define <vscale x 16 x float> @vfptrunc_nxv16f32_nxv16f64(<vscale x 16 x double> %a, <vscale x 16 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfptrunc_nxv16f32_nxv16f64: ; CHECK-LABEL: vfptrunc_nxv16f32_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3 ; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a2 ; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1 ; CHECK-NEXT: sub a2, a0, a1
Show All 27 Lines
; CHECK-LABEL: vfptrunc_nxv32f32_nxv32f64: ; CHECK-LABEL: vfptrunc_nxv32f32_nxv32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll

Show First 20 Lines • Show All 369 Lines • ▼ Show 20 Lines
define <vscale x 128 x i8> @vpmerge_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> %vb, <vscale x 128 x i1> %m, i32 zeroext %evl) { define <vscale x 128 x i8> @vpmerge_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> %vb, <vscale x 128 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vv_nxv128i8: ; CHECK-LABEL: vpmerge_vv_nxv128i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: vmv8r.v v24, v16 ; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a4, a0, a1 ; CHECK-NEXT: add a4, a0, a1
; CHECK-NEXT: vl8r.v v16, (a4) ; CHECK-NEXT: vl8r.v v16, (a4)
▲ Show 20 Lines • Show All 1,060 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

Show First 20 Lines • Show All 2,053 Lines • ▼ Show 20 Lines
; ;
; RV64-LABEL: vpscatter_nxv16f64: ; RV64-LABEL: vpscatter_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: sub sp, sp, a1 ; RV64-NEXT: sub sp, sp, a1
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a3, a1, 3 ; RV64-NEXT: slli a3, a1, 3
; RV64-NEXT: add a3, a0, a3 ; RV64-NEXT: add a3, a0, a3
; RV64-NEXT: vl8re64.v v24, (a3) ; RV64-NEXT: vl8re64.v v24, (a3)
; RV64-NEXT: addi a3, sp, 16 ; RV64-NEXT: addi a3, sp, 16
; RV64-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV64-NEXT: vl8re64.v v24, (a0) ; RV64-NEXT: vl8re64.v v24, (a0)
; RV64-NEXT: mv a0, a2 ; RV64-NEXT: mv a0, a2
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; ;
; RV64-LABEL: vpscatter_baseidx_nxv16i16_nxv16f64: ; RV64-LABEL: vpscatter_baseidx_nxv16i16_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 4 ; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-NEXT: vl4re16.v v24, (a1) ; RV64-NEXT: vl4re16.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v26 ; RV64-NEXT: vsext.vf4 v16, v26
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; ;
; RV64-LABEL: vpscatter_baseidx_sext_nxv16i16_nxv16f64: ; RV64-LABEL: vpscatter_baseidx_sext_nxv16i16_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 4 ; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-NEXT: vl4re16.v v24, (a1) ; RV64-NEXT: vl4re16.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v26 ; RV64-NEXT: vsext.vf4 v16, v26
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; ;
; RV64-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64: ; RV64-LABEL: vpscatter_baseidx_zext_nxv16i16_nxv16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 4 ; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3 ; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-NEXT: vl4re16.v v24, (a1) ; RV64-NEXT: vl4re16.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vzext.vf4 v16, v26 ; RV64-NEXT: vzext.vf4 v16, v26
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llvm/test/CodeGen/RISCV/rvv/vpstore.ll

Show First 20 Lines • Show All 412 Lines • ▼ Show 20 Lines
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a6, a3 ; CHECK-NEXT: mv a6, a3
; CHECK-NEXT: .LBB31_4: ; CHECK-NEXT: .LBB31_4:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a7, vlenb ; CHECK-NEXT: csrr a7, vlenb
; CHECK-NEXT: slli a7, a7, 3 ; CHECK-NEXT: slli a7, a7, 3
; CHECK-NEXT: sub sp, sp, a7 ; CHECK-NEXT: sub sp, sp, a7
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vl8re64.v v0, (a0) ; CHECK-NEXT: vl8re64.v v0, (a0)
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vse64.v v8, (a1), v0.t ; CHECK-NEXT: vse64.v v8, (a1), v0.t
; CHECK-NEXT: sub a0, a5, a3 ; CHECK-NEXT: sub a0, a5, a3
; CHECK-NEXT: sltu a5, a5, a0 ; CHECK-NEXT: sltu a5, a5, a0
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llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll

Show First 20 Lines • Show All 391 Lines • ▼ Show 20 Lines
define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %va, <vscale x 16 x double> %vb) { define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %va, <vscale x 16 x double> %vb) {
; CHECK-LABEL: vselect_combine_regression: ; CHECK-LABEL: vselect_combine_regression:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vl8re64.v v8, (a1) ; CHECK-NEXT: vl8re64.v v8, (a1)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
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llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll

Show First 20 Lines • Show All 346 Lines • ▼ Show 20 Lines
define <vscale x 32 x i32> @select_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 zeroext %evl) { define <vscale x 32 x i32> @select_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 zeroext %evl) {
; CHECK-LABEL: select_nxv32i32: ; CHECK-LABEL: select_nxv32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a1, a3, 3 ; CHECK-NEXT: slli a1, a3, 3
Show All 40 Lines
define <vscale x 32 x i32> @select_evl_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c) { define <vscale x 32 x i32> @select_evl_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c) {
; CHECK-LABEL: select_evl_nxv32i32: ; CHECK-LABEL: select_evl_nxv32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 3 ; CHECK-NEXT: slli a2, a1, 3
▲ Show 20 Lines • Show All 270 Lines • ▼ Show 20 Lines
define <vscale x 16 x double> @select_nxv16f64(<vscale x 16 x i1> %a, <vscale x 16 x double> %b, <vscale x 16 x double> %c, i32 zeroext %evl) { define <vscale x 16 x double> @select_nxv16f64(<vscale x 16 x i1> %a, <vscale x 16 x double> %b, <vscale x 16 x double> %c, i32 zeroext %evl) {
; CHECK-LABEL: select_nxv16f64: ; CHECK-LABEL: select_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3 ; CHECK-NEXT: slli a3, a1, 3
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll

Show First 20 Lines • Show All 305 Lines • ▼ Show 20 Lines
define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv32f16_nxv32i32: ; CHECK-LABEL: vsitofp_nxv32f16_nxv32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2 ; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a2 ; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: slli a1, a1, 1 ; CHECK-NEXT: slli a1, a1, 1
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll

Show First 20 Lines • Show All 282 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vtrunc_nxv32i64_nxv32i32: ; CHECK-LABEL: vtrunc_nxv32i64_nxv32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll

Show First 20 Lines • Show All 305 Lines • ▼ Show 20 Lines
define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv32f16_nxv32i32: ; CHECK-LABEL: vuitofp_nxv32f16_nxv32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2 ; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a2 ; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: slli a1, a1, 1 ; CHECK-NEXT: slli a1, a1, 1
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llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir

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; CHECK-NEXT: SD killed $x8, $x2, 48 :: (store (s64) into %stack.3) ; CHECK-NEXT: SD killed $x8, $x2, 48 :: (store (s64) into %stack.3)
; CHECK-NEXT: SD killed $x9, $x2, 40 :: (store (s64) into %stack.4) ; CHECK-NEXT: SD killed $x9, $x2, 40 :: (store (s64) into %stack.4)
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -24 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -24
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -32 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -32
; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -40 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -40
; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB ; CHECK-NEXT: $x10 = frame-setup PseudoReadVLENB
; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1 ; CHECK-NEXT: $x10 = frame-setup SLLI killed $x10, 1
; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10 ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10
; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
; CHECK-NEXT: renamable $x8 = COPY $x14 ; CHECK-NEXT: renamable $x8 = COPY $x14
; CHECK-NEXT: renamable $x9 = COPY $x11 ; CHECK-NEXT: renamable $x9 = COPY $x11
; CHECK-NEXT: $x10 = PseudoReadVLENB ; CHECK-NEXT: $x10 = PseudoReadVLENB
; CHECK-NEXT: $x10 = SLLI killed $x10, 1 ; CHECK-NEXT: $x10 = SLLI killed $x10, 1
; CHECK-NEXT: $x10 = ADD $x2, killed $x10 ; CHECK-NEXT: $x10 = ADD $x2, killed $x10
; CHECK-NEXT: SD killed renamable $x17, killed $x10, 72 :: (store (s64)) ; CHECK-NEXT: SD killed renamable $x17, killed $x10, 72 :: (store (s64))
; CHECK-NEXT: $x10 = PseudoReadVLENB ; CHECK-NEXT: $x10 = PseudoReadVLENB
; CHECK-NEXT: $x10 = SLLI killed $x10, 1 ; CHECK-NEXT: $x10 = SLLI killed $x10, 1
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llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

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; CHECK-LABEL: name: zvlsseg_spill ; CHECK-LABEL: name: zvlsseg_spill
; CHECK: liveins: $x10, $x11 ; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16 ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16
; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB ; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB
; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 3 ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 3
; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12 ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12
; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 renamable $x10, $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 renamable $x10, $noreg, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: $x11 = ADDI $x2, 16 ; CHECK-NEXT: $x11 = ADDI $x2, 16
; CHECK-NEXT: $x12 = PseudoReadVLENB ; CHECK-NEXT: $x12 = PseudoReadVLENB
; CHECK-NEXT: PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, killed $x11, killed $x12 ; CHECK-NEXT: PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, killed $x11, killed $x12
; CHECK-NEXT: $x11 = ADDI $x2, 16 ; CHECK-NEXT: $x11 = ADDI $x2, 16
; CHECK-NEXT: $x12 = PseudoReadVLENB ; CHECK-NEXT: $x12 = PseudoReadVLENB
; CHECK-NEXT: dead renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 killed $x11, killed $x12, implicit-def $v8 ; CHECK-NEXT: dead renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 killed $x11, killed $x12, implicit-def $v8
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