[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.

[craig.topper]

Summary

This is an alternative to fix PR57939 for RISC-V. It definitely
can be argued that the stack temporaries for RISC-V are being created
with an unnecessarily large alignment. But ignoring the alignment
in MachineFrameInfo also seems bad.

Looking at the test update that go with the current ID==0 check,
it was intending to exclude things like the NoAlloc stackid. So I'm
not sure if scalable vectors are intentionally being excluded.

[frasercrmck]

Seems like a reasonable approach to me. I feel it's too difficult for targets to account for the alignment of non-default stack IDs themselves. And that's without your suspicions that scalable vectors may not even be knowingly excluded at the present time.

llvm/include/llvm/CodeGen/MachineFrameInfo.h

498

Maybe a shared helper function like contributesToMaxAlignment(uint8_t ID) to group code together?

[craig.topper]

Rebase tests. Still need to address review feedback

[craig.topper]

Add function as suggested.

[reames]

LGTM, this looks to be in the spirit of the existing code.

In a follow up, we should probably adjust estimateStackSize in an analogous manner.

llvm/include/llvm/CodeGen/MachineFrameInfo.h

 //===-- CodeGen/MachineFrameInfo.h - Abstract Stack Frame Rep. --*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // The file defines the MachineFrameInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_MACHINEFRAMEINFO_H
 #define LLVM_CODEGEN_MACHINEFRAMEINFO_H
 
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/Register.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/Support/Alignment.h"
 #include <cassert>
 #include <vector>
 
 namespace llvm {
 class raw_ostream;
 class MachineFunction;
 class MachineBasicBlock;
public:
   }
 
   /// setObjectAlignment - Change the alignment of the specified stack object.
   void setObjectAlignment(int ObjectIdx, Align Alignment) {
     assert(unsigned(ObjectIdx + NumFixedObjects) < Objects.size() &&
            "Invalid Object Idx!");
     Objects[ObjectIdx + NumFixedObjects].Alignment = Alignment;
 
-    // Only ensure max alignment for the default stack.
-    if (getStackID(ObjectIdx) == 0)
+    // Only ensure max alignment for the default and scalable vector stack.
+    uint8_t StackID = getStackID(ObjectIdx);
+    if (StackID == TargetStackID::Default ||
+        StackID == TargetStackID::ScalableVector)
       ensureMaxAlignment(Alignment);
   }
 
   /// Return the underlying Alloca of the specified
   /// stack object if it exists. Returns 0 if none exists.
   const AllocaInst* getObjectAllocation(int ObjectIdx) const {
     assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() &&
            "Invalid Object Idx!");

llvm/lib/CodeGen/MachineFrameInfo.cpp

 //===-- MachineFrameInfo.cpp ---------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
int MachineFrameInfo::CreateStackObject(uint64_t Size, Align Alignment,
                                         const AllocaInst *Alloca,
                                         uint8_t StackID) {
   assert(Size != 0 && "Cannot allocate zero size stack objects!");
   Alignment = clampStackAlignment(!StackRealignable, Alignment, StackAlignment);
   Objects.push_back(StackObject(Size, Alignment, 0, false, IsSpillSlot, Alloca,
                                 !IsSpillSlot, StackID));
   int Index = (int)Objects.size() - NumFixedObjects - 1;
   assert(Index >= 0 && "Bad frame index!");
-  if (StackID == 0)
+  if (StackID == TargetStackID::Default ||
+      StackID == TargetStackID::ScalableVector)
     ensureMaxAlignment(Alignment);
   return Index;
 }
 
 int MachineFrameInfo::CreateSpillStackObject(uint64_t Size, Align Alignment) {
   Alignment = clampStackAlignment(!StackRealignable, Alignment, StackAlignment);
   CreateStackObject(Size, Alignment, true);
   int Index = (int)Objects.size() - NumFixedObjects - 1;

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
         .setMIFlag(MachineInstr::FrameSetup);
   }
 
   // Generate new FP.
   if (hasFP(MF)) {
     if (STI.isRegisterReservedByUser(FPReg))
       MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
           MF.getFunction(), "Frame pointer required, but has been reserved."});
+    // The frame pointer does need to be reserved from register allocation.
+    assert(MF.getRegInfo().isReserved(FPReg) && "FP not reserved");
 
     adjustReg(MBB, MBBI, DL, FPReg, SPReg,
               RealStackSize - RVFI->getVarArgsSaveSize(),
               MachineInstr::FrameSetup);
 
     // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()"
     unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
         nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize()));

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

 declare <vscale x 32 x i32> @ext3(<vscale x 32 x i32>, <vscale x 32 x i32>, <vscale x 32 x i32>, i32, i32)
 
 define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_i32(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y, i32 %w) {
 ; RV32-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -144
 ; RV32-NEXT:    .cfi_def_cfa_offset 144
 ; RV32-NEXT:    sw ra, 140(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 136(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 144
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    slli a1, a1, 4
 ; RV32-NEXT:    sub sp, sp, a1
 ; RV32-NEXT:    andi sp, sp, -128
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    slli a1, a1, 3
 ; RV32-NEXT:    add a3, a0, a1
 ; RV32-NEXT:    vl8re32.v v24, (a3)
 ; RV32-NEXT:    vl8re32.v v0, (a0)
 ; RV32-NEXT:    addi a0, sp, 128
 ; RV32-NEXT:    vs8r.v v8, (a0)
 ; RV32-NEXT:    add a1, a0, a1
 ; RV32-NEXT:    addi a0, sp, 128
 ; RV32-NEXT:    li a3, 2
 ; RV32-NEXT:    vs8r.v v16, (a1)
 ; RV32-NEXT:    vmv8r.v v8, v0
 ; RV32-NEXT:    vmv8r.v v16, v24
 ; RV32-NEXT:    call ext2@plt
 ; RV32-NEXT:    addi sp, s0, -144
 ; RV32-NEXT:    lw ra, 140(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 136(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 144
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -144
 ; RV64-NEXT:    .cfi_def_cfa_offset 144
 ; RV64-NEXT:    sd ra, 136(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 128(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 144
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 4
 ; RV64-NEXT:    sub sp, sp, a1
 ; RV64-NEXT:    andi sp, sp, -128
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 3
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    vl8re32.v v24, (a3)
 ; RV64-NEXT:    vl8re32.v v0, (a0)
 ; RV64-NEXT:    addi a0, sp, 128
 ; RV64-NEXT:    vs8r.v v8, (a0)
 ; RV64-NEXT:    add a1, a0, a1
 ; RV64-NEXT:    addi a0, sp, 128
 ; RV64-NEXT:    li a3, 2
 ; RV64-NEXT:    vs8r.v v16, (a1)
 ; RV64-NEXT:    vmv8r.v v8, v0
 ; RV64-NEXT:    vmv8r.v v16, v24
 ; RV64-NEXT:    call ext2@plt
 ; RV64-NEXT:    addi sp, s0, -144
 ; RV64-NEXT:    ld ra, 136(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 128(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 144
 ; RV64-NEXT:    ret
   %t = call fastcc <vscale x 32 x i32> @ext2(<vscale x 32 x i32> %y, <vscale x 32 x i32> %x, i32 %w, i32 2)
   ret <vscale x 32 x i32> %t
 }
 
 define fastcc <vscale x 32 x i32> @ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_i32(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y, <vscale x 32 x i32> %z, i32 %w) {
 ; RV32-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -144
 ; RV32-NEXT:    .cfi_def_cfa_offset 144
 ; RV32-NEXT:    sw ra, 140(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 136(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 144
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    li a3, 48
 ; RV32-NEXT:    mul a1, a1, a3
 ; RV32-NEXT:    sub sp, sp, a1
 ; RV32-NEXT:    andi sp, sp, -128
 ; RV32-NEXT:    csrr a1, vlenb

 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    slli a1, a1, 3
 ; RV32-NEXT:    add a1, sp, a1
 ; RV32-NEXT:    addi a1, a1, 128
 ; RV32-NEXT:    vl8re8.v v16, (a1) # Unknown-size Folded Reload
 ; RV32-NEXT:    call ext3@plt
 ; RV32-NEXT:    addi sp, s0, -144
 ; RV32-NEXT:    lw ra, 140(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 136(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 144
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ret_nxv32i32_call_nxv32i32_nxv32i32_nxv32i32_i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -144
 ; RV64-NEXT:    .cfi_def_cfa_offset 144
 ; RV64-NEXT:    sd ra, 136(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 128(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 144
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    li a3, 48
 ; RV64-NEXT:    mul a1, a1, a3
 ; RV64-NEXT:    sub sp, sp, a1
 ; RV64-NEXT:    andi sp, sp, -128
 ; RV64-NEXT:    csrr a1, vlenb

 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 3
 ; RV64-NEXT:    add a1, sp, a1
 ; RV64-NEXT:    addi a1, a1, 128
 ; RV64-NEXT:    vl8re8.v v16, (a1) # Unknown-size Folded Reload
 ; RV64-NEXT:    call ext3@plt
 ; RV64-NEXT:    addi sp, s0, -144
 ; RV64-NEXT:    ld ra, 136(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 128(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 144
 ; RV64-NEXT:    ret
   %t = call fastcc <vscale x 32 x i32> @ext3(<vscale x 32 x i32> %z, <vscale x 32 x i32> %y, <vscale x 32 x i32> %x, i32 %w, i32 42)
   ret <vscale x 32 x i32> %t
 }
 
 ; A test case where the normal calling convention would pass directly via the
 ; stack, but with fastcc can pass indirectly with the extra GPR registers

 
 ; Calling the function above. Ensure we pass the arguments correctly.
 define fastcc <vscale x 32 x i32> @pass_vector_arg_indirect_stack(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y, <vscale x 32 x i32> %z) {
 ; RV32-LABEL: pass_vector_arg_indirect_stack:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -144
 ; RV32-NEXT:    .cfi_def_cfa_offset 144
 ; RV32-NEXT:    sw ra, 140(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 136(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 144
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    csrr a0, vlenb
 ; RV32-NEXT:    slli a0, a0, 5
 ; RV32-NEXT:    sub sp, sp, a0
 ; RV32-NEXT:    andi sp, sp, -128
 ; RV32-NEXT:    csrr a0, vlenb
 ; RV32-NEXT:    slli a0, a0, 3

 ; RV32-NEXT:    addi t4, sp, 128
 ; RV32-NEXT:    li t6, 8
 ; RV32-NEXT:    vs8r.v v8, (a0)
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    vmv.v.i v16, 0
 ; RV32-NEXT:    call vector_arg_indirect_stack@plt
 ; RV32-NEXT:    addi sp, s0, -144
 ; RV32-NEXT:    lw ra, 140(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 136(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 144
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: pass_vector_arg_indirect_stack:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -144
 ; RV64-NEXT:    .cfi_def_cfa_offset 144
 ; RV64-NEXT:    sd ra, 136(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 128(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 144
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    csrr a0, vlenb
 ; RV64-NEXT:    slli a0, a0, 5
 ; RV64-NEXT:    sub sp, sp, a0
 ; RV64-NEXT:    andi sp, sp, -128
 ; RV64-NEXT:    csrr a0, vlenb
 ; RV64-NEXT:    slli a0, a0, 3

 ; RV64-NEXT:    addi t4, sp, 128
 ; RV64-NEXT:    li t6, 8
 ; RV64-NEXT:    vs8r.v v8, (a0)
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    vmv.v.i v16, 0
 ; RV64-NEXT:    call vector_arg_indirect_stack@plt
 ; RV64-NEXT:    addi sp, s0, -144
 ; RV64-NEXT:    ld ra, 136(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 128(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 144
 ; RV64-NEXT:    ret
   %s = call fastcc <vscale x 32 x i32> @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> zeroinitializer, i32 8)
   ret <vscale x 32 x i32> %s
 }

llvm/test/CodeGen/RISCV/rvv/calling-conv.ll

 
 ; Call the function above. Check that we set the arguments correctly.
 define <vscale x 32 x i32> @caller_scalable_vector_split_indirect(<vscale x 32 x i32> %x) {
 ; RV32-LABEL: caller_scalable_vector_split_indirect:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi sp, sp, -144
 ; RV32-NEXT:    .cfi_def_cfa_offset 144
 ; RV32-NEXT:    sw ra, 140(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 136(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 144
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    csrr a0, vlenb
 ; RV32-NEXT:    slli a0, a0, 4
 ; RV32-NEXT:    sub sp, sp, a0
 ; RV32-NEXT:    andi sp, sp, -128
 ; RV32-NEXT:    addi a0, sp, 128
 ; RV32-NEXT:    vs8r.v v8, (a0)
 ; RV32-NEXT:    csrr a1, vlenb
 ; RV32-NEXT:    slli a1, a1, 3
 ; RV32-NEXT:    add a0, a0, a1
 ; RV32-NEXT:    vs8r.v v16, (a0)
 ; RV32-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    addi a0, sp, 128
 ; RV32-NEXT:    vmv.v.i v16, 0
 ; RV32-NEXT:    call callee_scalable_vector_split_indirect@plt
 ; RV32-NEXT:    addi sp, s0, -144
 ; RV32-NEXT:    lw ra, 140(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 136(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 144
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: caller_scalable_vector_split_indirect:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -144
 ; RV64-NEXT:    .cfi_def_cfa_offset 144
 ; RV64-NEXT:    sd ra, 136(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 128(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 144
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    csrr a0, vlenb
 ; RV64-NEXT:    slli a0, a0, 4
 ; RV64-NEXT:    sub sp, sp, a0
 ; RV64-NEXT:    andi sp, sp, -128
 ; RV64-NEXT:    addi a0, sp, 128
 ; RV64-NEXT:    vs8r.v v8, (a0)
 ; RV64-NEXT:    csrr a1, vlenb
 ; RV64-NEXT:    slli a1, a1, 3
 ; RV64-NEXT:    add a0, a0, a1
 ; RV64-NEXT:    vs8r.v v16, (a0)
 ; RV64-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
 ; RV64-NEXT:    vmv.v.i v8, 0
 ; RV64-NEXT:    addi a0, sp, 128
 ; RV64-NEXT:    vmv.v.i v16, 0
 ; RV64-NEXT:    call callee_scalable_vector_split_indirect@plt
 ; RV64-NEXT:    addi sp, s0, -144
 ; RV64-NEXT:    ld ra, 136(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 128(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 144
 ; RV64-NEXT:    ret
   %c = alloca i64
   %a = call <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> %x)
   ret <vscale x 32 x i32> %a
 }

llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define half @extractelt_nxv1f16_0(<vscale x 1 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv1f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x half> %v, i32 0

 ; CHECK-NEXT:    vsetivli zero, 0, e64, m8, ta, ma
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x double> %v, i32 0
   ret double %r
 }
 
 define double @extractelt_nxv16f64_neg1(<vscale x 16 x double> %v) {
-; CHECK-LABEL: extractelt_nxv16f64_neg1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    addi s0, sp, 64
-; CHECK-NEXT:    .cfi_def_cfa s0, 0
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 4
-; CHECK-NEXT:    sub sp, sp, a0
-; CHECK-NEXT:    andi sp, sp, -64
-; CHECK-NEXT:    addi a0, sp, 64
-; CHECK-NEXT:    vs8r.v v8, (a0)
-; CHECK-NEXT:    csrr a1, vlenb
-; CHECK-NEXT:    slli a2, a1, 3
-; CHECK-NEXT:    add a2, a0, a2
-; CHECK-NEXT:    vs8r.v v16, (a2)
-; CHECK-NEXT:    slli a1, a1, 4
-; CHECK-NEXT:    add a0, a1, a0
-; CHECK-NEXT:    fld fa0, -8(a0)
-; CHECK-NEXT:    addi sp, s0, -64
-; CHECK-NEXT:    addi sp, sp, 64
-; CHECK-NEXT:    ret
+; CHECK-32-LABEL: extractelt_nxv16f64_neg1:
+; CHECK-32:       # %bb.0:
+; CHECK-32-NEXT:    addi sp, sp, -80
+; CHECK-32-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; CHECK-32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; CHECK-32-NEXT:    .cfi_offset ra, -4
+; CHECK-32-NEXT:    .cfi_offset s0, -8
+; CHECK-32-NEXT:    addi s0, sp, 80
+; CHECK-32-NEXT:    .cfi_def_cfa s0, 0
+; CHECK-32-NEXT:    csrr a0, vlenb
+; CHECK-32-NEXT:    slli a0, a0, 4
+; CHECK-32-NEXT:    sub sp, sp, a0
+; CHECK-32-NEXT:    andi sp, sp, -64
+; CHECK-32-NEXT:    addi a0, sp, 64
+; CHECK-32-NEXT:    vs8r.v v8, (a0)
+; CHECK-32-NEXT:    csrr a1, vlenb
+; CHECK-32-NEXT:    slli a2, a1, 3
+; CHECK-32-NEXT:    add a2, a0, a2
+; CHECK-32-NEXT:    vs8r.v v16, (a2)
+; CHECK-32-NEXT:    slli a1, a1, 4
+; CHECK-32-NEXT:    add a0, a1, a0
+; CHECK-32-NEXT:    fld fa0, -8(a0)
+; CHECK-32-NEXT:    addi sp, s0, -80
+; CHECK-32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; CHECK-32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; CHECK-32-NEXT:    addi sp, sp, 80
+; CHECK-32-NEXT:    ret
+;
+; CHECK-64-LABEL: extractelt_nxv16f64_neg1:
+; CHECK-64:       # %bb.0:
+; CHECK-64-NEXT:    addi sp, sp, -80
+; CHECK-64-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; CHECK-64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; CHECK-64-NEXT:    .cfi_offset ra, -8
+; CHECK-64-NEXT:    .cfi_offset s0, -16
+; CHECK-64-NEXT:    addi s0, sp, 80
+; CHECK-64-NEXT:    .cfi_def_cfa s0, 0
+; CHECK-64-NEXT:    csrr a0, vlenb
+; CHECK-64-NEXT:    slli a0, a0, 4
+; CHECK-64-NEXT:    sub sp, sp, a0
+; CHECK-64-NEXT:    andi sp, sp, -64
+; CHECK-64-NEXT:    addi a0, sp, 64
+; CHECK-64-NEXT:    vs8r.v v8, (a0)
+; CHECK-64-NEXT:    csrr a1, vlenb
+; CHECK-64-NEXT:    slli a2, a1, 3
+; CHECK-64-NEXT:    add a2, a0, a2
+; CHECK-64-NEXT:    vs8r.v v16, (a2)
+; CHECK-64-NEXT:    slli a1, a1, 4
+; CHECK-64-NEXT:    add a0, a1, a0
+; CHECK-64-NEXT:    fld fa0, -8(a0)
+; CHECK-64-NEXT:    addi sp, s0, -80
+; CHECK-64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; CHECK-64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; CHECK-64-NEXT:    addi sp, sp, 80
+; CHECK-64-NEXT:    ret
+; RV32-LABEL: extractelt_nxv16f64_neg1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -80
+; RV32-NEXT:    .cfi_def_cfa_offset 80
+; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
+; RV32-NEXT:    addi s0, sp, 80
+; RV32-NEXT:    .cfi_def_cfa s0, 0
+; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    slli a0, a0, 4
+; RV32-NEXT:    sub sp, sp, a0
+; RV32-NEXT:    andi sp, sp, -64
+; RV32-NEXT:    addi a0, sp, 64
+; RV32-NEXT:    vs8r.v v8, (a0)
+; RV32-NEXT:    csrr a1, vlenb
+; RV32-NEXT:    slli a2, a1, 3
+; RV32-NEXT:    add a2, a0, a2
+; RV32-NEXT:    vs8r.v v16, (a2)
+; RV32-NEXT:    slli a1, a1, 4
+; RV32-NEXT:    add a0, a1, a0
+; RV32-NEXT:    fld fa0, -8(a0)
+; RV32-NEXT:    addi sp, s0, -80
+; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; RV32-NEXT:    addi sp, sp, 80
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: extractelt_nxv16f64_neg1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi sp, sp, -80
+; RV64-NEXT:    .cfi_def_cfa_offset 80
+; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
+; RV64-NEXT:    addi s0, sp, 80
+; RV64-NEXT:    .cfi_def_cfa s0, 0
+; RV64-NEXT:    csrr a0, vlenb
+; RV64-NEXT:    slli a0, a0, 4
+; RV64-NEXT:    sub sp, sp, a0
+; RV64-NEXT:    andi sp, sp, -64
+; RV64-NEXT:    addi a0, sp, 64
+; RV64-NEXT:    vs8r.v v8, (a0)
+; RV64-NEXT:    csrr a1, vlenb
+; RV64-NEXT:    slli a2, a1, 3
+; RV64-NEXT:    add a2, a0, a2
+; RV64-NEXT:    vs8r.v v16, (a2)
+; RV64-NEXT:    slli a1, a1, 4
+; RV64-NEXT:    add a0, a1, a0
+; RV64-NEXT:    fld fa0, -8(a0)
+; RV64-NEXT:    addi sp, s0, -80
+; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; RV64-NEXT:    addi sp, sp, 80
+; RV64-NEXT:    ret
   %r = extractelement <vscale x 16 x double> %v, i32 -1
   ret double %r
 }
 
 define double @extractelt_nxv16f64_imm(<vscale x 16 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv16f64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e64, m8, ta, ma
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x double> %v, i32 2
   ret double %r
 }
 
 define double @extractelt_nxv16f64_idx(<vscale x 16 x double> %v, i32 signext %idx) {
-; CHECK-LABEL: extractelt_nxv16f64_idx:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    csrr a1, vlenb
-; CHECK-NEXT:    slli a2, a1, 1
-; CHECK-NEXT:    addi a2, a2, -1
-; CHECK-NEXT:    bltu a0, a2, .LBB54_2
-; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    mv a0, a2
-; CHECK-NEXT:  .LBB54_2:
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    addi s0, sp, 64
-; CHECK-NEXT:    .cfi_def_cfa s0, 0
-; CHECK-NEXT:    csrr a2, vlenb
-; CHECK-NEXT:    slli a2, a2, 4
-; CHECK-NEXT:    sub sp, sp, a2
-; CHECK-NEXT:    andi sp, sp, -64
-; CHECK-NEXT:    slli a0, a0, 3
-; CHECK-NEXT:    addi a2, sp, 64
-; CHECK-NEXT:    add a0, a2, a0
-; CHECK-NEXT:    vs8r.v v8, (a2)
-; CHECK-NEXT:    slli a1, a1, 3
-; CHECK-NEXT:    add a1, a2, a1
-; CHECK-NEXT:    vs8r.v v16, (a1)
-; CHECK-NEXT:    fld fa0, 0(a0)
-; CHECK-NEXT:    addi sp, s0, -64
-; CHECK-NEXT:    addi sp, sp, 64
-; CHECK-NEXT:    ret
+; RV32-LABEL: extractelt_nxv16f64_idx:
+; RV32:       # %bb.0:
+; RV32-NEXT:    csrr a1, vlenb
+; RV32-NEXT:    slli a2, a1, 1
+; RV32-NEXT:    addi a2, a2, -1
+; RV32-NEXT:    bltu a0, a2, .LBB54_2
+; RV32-NEXT:  # %bb.1:
+; RV32-NEXT:    mv a0, a2
+; RV32-NEXT:  .LBB54_2:
+; RV32-NEXT:    addi sp, sp, -80
+; RV32-NEXT:    .cfi_def_cfa_offset 80
+; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
+; RV32-NEXT:    addi s0, sp, 80
+; RV32-NEXT:    .cfi_def_cfa s0, 0
+; RV32-NEXT:    csrr a2, vlenb
+; RV32-NEXT:    slli a2, a2, 4
+; RV32-NEXT:    sub sp, sp, a2
+; RV32-NEXT:    andi sp, sp, -64
+; RV32-NEXT:    slli a0, a0, 3
+; RV32-NEXT:    addi a2, sp, 64
+; RV32-NEXT:    add a0, a2, a0
+; RV32-NEXT:    vs8r.v v8, (a2)
+; RV32-NEXT:    slli a1, a1, 3
+; RV32-NEXT:    add a1, a2, a1
+; RV32-NEXT:    vs8r.v v16, (a1)
+; RV32-NEXT:    fld fa0, 0(a0)
+; RV32-NEXT:    addi sp, s0, -80
+; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; RV32-NEXT:    addi sp, sp, 80
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: extractelt_nxv16f64_idx:
+; RV64:       # %bb.0:
+; RV64-NEXT:    csrr a1, vlenb
+; RV64-NEXT:    slli a2, a1, 1
+; RV64-NEXT:    addi a2, a2, -1
+; RV64-NEXT:    bltu a0, a2, .LBB54_2
+; RV64-NEXT:  # %bb.1:
+; RV64-NEXT:    mv a0, a2
+; RV64-NEXT:  .LBB54_2:
+; RV64-NEXT:    addi sp, sp, -80
+; RV64-NEXT:    .cfi_def_cfa_offset 80
+; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
+; RV64-NEXT:    addi s0, sp, 80
+; RV64-NEXT:    .cfi_def_cfa s0, 0
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    slli a2, a2, 4
+; RV64-NEXT:    sub sp, sp, a2
+; RV64-NEXT:    andi sp, sp, -64
+; RV64-NEXT:    slli a0, a0, 3
+; RV64-NEXT:    addi a2, sp, 64
+; RV64-NEXT:    add a0, a2, a0
+; RV64-NEXT:    vs8r.v v8, (a2)
+; RV64-NEXT:    slli a1, a1, 3
+; RV64-NEXT:    add a1, a2, a1
+; RV64-NEXT:    vs8r.v v16, (a1)
+; RV64-NEXT:    fld fa0, 0(a0)
+; RV64-NEXT:    addi sp, s0, -80
+; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; RV64-NEXT:    addi sp, sp, 80
+; RV64-NEXT:    ret
   %r = extractelement <vscale x 16 x double> %v, i32 %idx
   ret double %r
 }

llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define i1 @extractelt_nxv1i1(<vscale x 1 x i8>* %x, i64 %idx) nounwind {
 ; CHECK-LABEL: extractelt_nxv1i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a2, zero, e8, mf8, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    vmseq.vi v0, v8, 0
 ; CHECK-NEXT:    vmv.v.i v8, 0

 ; CHECK-NEXT:    ret
   %a = load <vscale x 64 x i8>, <vscale x 64 x i8>* %x
   %b = icmp eq <vscale x 64 x i8> %a, zeroinitializer
   %c = extractelement <vscale x 64 x i1> %b, i64 %idx
   ret i1 %c
 }
 
 define i1 @extractelt_nxv128i1(<vscale x 128 x i8>* %x, i64 %idx) nounwind {
-; CHECK-LABEL: extractelt_nxv128i1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    csrr a2, vlenb
-; CHECK-NEXT:    slli a3, a2, 4
-; CHECK-NEXT:    addi a3, a3, -1
-; CHECK-NEXT:    bltu a1, a3, .LBB7_2
-; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    mv a1, a3
-; CHECK-NEXT:  .LBB7_2:
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    addi s0, sp, 64
-; CHECK-NEXT:    csrr a3, vlenb
-; CHECK-NEXT:    slli a3, a3, 4
-; CHECK-NEXT:    sub sp, sp, a3
-; CHECK-NEXT:    andi sp, sp, -64
-; CHECK-NEXT:    addi a3, sp, 64
-; CHECK-NEXT:    slli a2, a2, 3
-; CHECK-NEXT:    add a4, a0, a2
-; CHECK-NEXT:    vl8r.v v16, (a4)
-; CHECK-NEXT:    vl8r.v v24, (a0)
-; CHECK-NEXT:    add a0, a3, a1
-; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-NEXT:    vmseq.vi v8, v16, 0
-; CHECK-NEXT:    vmseq.vi v0, v24, 0
-; CHECK-NEXT:    vmv.v.i v16, 0
-; CHECK-NEXT:    vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT:    vs8r.v v24, (a3)
-; CHECK-NEXT:    add a1, a3, a2
-; CHECK-NEXT:    vmv1r.v v0, v8
-; CHECK-NEXT:    vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT:    vs8r.v v8, (a1)
-; CHECK-NEXT:    lb a0, 0(a0)
-; CHECK-NEXT:    addi sp, s0, -64
-; CHECK-NEXT:    addi sp, sp, 64
-; CHECK-NEXT:    ret
+; RV32-LABEL: extractelt_nxv128i1:
+; RV32:       # %bb.0:
+; RV32-NEXT:    csrr a2, vlenb
+; RV32-NEXT:    slli a3, a2, 4
+; RV32-NEXT:    addi a3, a3, -1
+; RV32-NEXT:    bltu a1, a3, .LBB7_2
+; RV32-NEXT:  # %bb.1:
+; RV32-NEXT:    mv a1, a3
+; RV32-NEXT:  .LBB7_2:
+; RV32-NEXT:    addi sp, sp, -80
+; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; RV32-NEXT:    addi s0, sp, 80
+; RV32-NEXT:    csrr a3, vlenb
+; RV32-NEXT:    slli a3, a3, 4
+; RV32-NEXT:    sub sp, sp, a3
+; RV32-NEXT:    andi sp, sp, -64
+; RV32-NEXT:    addi a3, sp, 64
+; RV32-NEXT:    slli a2, a2, 3
+; RV32-NEXT:    add a4, a0, a2
+; RV32-NEXT:    vl8r.v v16, (a4)
+; RV32-NEXT:    vl8r.v v24, (a0)
+; RV32-NEXT:    add a0, a3, a1
+; RV32-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
+; RV32-NEXT:    vmseq.vi v8, v16, 0
+; RV32-NEXT:    vmseq.vi v0, v24, 0
+; RV32-NEXT:    vmv.v.i v16, 0
+; RV32-NEXT:    vmerge.vim v24, v16, 1, v0
+; RV32-NEXT:    vs8r.v v24, (a3)
+; RV32-NEXT:    add a1, a3, a2
+; RV32-NEXT:    vmv1r.v v0, v8
+; RV32-NEXT:    vmerge.vim v8, v16, 1, v0
+; RV32-NEXT:    vs8r.v v8, (a1)
+; RV32-NEXT:    lb a0, 0(a0)
+; RV32-NEXT:    addi sp, s0, -80
+; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; RV32-NEXT:    addi sp, sp, 80
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: extractelt_nxv128i1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    slli a3, a2, 4
+; RV64-NEXT:    addi a3, a3, -1
+; RV64-NEXT:    bltu a1, a3, .LBB7_2
+; RV64-NEXT:  # %bb.1:
+; RV64-NEXT:    mv a1, a3
+; RV64-NEXT:  .LBB7_2:
+; RV64-NEXT:    addi sp, sp, -80
+; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; RV64-NEXT:    addi s0, sp, 80
+; RV64-NEXT:    csrr a3, vlenb
+; RV64-NEXT:    slli a3, a3, 4
+; RV64-NEXT:    sub sp, sp, a3
+; RV64-NEXT:    andi sp, sp, -64
+; RV64-NEXT:    addi a3, sp, 64
+; RV64-NEXT:    slli a2, a2, 3
+; RV64-NEXT:    add a4, a0, a2
+; RV64-NEXT:    vl8r.v v16, (a4)
+; RV64-NEXT:    vl8r.v v24, (a0)
+; RV64-NEXT:    add a0, a3, a1
+; RV64-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
+; RV64-NEXT:    vmseq.vi v8, v16, 0
+; RV64-NEXT:    vmseq.vi v0, v24, 0
+; RV64-NEXT:    vmv.v.i v16, 0
+; RV64-NEXT:    vmerge.vim v24, v16, 1, v0
+; RV64-NEXT:    vs8r.v v24, (a3)
+; RV64-NEXT:    add a1, a3, a2
+; RV64-NEXT:    vmv1r.v v0, v8
+; RV64-NEXT:    vmerge.vim v8, v16, 1, v0
+; RV64-NEXT:    vs8r.v v8, (a1)
+; RV64-NEXT:    lb a0, 0(a0)
+; RV64-NEXT:    addi sp, s0, -80
+; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; RV64-NEXT:    addi sp, sp, 80
+; RV64-NEXT:    ret
   %a = load <vscale x 128 x i8>, <vscale x 128 x i8>* %x
   %b = icmp eq <vscale x 128 x i8> %a, zeroinitializer
   %c = extractelement <vscale x 128 x i1> %b, i64 %idx
   ret i1 %c
 }

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i32> %v, i32 0
   ret i32 %r
 }
 
 define i32 @extractelt_nxv32i32_neg1(<vscale x 32 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv32i32_neg1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    addi s0, sp, 64
+; CHECK-NEXT:    addi sp, sp, -80
+; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -4
+; CHECK-NEXT:    .cfi_offset s0, -8
+; CHECK-NEXT:    addi s0, sp, 80
 ; CHECK-NEXT:    .cfi_def_cfa s0, 0
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 4
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -64
 ; CHECK-NEXT:    addi a0, sp, 64
 ; CHECK-NEXT:    vs8r.v v8, (a0)
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a2, a1, 3
 ; CHECK-NEXT:    add a2, a0, a2
 ; CHECK-NEXT:    vs8r.v v16, (a2)
 ; CHECK-NEXT:    slli a1, a1, 4
 ; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    lw a0, -4(a0)
-; CHECK-NEXT:    addi sp, s0, -64
-; CHECK-NEXT:    addi sp, sp, 64
+; CHECK-NEXT:    addi sp, s0, -80
+; CHECK-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 80
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i32> %v, i32 -1
   ret i32 %r
 }
 
 define i32 @extractelt_nxv32i32_imm(<vscale x 32 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv32i32_imm:
 ; CHECK:       # %bb.0:

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a2, a1, 2
 ; CHECK-NEXT:    addi a2, a2, -1
 ; CHECK-NEXT:    bltu a0, a2, .LBB74_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, a2
 ; CHECK-NEXT:  .LBB74_2:
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    addi s0, sp, 64
+; CHECK-NEXT:    addi sp, sp, -80
+; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -4
+; CHECK-NEXT:    .cfi_offset s0, -8
+; CHECK-NEXT:    addi s0, sp, 80
 ; CHECK-NEXT:    .cfi_def_cfa s0, 0
 ; CHECK-NEXT:    csrr a2, vlenb
 ; CHECK-NEXT:    slli a2, a2, 4
 ; CHECK-NEXT:    sub sp, sp, a2
 ; CHECK-NEXT:    andi sp, sp, -64
 ; CHECK-NEXT:    slli a0, a0, 2
 ; CHECK-NEXT:    addi a2, sp, 64
 ; CHECK-NEXT:    add a0, a2, a0
 ; CHECK-NEXT:    vs8r.v v8, (a2)
 ; CHECK-NEXT:    slli a1, a1, 3
 ; CHECK-NEXT:    add a1, a2, a1
 ; CHECK-NEXT:    vs8r.v v16, (a1)
 ; CHECK-NEXT:    lw a0, 0(a0)
-; CHECK-NEXT:    addi sp, s0, -64
-; CHECK-NEXT:    addi sp, sp, 64
+; CHECK-NEXT:    addi sp, s0, -80
+; CHECK-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 80
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define i64 @extractelt_nxv16i64_0(<vscale x 16 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv16i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e32, m8, ta, ma
 ; CHECK-NEXT:    vslidedown.vi v16, v8, 1
 ; CHECK-NEXT:    vmv.x.s a1, v16
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i64> %v, i32 0
   ret i64 %r
 }

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i64> %v, i32 0
   ret i64 %r
 }
 
 define i64 @extractelt_nxv16i64_neg1(<vscale x 16 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv16i64_neg1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    addi s0, sp, 64
+; CHECK-NEXT:    addi sp, sp, -80
+; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    addi s0, sp, 80
 ; CHECK-NEXT:    .cfi_def_cfa s0, 0
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 4
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -64
 ; CHECK-NEXT:    addi a0, sp, 64
 ; CHECK-NEXT:    vs8r.v v8, (a0)
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a2, a1, 3
 ; CHECK-NEXT:    add a2, a0, a2
 ; CHECK-NEXT:    vs8r.v v16, (a2)
 ; CHECK-NEXT:    slli a1, a1, 4
 ; CHECK-NEXT:    add a0, a1, a0
 ; CHECK-NEXT:    ld a0, -8(a0)
-; CHECK-NEXT:    addi sp, s0, -64
-; CHECK-NEXT:    addi sp, sp, 64
+; CHECK-NEXT:    addi sp, s0, -80
+; CHECK-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 80
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i64> %v, i32 -1
   ret i64 %r
 }
 
 define i64 @extractelt_nxv16i64_imm(<vscale x 16 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv16i64_imm:
 ; CHECK:       # %bb.0:

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    csrr a1, vlenb
 ; CHECK-NEXT:    slli a2, a1, 1
 ; CHECK-NEXT:    addi a2, a2, -1
 ; CHECK-NEXT:    bltu a0, a2, .LBB74_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, a2
 ; CHECK-NEXT:  .LBB74_2:
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    addi s0, sp, 64
+; CHECK-NEXT:    addi sp, sp, -80
+; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    addi s0, sp, 80
 ; CHECK-NEXT:    .cfi_def_cfa s0, 0
 ; CHECK-NEXT:    csrr a2, vlenb
 ; CHECK-NEXT:    slli a2, a2, 4
 ; CHECK-NEXT:    sub sp, sp, a2
 ; CHECK-NEXT:    andi sp, sp, -64
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    addi a2, sp, 64
 ; CHECK-NEXT:    add a0, a2, a0
 ; CHECK-NEXT:    vs8r.v v8, (a2)
 ; CHECK-NEXT:    slli a1, a1, 3
 ; CHECK-NEXT:    add a1, a2, a1
 ; CHECK-NEXT:    vs8r.v v16, (a1)
 ; CHECK-NEXT:    ld a0, 0(a0)
-; CHECK-NEXT:    addi sp, s0, -64
-; CHECK-NEXT:    addi sp, sp, 64
+; CHECK-NEXT:    addi sp, s0, -80
+; CHECK-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 80
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i64> %v, i32 %idx
   ret i64 %r
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
-
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX2
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1
+
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX2
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1
 
 define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
 ; CHECK-LABEL: insert_nxv8i32_v2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; CHECK-NEXT:    vle32.v v12, (a0)
 ; CHECK-NEXT:    vsetivli zero, 2, e32, m4, tu, ma
 ; CHECK-NEXT:    vslideup.vi v8, v12, 0
; CHECK-NEXT:    ret
   %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
   store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
   ret void
 }
 
 ; Check we don't mistakenly optimize this: we don't know whether this is
 ; inserted into the low or high split vector.
 define void @insert_v2i64_nxv16i64_hi(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
-; CHECK-LABEL: insert_v2i64_nxv16i64_hi:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    addi s0, sp, 64
-; CHECK-NEXT:    .cfi_def_cfa s0, 0
-; CHECK-NEXT:    csrr a2, vlenb
-; CHECK-NEXT:    slli a2, a2, 4
-; CHECK-NEXT:    sub sp, sp, a2
-; CHECK-NEXT:    andi sp, sp, -64
-; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT:    vle64.v v8, (a0)
-; CHECK-NEXT:    addi a0, sp, 128
-; CHECK-NEXT:    vse64.v v8, (a0)
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 3
-; CHECK-NEXT:    addi a2, sp, 64
-; CHECK-NEXT:    add a3, a2, a0
-; CHECK-NEXT:    vl8re64.v v8, (a3)
-; CHECK-NEXT:    vl8re64.v v16, (a2)
-; CHECK-NEXT:    add a0, a1, a0
-; CHECK-NEXT:    vs8r.v v8, (a0)
-; CHECK-NEXT:    vs8r.v v16, (a1)
-; CHECK-NEXT:    addi sp, s0, -64
-; CHECK-NEXT:    addi sp, sp, 64
-; CHECK-NEXT:    ret
+; RV32-LABEL: insert_v2i64_nxv16i64_hi:
+; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -80
+; RV32-NEXT:    .cfi_def_cfa_offset 80
+; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; RV32-NEXT:    .cfi_offset ra, -4
+; RV32-NEXT:    .cfi_offset s0, -8
+; RV32-NEXT:    addi s0, sp, 80
+; RV32-NEXT:    .cfi_def_cfa s0, 0
+; RV32-NEXT:    csrr a2, vlenb
+; RV32-NEXT:    slli a2, a2, 4
+; RV32-NEXT:    sub sp, sp, a2
+; RV32-NEXT:    andi sp, sp, -64
+; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT:    vle64.v v8, (a0)
+; RV32-NEXT:    addi a0, sp, 128
+; RV32-NEXT:    vse64.v v8, (a0)
+; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    slli a0, a0, 3
+; RV32-NEXT:    addi a2, sp, 64
+; RV32-NEXT:    add a3, a2, a0
+; RV32-NEXT:    vl8re64.v v8, (a3)
+; RV32-NEXT:    vl8re64.v v16, (a2)
+; RV32-NEXT:    add a0, a1, a0
+; RV32-NEXT:    vs8r.v v8, (a0)
+; RV32-NEXT:    vs8r.v v16, (a1)
+; RV32-NEXT:    addi sp, s0, -80
+; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; RV32-NEXT:    addi sp, sp, 80
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: insert_v2i64_nxv16i64_hi:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi sp, sp, -80
+; RV64-NEXT:    .cfi_def_cfa_offset 80
+; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; RV64-NEXT:    .cfi_offset ra, -8
+; RV64-NEXT:    .cfi_offset s0, -16
+; RV64-NEXT:    addi s0, sp, 80
+; RV64-NEXT:    .cfi_def_cfa s0, 0
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    slli a2, a2, 4
+; RV64-NEXT:    sub sp, sp, a2
+; RV64-NEXT:    andi sp, sp, -64
+; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT:    vle64.v v8, (a0)
+; RV64-NEXT:    addi a0, sp, 128
+; RV64-NEXT:    vse64.v v8, (a0)
+; RV64-NEXT:    csrr a0, vlenb
+; RV64-NEXT:    slli a0, a0, 3
+; RV64-NEXT:    addi a2, sp, 64
+; RV64-NEXT:    add a3, a2, a0
+; RV64-NEXT:    vl8re64.v v8, (a3)
+; RV64-NEXT:    vl8re64.v v16, (a2)
+; RV64-NEXT:    add a0, a1, a0
+; RV64-NEXT:    vs8r.v v8, (a0)
+; RV64-NEXT:    vs8r.v v16, (a1)
+; RV64-NEXT:    addi sp, s0, -80
+; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; RV64-NEXT:    addi sp, sp, 80
+; RV64-NEXT:    ret
   %sv = load <2 x i64>, <2 x i64>* %psv
   %v = call <vscale x 16 x i64> @llvm.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 8)
   store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
   ret void
 }
 
 declare <8 x i1> @llvm.vector.insert.v4i1.v8i1(<8 x i1>, <4 x i1>, i64)
 declare <32 x i1> @llvm.vector.insert.v8i1.v32i1(<32 x i1>, <8 x i1>, i64)

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

 ; CHECK-NEXT:    vmv2r.v v10, v28
 ; CHECK-NEXT:    vmv2r.v v12, v30
 ; CHECK-NEXT:    ret
   %res = call <vscale x 6 x i64> @llvm.experimental.vector.reverse.nxv6i64(<vscale x 6 x i64> %a)
   ret <vscale x 6 x i64> %res
 }
 
 define <vscale x 12 x i64> @reverse_nxv12i64(<vscale x 12 x i64> %a) {
-; CHECK-LABEL: reverse_nxv12i64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -64
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    addi s0, sp, 64
-; CHECK-NEXT:    .cfi_def_cfa s0, 0
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    slli a0, a0, 4
-; CHECK-NEXT:    sub sp, sp, a0
-; CHECK-NEXT:    andi sp, sp, -64
-; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    addi a1, a0, -1
-; CHECK-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
-; CHECK-NEXT:    vid.v v24
-; CHECK-NEXT:    vrsub.vx v24, v24, a1
-; CHECK-NEXT:    vrgather.vv v0, v16, v24
-; CHECK-NEXT:    vmv4r.v v16, v4
-; CHECK-NEXT:    vrgather.vv v0, v8, v24
-; CHECK-NEXT:    vmv4r.v v20, v0
-; CHECK-NEXT:    slli a0, a0, 3
-; CHECK-NEXT:    addi a1, sp, 64
-; CHECK-NEXT:    add a0, a1, a0
-; CHECK-NEXT:    vs4r.v v4, (a0)
-; CHECK-NEXT:    vs8r.v v16, (a1)
-; CHECK-NEXT:    vl8re64.v v16, (a0)
-; CHECK-NEXT:    vl8re64.v v8, (a1)
-; CHECK-NEXT:    addi sp, s0, -64
-; CHECK-NEXT:    addi sp, sp, 64
-; CHECK-NEXT:    ret
+; RV32-BITS-UNKNOWN-LABEL: reverse_nxv12i64:
+; RV32-BITS-UNKNOWN:       # %bb.0:
+; RV32-BITS-UNKNOWN-NEXT:    addi sp, sp, -80
+; RV32-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 80
+; RV32-BITS-UNKNOWN-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; RV32-BITS-UNKNOWN-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; RV32-BITS-UNKNOWN-NEXT:    .cfi_offset ra, -4
+; RV32-BITS-UNKNOWN-NEXT:    .cfi_offset s0, -8
+; RV32-BITS-UNKNOWN-NEXT:    addi s0, sp, 80
+; RV32-BITS-UNKNOWN-NEXT:    .cfi_def_cfa s0, 0
+; RV32-BITS-UNKNOWN-NEXT:    csrr a0, vlenb
+; RV32-BITS-UNKNOWN-NEXT:    slli a0, a0, 4
+; RV32-BITS-UNKNOWN-NEXT:    sub sp, sp, a0
+; RV32-BITS-UNKNOWN-NEXT:    andi sp, sp, -64
+; RV32-BITS-UNKNOWN-NEXT:    csrr a0, vlenb
+; RV32-BITS-UNKNOWN-NEXT:    addi a1, a0, -1
+; RV32-BITS-UNKNOWN-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
+; RV32-BITS-UNKNOWN-NEXT:    vid.v v24
+; RV32-BITS-UNKNOWN-NEXT:    vrsub.vx v24, v24, a1
+; RV32-BITS-UNKNOWN-NEXT:    vrgather.vv v0, v16, v24
+; RV32-BITS-UNKNOWN-NEXT:    vmv4r.v v16, v4
+; RV32-BITS-UNKNOWN-NEXT:    vrgather.vv v0, v8, v24
+; RV32-BITS-UNKNOWN-NEXT:    vmv4r.v v20, v0
+; RV32-BITS-UNKNOWN-NEXT:    slli a0, a0, 3
+; RV32-BITS-UNKNOWN-NEXT:    addi a1, sp, 64
+; RV32-BITS-UNKNOWN-NEXT:    add a0, a1, a0
+; RV32-BITS-UNKNOWN-NEXT:    vs4r.v v4, (a0)
+; RV32-BITS-UNKNOWN-NEXT:    vs8r.v v16, (a1)
+; RV32-BITS-UNKNOWN-NEXT:    vl8re64.v v16, (a0)
+; RV32-BITS-UNKNOWN-NEXT:    vl8re64.v v8, (a1)
+; RV32-BITS-UNKNOWN-NEXT:    addi sp, s0, -80
+; RV32-BITS-UNKNOWN-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; RV32-BITS-UNKNOWN-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; RV32-BITS-UNKNOWN-NEXT:    addi sp, sp, 80
+; RV32-BITS-UNKNOWN-NEXT:    ret
+;
+; RV32-BITS-256-LABEL: reverse_nxv12i64:
+; RV32-BITS-256:       # %bb.0:
+; RV32-BITS-256-NEXT:    addi sp, sp, -80
+; RV32-BITS-256-NEXT:    .cfi_def_cfa_offset 80
+; RV32-BITS-256-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; RV32-BITS-256-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; RV32-BITS-256-NEXT:    .cfi_offset ra, -4
+; RV32-BITS-256-NEXT:    .cfi_offset s0, -8
+; RV32-BITS-256-NEXT:    addi s0, sp, 80
+; RV32-BITS-256-NEXT:    .cfi_def_cfa s0, 0
+; RV32-BITS-256-NEXT:    csrr a0, vlenb
+; RV32-BITS-256-NEXT:    slli a0, a0, 4
+; RV32-BITS-256-NEXT:    sub sp, sp, a0
+; RV32-BITS-256-NEXT:    andi sp, sp, -64
+; RV32-BITS-256-NEXT:    csrr a0, vlenb
+; RV32-BITS-256-NEXT:    addi a1, a0, -1
+; RV32-BITS-256-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
+; RV32-BITS-256-NEXT:    vid.v v24
+; RV32-BITS-256-NEXT:    vrsub.vx v24, v24, a1
+; RV32-BITS-256-NEXT:    vrgather.vv v0, v16, v24
+; RV32-BITS-256-NEXT:    vmv4r.v v16, v4
+; RV32-BITS-256-NEXT:    vrgather.vv v0, v8, v24
+; RV32-BITS-256-NEXT:    vmv4r.v v20, v0
+; RV32-BITS-256-NEXT:    slli a0, a0, 3
+; RV32-BITS-256-NEXT:    addi a1, sp, 64
+; RV32-BITS-256-NEXT:    add a0, a1, a0
+; RV32-BITS-256-NEXT:    vs4r.v v4, (a0)
+; RV32-BITS-256-NEXT:    vs8r.v v16, (a1)
+; RV32-BITS-256-NEXT:    vl8re64.v v16, (a0)
+; RV32-BITS-256-NEXT:    vl8re64.v v8, (a1)
+; RV32-BITS-256-NEXT:    addi sp, s0, -80
+; RV32-BITS-256-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; RV32-BITS-256-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; RV32-BITS-256-NEXT:    addi sp, sp, 80
+; RV32-BITS-256-NEXT:    ret
+;
+; RV32-BITS-512-LABEL: reverse_nxv12i64:
+; RV32-BITS-512:       # %bb.0:
+; RV32-BITS-512-NEXT:    addi sp, sp, -80
+; RV32-BITS-512-NEXT:    .cfi_def_cfa_offset 80
+; RV32-BITS-512-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
+; RV32-BITS-512-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
+; RV32-BITS-512-NEXT:    .cfi_offset ra, -4
+; RV32-BITS-512-NEXT:    .cfi_offset s0, -8
+; RV32-BITS-512-NEXT:    addi s0, sp, 80
+; RV32-BITS-512-NEXT:    .cfi_def_cfa s0, 0
+; RV32-BITS-512-NEXT:    csrr a0, vlenb
+; RV32-BITS-512-NEXT:    slli a0, a0, 4
+; RV32-BITS-512-NEXT:    sub sp, sp, a0
+; RV32-BITS-512-NEXT:    andi sp, sp, -64
+; RV32-BITS-512-NEXT:    csrr a0, vlenb
+; RV32-BITS-512-NEXT:    addi a1, a0, -1
+; RV32-BITS-512-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
+; RV32-BITS-512-NEXT:    vid.v v24
+; RV32-BITS-512-NEXT:    vrsub.vx v24, v24, a1
+; RV32-BITS-512-NEXT:    vrgather.vv v0, v16, v24
+; RV32-BITS-512-NEXT:    vmv4r.v v16, v4
+; RV32-BITS-512-NEXT:    vrgather.vv v0, v8, v24
+; RV32-BITS-512-NEXT:    vmv4r.v v20, v0
+; RV32-BITS-512-NEXT:    slli a0, a0, 3
+; RV32-BITS-512-NEXT:    addi a1, sp, 64
+; RV32-BITS-512-NEXT:    add a0, a1, a0
+; RV32-BITS-512-NEXT:    vs4r.v v4, (a0)
+; RV32-BITS-512-NEXT:    vs8r.v v16, (a1)
+; RV32-BITS-512-NEXT:    vl8re64.v v16, (a0)
+; RV32-BITS-512-NEXT:    vl8re64.v v8, (a1)
+; RV32-BITS-512-NEXT:    addi sp, s0, -80
+; RV32-BITS-512-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
+; RV32-BITS-512-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
+; RV32-BITS-512-NEXT:    addi sp, sp, 80
+; RV32-BITS-512-NEXT:    ret
+;
+; RV64-BITS-UNKNOWN-LABEL: reverse_nxv12i64:
+; RV64-BITS-UNKNOWN:       # %bb.0:
+; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, -80
+; RV64-BITS-UNKNOWN-NEXT:    .cfi_def_cfa_offset 80
+; RV64-BITS-UNKNOWN-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; RV64-BITS-UNKNOWN-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; RV64-BITS-UNKNOWN-NEXT:    .cfi_offset ra, -8
+; RV64-BITS-UNKNOWN-NEXT:    .cfi_offset s0, -16
+; RV64-BITS-UNKNOWN-NEXT:    addi s0, sp, 80
+; RV64-BITS-UNKNOWN-NEXT:    .cfi_def_cfa s0, 0
+; RV64-BITS-UNKNOWN-NEXT:    csrr a0, vlenb
+; RV64-BITS-UNKNOWN-NEXT:    slli a0, a0, 4
+; RV64-BITS-UNKNOWN-NEXT:    sub sp, sp, a0
+; RV64-BITS-UNKNOWN-NEXT:    andi sp, sp, -64
+; RV64-BITS-UNKNOWN-NEXT:    csrr a0, vlenb
+; RV64-BITS-UNKNOWN-NEXT:    addi a1, a0, -1
+; RV64-BITS-UNKNOWN-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
+; RV64-BITS-UNKNOWN-NEXT:    vid.v v24
+; RV64-BITS-UNKNOWN-NEXT:    vrsub.vx v24, v24, a1
+; RV64-BITS-UNKNOWN-NEXT:    vrgather.vv v0, v16, v24
+; RV64-BITS-UNKNOWN-NEXT:    vmv4r.v v16, v4
+; RV64-BITS-UNKNOWN-NEXT:    vrgather.vv v0, v8, v24
+; RV64-BITS-UNKNOWN-NEXT:    vmv4r.v v20, v0
+; RV64-BITS-UNKNOWN-NEXT:    slli a0, a0, 3
+; RV64-BITS-UNKNOWN-NEXT:    addi a1, sp, 64
+; RV64-BITS-UNKNOWN-NEXT:    add a0, a1, a0
+; RV64-BITS-UNKNOWN-NEXT:    vs4r.v v4, (a0)
+; RV64-BITS-UNKNOWN-NEXT:    vs8r.v v16, (a1)
+; RV64-BITS-UNKNOWN-NEXT:    vl8re64.v v16, (a0)
+; RV64-BITS-UNKNOWN-NEXT:    vl8re64.v v8, (a1)
+; RV64-BITS-UNKNOWN-NEXT:    addi sp, s0, -80
+; RV64-BITS-UNKNOWN-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; RV64-BITS-UNKNOWN-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; RV64-BITS-UNKNOWN-NEXT:    addi sp, sp, 80
+; RV64-BITS-UNKNOWN-NEXT:    ret
+;
+; RV64-BITS-256-LABEL: reverse_nxv12i64:
+; RV64-BITS-256:       # %bb.0:
+; RV64-BITS-256-NEXT:    addi sp, sp, -80
+; RV64-BITS-256-NEXT:    .cfi_def_cfa_offset 80
+; RV64-BITS-256-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; RV64-BITS-256-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; RV64-BITS-256-NEXT:    .cfi_offset ra, -8
+; RV64-BITS-256-NEXT:    .cfi_offset s0, -16
+; RV64-BITS-256-NEXT:    addi s0, sp, 80
+; RV64-BITS-256-NEXT:    .cfi_def_cfa s0, 0
+; RV64-BITS-256-NEXT:    csrr a0, vlenb
+; RV64-BITS-256-NEXT:    slli a0, a0, 4
+; RV64-BITS-256-NEXT:    sub sp, sp, a0
+; RV64-BITS-256-NEXT:    andi sp, sp, -64
+; RV64-BITS-256-NEXT:    csrr a0, vlenb
+; RV64-BITS-256-NEXT:    addi a1, a0, -1
+; RV64-BITS-256-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
+; RV64-BITS-256-NEXT:    vid.v v24
+; RV64-BITS-256-NEXT:    vrsub.vx v24, v24, a1
+; RV64-BITS-256-NEXT:    vrgather.vv v0, v16, v24
+; RV64-BITS-256-NEXT:    vmv4r.v v16, v4
+; RV64-BITS-256-NEXT:    vrgather.vv v0, v8, v24
+; RV64-BITS-256-NEXT:    vmv4r.v v20, v0
+; RV64-BITS-256-NEXT:    slli a0, a0, 3
+; RV64-BITS-256-NEXT:    addi a1, sp, 64
+; RV64-BITS-256-NEXT:    add a0, a1, a0
+; RV64-BITS-256-NEXT:    vs4r.v v4, (a0)
+; RV64-BITS-256-NEXT:    vs8r.v v16, (a1)
+; RV64-BITS-256-NEXT:    vl8re64.v v16, (a0)
+; RV64-BITS-256-NEXT:    vl8re64.v v8, (a1)
+; RV64-BITS-256-NEXT:    addi sp, s0, -80
+; RV64-BITS-256-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; RV64-BITS-256-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; RV64-BITS-256-NEXT:    addi sp, sp, 80
+; RV64-BITS-256-NEXT:    ret
+;
+; RV64-BITS-512-LABEL: reverse_nxv12i64:
+; RV64-BITS-512:       # %bb.0:
+; RV64-BITS-512-NEXT:    addi sp, sp, -80
+; RV64-BITS-512-NEXT:    .cfi_def_cfa_offset 80
+; RV64-BITS-512-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; RV64-BITS-512-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; RV64-BITS-512-NEXT:    .cfi_offset ra, -8
+; RV64-BITS-512-NEXT:    .cfi_offset s0, -16
+; RV64-BITS-512-NEXT:    addi s0, sp, 80
+; RV64-BITS-512-NEXT:    .cfi_def_cfa s0, 0
+; RV64-BITS-512-NEXT:    csrr a0, vlenb
+; RV64-BITS-512-NEXT:    slli a0, a0, 4
+; RV64-BITS-512-NEXT:    sub sp, sp, a0
+; RV64-BITS-512-NEXT:    andi sp, sp, -64
+; RV64-BITS-512-NEXT:    csrr a0, vlenb
+; RV64-BITS-512-NEXT:    addi a1, a0, -1
+; RV64-BITS-512-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
+; RV64-BITS-512-NEXT:    vid.v v24
+; RV64-BITS-512-NEXT:    vrsub.vx v24, v24, a1
+; RV64-BITS-512-NEXT:    vrgather.vv v0, v16, v24
+; RV64-BITS-512-NEXT:    vmv4r.v v16, v4
+; RV64-BITS-512-NEXT:    vrgather.vv v0, v8, v24
+; RV64-BITS-512-NEXT:    vmv4r.v v20, v0
+; RV64-BITS-512-NEXT:    slli a0, a0, 3
+; RV64-BITS-512-NEXT:    addi a1, sp, 64
+; RV64-BITS-512-NEXT:    add a0, a1, a0
+; RV64-BITS-512-NEXT:    vs4r.v v4, (a0)
+; RV64-BITS-512-NEXT:    vs8r.v v16, (a1)
+; RV64-BITS-512-NEXT:    vl8re64.v v16, (a0)
+; RV64-BITS-512-NEXT:    vl8re64.v v8, (a1)
+; RV64-BITS-512-NEXT:    addi sp, s0, -80
+; RV64-BITS-512-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; RV64-BITS-512-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; RV64-BITS-512-NEXT:    addi sp, sp, 80
+; RV64-BITS-512-NEXT:    ret
   %res = call <vscale x 12 x i64> @llvm.experimental.vector.reverse.nxv12i64(<vscale x 12 x i64> %a)
   ret <vscale x 12 x i64> %res
 }
 
 declare <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1>)
 declare <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1>)
 declare <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1>)
 declare <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1>)

llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll

; CHECK-NEXT:    ret
   %s1 = add <vscale x 16 x i32> %x, %z
   %s = add <vscale x 16 x i32> %s0, %s1
   ret <vscale x 16 x i32> %s
 }
 
 define <vscale x 16 x i32> @foo(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <vscale x 16 x i32> %x) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi sp, sp, -80
-; CHECK-NEXT:    .cfi_def_cfa_offset 80
-; CHECK-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    addi sp, sp, -96
+; CHECK-NEXT:    .cfi_def_cfa_offset 96
+; CHECK-NEXT:    sd ra, 88(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 80(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 72(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset ra, -8
-; CHECK-NEXT:    addi s0, sp, 80
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    addi s0, sp, 96
 ; CHECK-NEXT:    .cfi_def_cfa s0, 0
 ; CHECK-NEXT:    csrr t0, vlenb
 ; CHECK-NEXT:    slli t0, t0, 4
 ; CHECK-NEXT:    sub sp, sp, t0
 ; CHECK-NEXT:    andi sp, sp, -64
 ; CHECK-NEXT:    mv s1, sp
+; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    addi t0, s1, 64
 ; CHECK-NEXT:    vs8r.v v8, (t0)
 ; CHECK-NEXT:    csrr t1, vlenb
 ; CHECK-NEXT:    slli t1, t1, 3
 ; CHECK-NEXT:    add t1, s1, t1
 ; CHECK-NEXT:    addi t1, t1, 64
 ; CHECK-NEXT:    vs8r.v v8, (t1)
 ; CHECK-NEXT:    sd t0, 8(sp)
 ; CHECK-NEXT:    sd t1, 0(sp)
 ; CHECK-NEXT:    vmv8r.v v16, v8
 ; CHECK-NEXT:    call bar@plt
-; CHECK-NEXT:    addi sp, s0, -80
-; CHECK-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
-; CHECK-NEXT:    addi sp, sp, 80
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    addi sp, s0, -96
+; CHECK-NEXT:    ld ra, 88(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 80(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 96
 ; CHECK-NEXT:    ret
   %ret = call <vscale x 16 x i32> @bar(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, <vscale x 16 x i32> %x, <vscale x 16 x i32> %x, <vscale x 16 x i32> %x, <vscale x 16 x i32> %x)
   ret <vscale x 16 x i32> %ret
 }