This is an archive of the discontinued LLVM Phabricator instance.

Differential D135600

[RISCV] Use branchless form for selects with 0 in either arm
ClosedPublic

Authored by reames on Oct 10 2022, 9:18 AM.

Details

Reviewers
craig.topper
asb
frasercrmck
Commits
rG1c41d0cb62c2: [RISCV] Use branchless form for selects with 0 in either arm
Summary

Continuing the theme of adding branchless lowerings for simple selects, this time handle the 0 arm case. This is very common for various umin idioms, etc..

Diff Detail

Event Timeline

reames created this revision.Oct 10 2022, 9:18 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 10 2022, 9:18 AM
Herald added subscribers: sunshaoce, VincentWu, armkevincheng and 33 others. · View Herald Transcript
reames requested review of this revision.Oct 10 2022, 9:18 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 10 2022, 9:18 AM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper added inline comments.Oct 10 2022, 9:55 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
9505

Too much copy/paste. :) This should be isNullConstant

Harbormaster completed remote builds in B191302: Diff 466532.Oct 10 2022, 10:20 AM
reames added inline comments.Oct 10 2022, 11:17 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
9505

Eek, how did I miss that? I swear I looked at the test diffs too!

reames updated this revision to Diff 466572.Oct 10 2022, 11:43 AM

Address bug caught by @craig.topper. Due to copy paste mistake, second case was dead code. With fix, impact is even broader, including making many floating point conversion idioms branchless.

jrtc27 added a comment.Oct 10 2022, 11:50 AM

Is the branchless form better though? Branch+move can be fused but these forms can't and have more instructions to execute.

craig.topper added a comment.Oct 10 2022, 12:01 PM
In D135600#3847548, @jrtc27 wrote:

Is the branchless form better though? Branch+move can be fused but these forms can't and have more instructions to execute.

We need an mtune flag for CPUs that can fuse these like sifive-7-series. But we also need to implement a fusion guarantee too so that code motion doesn't sinks things into the basic block and break fusion. I assume rocket doesn't fuse these?

Harbormaster completed remote builds in B191338: Diff 466572.Oct 10 2022, 12:31 PM
liaolucy added a subscriber: liaolucy.Oct 10 2022, 5:45 PM
craig.topper added inline comments.Oct 12 2022, 11:06 AM
llvm/test/CodeGen/RISCV/double-convert.ll
97

This is interesting. The seqz isn't necessary. I'll take a look at this.

craig.topper accepted this revision.Oct 12 2022, 12:15 PM

LGTM. I think this is a good starting point. I have a followup I'm going to try to fix the issue I noticed, but that shouldn't block this.

This revision is now accepted and ready to land.Oct 12 2022, 12:15 PM
This revision was landed with ongoing or failed builds.Oct 12 2022, 1:52 PM
Closed by commit rG1c41d0cb62c2: [RISCV] Use branchless form for selects with 0 in either arm (authored by reames). · Explain Why
This revision was automatically updated to reflect the committed changes.
reames added a commit: rG1c41d0cb62c2: [RISCV] Use branchless form for selects with 0 in either arm.

Large Diff

This large diff affects 101 files. Files without inline comments have been collapsed. Expand All Files

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
15 lines
test/
CodeGen/
RISCV/
39 lines
24 lines
24 lines
598 lines
285 lines
443 lines
285 lines
67 lines
3070 lines
2981 lines
802 lines
285 lines
744 lines
41 lines
70 lines
42 lines
rvv/
97 lines
16 lines
16 lines
318 lines
145 lines
145 lines
300 lines
39 lines
39 lines
46 lines
23 lines
32 lines
145 lines
145 lines
145 lines
103 lines
190 lines
32 lines
39 lines
194 lines
64 lines
39 lines
126 lines
79 lines
39 lines
156 lines
79 lines
79 lines
156 lines
39 lines
39 lines
80 lines
80 lines
80 lines
80 lines
596 lines
50 lines
177 lines
236 lines
22 lines
171 lines
32 lines
97 lines
97 lines
97 lines
97 lines
264 lines
229 lines
180 lines
244 lines
112 lines
39 lines
127 lines
127 lines
39 lines
20 lines
59 lines
59 lines
165 lines
39 lines
112 lines
112 lines
112 lines
112 lines
312 lines
76 lines
206 lines
252 lines
90 lines
54 lines
66 lines
29 lines
106 lines
41 lines
59 lines
190 lines
59 lines
41 lines
76 lines
26 lines
569 lines
111 lines
148 lines
100 lines

Diff 467252

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,488 Lines • ▼ Show 20 Lines case RISCVISD::SELECT_CC: {
// (select c, y, -1) -> -!c | y // (select c, y, -1) -> -!c | y
if (isAllOnesConstant(FalseV)) { if (isAllOnesConstant(FalseV)) {
SDValue C = DAG.getSetCC(DL, VT, LHS, RHS, SDValue C = DAG.getSetCC(DL, VT, LHS, RHS,
ISD::getSetCCInverse(CCVal, VT)); ISD::getSetCCInverse(CCVal, VT));
SDValue Neg = DAG.getNegative(C, DL, VT); SDValue Neg = DAG.getNegative(C, DL, VT);
return DAG.getNode(ISD::OR, DL, VT, Neg, TrueV); return DAG.getNode(ISD::OR, DL, VT, Neg, TrueV);
} }
// (select c, 0, y) -> -!c & y
if (isNullConstant(TrueV)) {
SDValue C = DAG.getSetCC(DL, VT, LHS, RHS,
ISD::getSetCCInverse(CCVal, VT));
SDValue Neg = DAG.getNegative(C, DL, VT);
return DAG.getNode(ISD::AND, DL, VT, Neg, FalseV);
}
// (select c, y, 0) -> -c & y
if (isNullConstant(FalseV)) {
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Too much copy/paste. :) This should be isNullConstant

craig.topper: Too much copy/paste. :) This should be `isNullConstant`
reamesAuthorUnsubmitted
Done
ReplyInline Actions

Eek, how did I miss that? I swear I looked at the test diffs too!

reames: Eek, how did I miss that? I swear I looked at the test diffs too!
SDValue C = DAG.getSetCC(DL, VT, LHS, RHS, CCVal);
SDValue Neg = DAG.getNegative(C, DL, VT);
return DAG.getNode(ISD::AND, DL, VT, Neg, TrueV);
}
return SDValue(); return SDValue();
} }
case RISCVISD::BR_CC: { case RISCVISD::BR_CC: {
SDValue LHS = N->getOperand(1); SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2); SDValue RHS = N->getOperand(2);
SDValue CC = N->getOperand(3); SDValue CC = N->getOperand(3);
SDLoc DL(N); SDLoc DL(N);
▲ Show 20 Lines • Show All 3,506 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/alu64.ll

llvm/test/CodeGen/RISCV/bittest.ll

llvm/test/CodeGen/RISCV/compress-opt-select.ll

llvm/test/CodeGen/RISCV/double-convert.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptosi double %a to i32 %1 = fptosi double %a to i32
ret i32 %1 ret i32 %1
} }
define i32 @fcvt_w_d_sat(double %a) nounwind { define i32 @fcvt_w_d_sat(double %a) nounwind {
; CHECKIFD-LABEL: fcvt_w_d_sat: ; CHECKIFD-LABEL: fcvt_w_d_sat:
; CHECKIFD: # %bb.0: # %start ; CHECKIFD: # %bb.0: # %start
; CHECKIFD-NEXT: feq.d a0, fa0, fa0
; CHECKIFD-NEXT: beqz a0, .LBB3_2
; CHECKIFD-NEXT: # %bb.1:
; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
; CHECKIFD-NEXT: .LBB3_2: # %start ; CHECKIFD-NEXT: feq.d a1, fa0, fa0
; CHECKIFD-NEXT: seqz a1, a1
craig.topperUnsubmitted
Not Done
ReplyInline Actions

This is interesting. The seqz isn't necessary. I'll take a look at this.

craig.topper: This is interesting. The seqz isn't necessary. I'll take a look at this.
; CHECKIFD-NEXT: addi a1, a1, -1
; CHECKIFD-NEXT: and a0, a1, a0
; CHECKIFD-NEXT: ret ; CHECKIFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_d_sat: ; RV32I-LABEL: fcvt_w_d_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 269824 ; RV32I-NEXT: lui a0, 269824
; RV32I-NEXT: addi a3, a0, -1 ; RV32I-NEXT: addi a3, a0, -1
; RV32I-NEXT: lui a2, 1047552 ; RV32I-NEXT: lui a2, 1047552
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 794112 ; RV32I-NEXT: lui a3, 794112
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfsi@plt ; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: lui s5, 524288 ; RV32I-NEXT: lui s4, 524288
; RV32I-NEXT: bltz s4, .LBB3_2 ; RV32I-NEXT: bltz s3, .LBB3_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: .LBB3_2: # %start ; RV32I-NEXT: .LBB3_2: # %start
; RV32I-NEXT: bge s2, s3, .LBB3_4 ; RV32I-NEXT: blez s2, .LBB3_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: addi s5, a1, -1 ; RV32I-NEXT: addi s4, a1, -1
; RV32I-NEXT: .LBB3_4: # %start ; RV32I-NEXT: .LBB3_4: # %start
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bnez a0, .LBB3_6 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: mv s2, s5 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: .LBB3_6: # %start
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_w_d_sat: ; RV64I-LABEL: fcvt_w_d_sat:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
Show All 22 Lines
; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: blez a0, .LBB3_4 ; RV64I-NEXT: blez a0, .LBB3_4
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: addiw s2, s3, -1 ; RV64I-NEXT: addiw s2, s3, -1
; RV64I-NEXT: .LBB3_4: # %start ; RV64I-NEXT: .LBB3_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt ; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: li a0, 0 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: bnez a1, .LBB3_6 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: .LBB3_6: # %start
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
%b = icmp eq i32 %a, 0 %b = icmp eq i32 %a, 0
%c = select i1 %b, i32 1, i32 %a %c = select i1 %b, i32 1, i32 %a
ret i32 %c ret i32 %c
} }
define i32 @fcvt_wu_d_sat(double %a) nounwind { define i32 @fcvt_wu_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_wu_d_sat: ; RV32IFD-LABEL: fcvt_wu_d_sat:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0
; RV32IFD-NEXT: beqz a0, .LBB6_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV32IFD-NEXT: .LBB6_2: # %start ; RV32IFD-NEXT: feq.d a1, fa0, fa0
; RV32IFD-NEXT: seqz a1, a1
; RV32IFD-NEXT: addi a1, a1, -1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_wu_d_sat: ; RV64IFD-LABEL: fcvt_wu_d_sat:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: beqz a0, .LBB6_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz ; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: slli a0, a0, 32 ; RV64IFD-NEXT: slli a0, a0, 32
; RV64IFD-NEXT: srli a0, a0, 32 ; RV64IFD-NEXT: srli a0, a0, 32
; RV64IFD-NEXT: .LBB6_2: # %start
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_wu_d_sat: ; RV32I-LABEL: fcvt_wu_d_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
Show All 32 Lines
; ;
; RV64I-LABEL: fcvt_wu_d_sat: ; RV64I-LABEL: fcvt_wu_d_sat:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __fixunsdfdi@plt ; RV64I-NEXT: call __fixunsdfdi@plt
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: bltz s2, .LBB6_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: .LBB6_2: # %start
; RV64I-NEXT: li a0, 1055 ; RV64I-NEXT: li a0, 1055
; RV64I-NEXT: slli a0, a0, 31 ; RV64I-NEXT: slli a0, a0, 31
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: slli a1, a0, 21 ; RV64I-NEXT: slli a1, a0, 21
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: blez a0, .LBB6_4 ; RV64I-NEXT: bgtz a0, .LBB6_2
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: slti a0, s0, 0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: j .LBB6_3
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: li a0, -1 ; RV64I-NEXT: li a0, -1
; RV64I-NEXT: srli s1, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: .LBB6_4: # %start ; RV64I-NEXT: .LBB6_3: # %start
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
%0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a) %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
; RV32IFD-NEXT: lui a2, %hi(.LCPI12_1) ; RV32IFD-NEXT: lui a2, %hi(.LCPI12_1)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI12_1)(a2) ; RV32IFD-NEXT: fld ft0, %lo(.LCPI12_1)(a2)
; RV32IFD-NEXT: flt.d a2, ft0, fs0 ; RV32IFD-NEXT: flt.d a2, ft0, fs0
; RV32IFD-NEXT: beqz a2, .LBB12_4 ; RV32IFD-NEXT: beqz a2, .LBB12_4
; RV32IFD-NEXT: # %bb.3: ; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: addi a1, a3, -1 ; RV32IFD-NEXT: addi a1, a3, -1
; RV32IFD-NEXT: .LBB12_4: # %start ; RV32IFD-NEXT: .LBB12_4: # %start
; RV32IFD-NEXT: feq.d a3, fs0, fs0 ; RV32IFD-NEXT: feq.d a3, fs0, fs0
; RV32IFD-NEXT: bnez a3, .LBB12_6 ; RV32IFD-NEXT: seqz a3, a3
; RV32IFD-NEXT: # %bb.5: # %start ; RV32IFD-NEXT: addi a3, a3, -1
; RV32IFD-NEXT: li a1, 0 ; RV32IFD-NEXT: and a1, a3, a1
; RV32IFD-NEXT: li a0, 0 ; RV32IFD-NEXT: seqz a4, s0
; RV32IFD-NEXT: j .LBB12_7 ; RV32IFD-NEXT: addi a4, a4, -1
; RV32IFD-NEXT: .LBB12_6: ; RV32IFD-NEXT: and a0, a4, a0
; RV32IFD-NEXT: neg a3, s0
; RV32IFD-NEXT: and a0, a3, a0
; RV32IFD-NEXT: seqz a2, a2 ; RV32IFD-NEXT: seqz a2, a2
; RV32IFD-NEXT: addi a2, a2, -1 ; RV32IFD-NEXT: addi a2, a2, -1
; RV32IFD-NEXT: or a0, a0, a2 ; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: .LBB12_7: # %start ; RV32IFD-NEXT: and a0, a3, a0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_l_d_sat: ; RV64IFD-LABEL: fcvt_l_d_sat:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: beqz a0, .LBB12_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz ; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
; RV64IFD-NEXT: .LBB12_2: # %start ; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_l_d_sat: ; RV32I-LABEL: fcvt_l_d_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a3, 802304 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lui a0, 278016 ; RV32I-NEXT: lui a0, 278016
; RV32I-NEXT: addi s4, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: mv a3, s4
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: neg s6, a0 ; RV32I-NEXT: lui a3, 802304
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfdi@plt ; RV32I-NEXT: call __fixdfdi@plt
; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: bltz s3, .LBB12_2 ; RV32I-NEXT: mv s4, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: bgtz s7, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: or s6, s6, a0 ; RV32I-NEXT: slti a0, s5, 0
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: and s2, s2, a0
; RV32I-NEXT: .LBB12_2: # %start ; RV32I-NEXT: .LBB12_2: # %start
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: mv s3, s0
; RV32I-NEXT: bnez a0, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s3, s6
; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a3, s4 ; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: lui a3, 802304 ; RV32I-NEXT: lui a3, 802304
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: lui s6, 524288 ; RV32I-NEXT: lui s5, 524288
; RV32I-NEXT: bltz a0, .LBB12_6 ; RV32I-NEXT: bltz a0, .LBB12_4
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s6, s5 ; RV32I-NEXT: mv s5, s4
; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: blez s3, .LBB12_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: addi s5, a1, -1
; RV32I-NEXT: .LBB12_6: # %start ; RV32I-NEXT: .LBB12_6: # %start
; RV32I-NEXT: bge s0, s4, .LBB12_8 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: # %bb.7:
; RV32I-NEXT: addi s6, a1, -1
; RV32I-NEXT: .LBB12_8: # %start
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bnez a0, .LBB12_10
; RV32I-NEXT: # %bb.9: # %start
; RV32I-NEXT: mv s0, s6
; RV32I-NEXT: .LBB12_10: # %start
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_l_d_sat: ; RV64I-LABEL: fcvt_l_d_sat:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
Show All 22 Lines
; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: blez a0, .LBB12_5 ; RV64I-NEXT: blez a0, .LBB12_5
; RV64I-NEXT: # %bb.4: ; RV64I-NEXT: # %bb.4:
; RV64I-NEXT: srli s1, s3, 1 ; RV64I-NEXT: srli s1, s3, 1
; RV64I-NEXT: .LBB12_5: # %start ; RV64I-NEXT: .LBB12_5: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt ; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: li a0, 0 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: bnez a1, .LBB12_7 ; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: # %bb.6: # %start
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: .LBB12_7: # %start
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w ft0, zero
; RV32IFD-NEXT: fle.d a0, ft0, fa0 ; RV32IFD-NEXT: fle.d a0, ft0, fa0
; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: seqz a0, a0
; RV32IFD-NEXT: addi s0, a0, -1
; RV32IFD-NEXT: call __fixunsdfdi@plt ; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0) ; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI14_0)(a2) ; RV32IFD-NEXT: fld ft0, %lo(.LCPI14_0)(a2)
; RV32IFD-NEXT: and a0, s0, a0 ; RV32IFD-NEXT: and a0, s0, a0
; RV32IFD-NEXT: flt.d a2, ft0, fs0 ; RV32IFD-NEXT: flt.d a2, ft0, fs0
; RV32IFD-NEXT: seqz a2, a2 ; RV32IFD-NEXT: seqz a2, a2
; RV32IFD-NEXT: addi a2, a2, -1 ; RV32IFD-NEXT: addi a2, a2, -1
; RV32IFD-NEXT: or a0, a0, a2 ; RV32IFD-NEXT: or a0, a2, a0
; RV32IFD-NEXT: and a1, s0, a1 ; RV32IFD-NEXT: and a1, s0, a1
; RV32IFD-NEXT: or a1, a1, a2 ; RV32IFD-NEXT: or a1, a2, a1
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_lu_d_sat: ; RV64IFD-LABEL: fcvt_lu_d_sat:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: beqz a0, .LBB14_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz ; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
; RV64IFD-NEXT: .LBB14_2: # %start ; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_lu_d_sat: ; RV32I-LABEL: fcvt_lu_d_sat:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 501 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptosi double %a to i16 %1 = fptosi double %a to i16
ret i16 %1 ret i16 %1
} }
define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind { define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32IFD-LABEL: fcvt_w_s_sat_i16: ; RV32IFD-LABEL: fcvt_w_s_sat_i16:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0
; RV32IFD-NEXT: beqz a0, .LBB26_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0) ; RV32IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1)
; RV32IFD-NEXT: fld ft1, %lo(.LCPI26_1)(a0) ; RV32IFD-NEXT: fld ft1, %lo(.LCPI26_1)(a0)
; RV32IFD-NEXT: fmax.d ft0, fa0, ft0 ; RV32IFD-NEXT: fmax.d ft0, fa0, ft0
; RV32IFD-NEXT: fmin.d ft0, ft0, ft1 ; RV32IFD-NEXT: fmin.d ft0, ft0, ft1
; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz ; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
; RV32IFD-NEXT: .LBB26_2: # %start ; RV32IFD-NEXT: feq.d a1, fa0, fa0
; RV32IFD-NEXT: seqz a1, a1
; RV32IFD-NEXT: addi a1, a1, -1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_w_s_sat_i16: ; RV64IFD-LABEL: fcvt_w_s_sat_i16:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: beqz a0, .LBB26_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0) ; RV64IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1) ; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI26_1)(a0) ; RV64IFD-NEXT: fld ft1, %lo(.LCPI26_1)(a0)
; RV64IFD-NEXT: fmax.d ft0, fa0, ft0 ; RV64IFD-NEXT: fmax.d ft0, fa0, ft0
; RV64IFD-NEXT: fmin.d ft0, ft0, ft1 ; RV64IFD-NEXT: fmin.d ft0, ft0, ft1
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz ; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
; RV64IFD-NEXT: .LBB26_2: # %start ; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i16: ; RV32I-LABEL: fcvt_w_s_sat_i16:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 265728 ; RV32I-NEXT: lui a0, 265728
; RV32I-NEXT: addi a3, a0, -64 ; RV32I-NEXT: addi a3, a0, -64
; RV32I-NEXT: li s0, 0 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 790016 ; RV32I-NEXT: lui a3, 790016
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfsi@plt ; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: lui s5, 1048568 ; RV32I-NEXT: lui s4, 1048568
; RV32I-NEXT: bltz s4, .LBB26_2 ; RV32I-NEXT: bltz s3, .LBB26_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: .LBB26_2: # %start ; RV32I-NEXT: .LBB26_2: # %start
; RV32I-NEXT: bge s0, s3, .LBB26_4 ; RV32I-NEXT: blez s2, .LBB26_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: lui a0, 8 ; RV32I-NEXT: lui a0, 8
; RV32I-NEXT: addi s5, a0, -1 ; RV32I-NEXT: addi s4, a0, -1
; RV32I-NEXT: .LBB26_4: # %start ; RV32I-NEXT: .LBB26_4: # %start
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bnez a0, .LBB26_6 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: mv s0, s5 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: .LBB26_6: # %start ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: slli a0, s0, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_w_s_sat_i16: ; RV64I-LABEL: fcvt_w_s_sat_i16:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
Show All 20 Lines
; RV64I-NEXT: blez a0, .LBB26_4 ; RV64I-NEXT: blez a0, .LBB26_4
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: lui a0, 8 ; RV64I-NEXT: lui a0, 8
; RV64I-NEXT: addiw s2, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: .LBB26_4: # %start ; RV64I-NEXT: .LBB26_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt ; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: bnez a0, .LBB26_6 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: # %bb.5: # %start ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: .LBB26_6: # %start
; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 265984 ; RV32I-NEXT: lui a0, 265984
; RV32I-NEXT: addi a3, a0, -32 ; RV32I-NEXT: addi a3, a0, -32
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfsi@plt ; RV32I-NEXT: call __fixunsdfsi@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: bltz s3, .LBB28_2 ; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgtz s3, .LBB28_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: slti a2, s0, 0
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a2, a2, a0
; RV32I-NEXT: .LBB28_2: # %start ; RV32I-NEXT: .LBB28_2: # %start
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: and a0, a2, a1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: bgtz s0, .LBB28_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: .LBB28_4: # %start
; RV32I-NEXT: and a0, a2, a0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_wu_s_sat_i16: ; RV64I-LABEL: fcvt_wu_s_sat_i16:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __fixunsdfdi@plt ; RV64I-NEXT: call __fixunsdfdi@plt
; RV64I-NEXT: li s2, 0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: bltz s1, .LBB28_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: .LBB28_2: # %start
; RV64I-NEXT: lui a0, 8312 ; RV64I-NEXT: lui a0, 8312
; RV64I-NEXT: addiw a0, a0, -1 ; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: slli a1, a0, 37 ; RV64I-NEXT: slli a1, a0, 37
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgtz a0, .LBB28_4 ; RV64I-NEXT: bgtz a0, .LBB28_2
; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: slti a0, s0, 0
; RV64I-NEXT: .LBB28_4: # %start ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a2, a0, s1
; RV64I-NEXT: .LBB28_2: # %start
; RV64I-NEXT: and a0, a2, a1 ; RV64I-NEXT: and a0, a2, a1
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
Show All 32 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fptosi double %a to i8 %1 = fptosi double %a to i8
ret i8 %1 ret i8 %1
} }
define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind { define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV32IFD-LABEL: fcvt_w_s_sat_i8: ; RV32IFD-LABEL: fcvt_w_s_sat_i8:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0
; RV32IFD-NEXT: beqz a0, .LBB30_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0) ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0) ; RV32IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1) ; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1)
; RV32IFD-NEXT: fld ft1, %lo(.LCPI30_1)(a0) ; RV32IFD-NEXT: fld ft1, %lo(.LCPI30_1)(a0)
; RV32IFD-NEXT: fmax.d ft0, fa0, ft0 ; RV32IFD-NEXT: fmax.d ft0, fa0, ft0
; RV32IFD-NEXT: fmin.d ft0, ft0, ft1 ; RV32IFD-NEXT: fmin.d ft0, ft0, ft1
; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz ; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
; RV32IFD-NEXT: .LBB30_2: # %start ; RV32IFD-NEXT: feq.d a1, fa0, fa0
; RV32IFD-NEXT: seqz a1, a1
; RV32IFD-NEXT: addi a1, a1, -1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_w_s_sat_i8: ; RV64IFD-LABEL: fcvt_w_s_sat_i8:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: beqz a0, .LBB30_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0) ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0) ; RV64IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1) ; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1)
; RV64IFD-NEXT: fld ft1, %lo(.LCPI30_1)(a0) ; RV64IFD-NEXT: fld ft1, %lo(.LCPI30_1)(a0)
; RV64IFD-NEXT: fmax.d ft0, fa0, ft0 ; RV64IFD-NEXT: fmax.d ft0, fa0, ft0
; RV64IFD-NEXT: fmin.d ft0, ft0, ft1 ; RV64IFD-NEXT: fmin.d ft0, ft0, ft1
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz ; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
; RV64IFD-NEXT: .LBB30_2: # %start ; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_s_sat_i8: ; RV32I-LABEL: fcvt_w_s_sat_i8:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 263676 ; RV32I-NEXT: lui a3, 263676
; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 787968 ; RV32I-NEXT: lui a3, 787968
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfsi@plt ; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: li a1, -128 ; RV32I-NEXT: li a1, -128
; RV32I-NEXT: bltz s4, .LBB30_2 ; RV32I-NEXT: bltz s3, .LBB30_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB30_2: # %start ; RV32I-NEXT: .LBB30_2: # %start
; RV32I-NEXT: li s4, 127 ; RV32I-NEXT: li s3, 127
; RV32I-NEXT: blt s0, s3, .LBB30_4 ; RV32I-NEXT: bgtz s2, .LBB30_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s4, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: .LBB30_4: # %start ; RV32I-NEXT: .LBB30_4: # %start
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bnez a0, .LBB30_6 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: mv s0, s4 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: .LBB30_6: # %start ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: slli a0, s0, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_w_s_sat_i8: ; RV64I-LABEL: fcvt_w_s_sat_i8:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
Show All 19 Lines
; RV64I-NEXT: li s1, 127 ; RV64I-NEXT: li s1, 127
; RV64I-NEXT: bgtz a0, .LBB30_4 ; RV64I-NEXT: bgtz a0, .LBB30_4
; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv s1, s2 ; RV64I-NEXT: mv s1, s2
; RV64I-NEXT: .LBB30_4: # %start ; RV64I-NEXT: .LBB30_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt ; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: bnez a0, .LBB30_6 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: # %bb.5: # %start ; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: .LBB30_6: # %start
; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 263934 ; RV32I-NEXT: lui a3, 263934
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfsi@plt ; RV32I-NEXT: call __fixunsdfsi@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 255
; RV32I-NEXT: bltz s3, .LBB32_2 ; RV32I-NEXT: bgtz s3, .LBB32_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: slti a1, s0, 0
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a1, a0
; RV32I-NEXT: .LBB32_2: # %start ; RV32I-NEXT: .LBB32_2: # %start
; RV32I-NEXT: li a0, 255 ; RV32I-NEXT: andi a0, a1, 255
; RV32I-NEXT: bgtz s0, .LBB32_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB32_4: # %start
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_wu_s_sat_i8: ; RV64I-LABEL: fcvt_wu_s_sat_i8:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __fixunsdfdi@plt ; RV64I-NEXT: call __fixunsdfdi@plt
; RV64I-NEXT: li s2, 0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: bltz s1, .LBB32_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: .LBB32_2: # %start
; RV64I-NEXT: lui a0, 131967 ; RV64I-NEXT: lui a0, 131967
; RV64I-NEXT: slli a1, a0, 33 ; RV64I-NEXT: slli a1, a0, 33
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: li a1, 255 ; RV64I-NEXT: li a1, 255
; RV64I-NEXT: bgtz a0, .LBB32_4 ; RV64I-NEXT: bgtz a0, .LBB32_2
; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: slti a0, s0, 0
; RV64I-NEXT: .LBB32_4: # %start ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a1, a0, s1
; RV64I-NEXT: .LBB32_2: # %start
; RV64I-NEXT: andi a0, a1, 255 ; RV64I-NEXT: andi a0, a1, 255
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
%0 = tail call i8 @llvm.fptoui.sat.i8.f64(double %a) %0 = tail call i8 @llvm.fptoui.sat.i8.f64(double %a)
ret i8 %0 ret i8 %0
} }
declare i8 @llvm.fptoui.sat.i8.f64(double) declare i8 @llvm.fptoui.sat.i8.f64(double)
define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind { define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind {
; RV32IFD-LABEL: fcvt_wu_d_sat_zext: ; RV32IFD-LABEL: fcvt_wu_d_sat_zext:
; RV32IFD: # %bb.0: # %start ; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0
; RV32IFD-NEXT: beqz a0, .LBB33_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz ; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV32IFD-NEXT: .LBB33_2: # %start ; RV32IFD-NEXT: feq.d a1, fa0, fa0
; RV32IFD-NEXT: seqz a1, a1
; RV32IFD-NEXT: addi a1, a1, -1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcvt_wu_d_sat_zext: ; RV64IFD-LABEL: fcvt_wu_d_sat_zext:
; RV64IFD: # %bb.0: # %start ; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
; RV64IFD-NEXT: beqz a0, .LBB33_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz ; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64IFD-NEXT: feq.d a1, fa0, fa0
; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: slli a0, a0, 32 ; RV64IFD-NEXT: slli a0, a0, 32
; RV64IFD-NEXT: srli a0, a0, 32 ; RV64IFD-NEXT: srli a0, a0, 32
; RV64IFD-NEXT: .LBB33_2: # %start
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_wu_d_sat_zext: ; RV32I-LABEL: fcvt_wu_d_sat_zext:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
Show All 32 Lines
; ;
; RV64I-LABEL: fcvt_wu_d_sat_zext: ; RV64I-LABEL: fcvt_wu_d_sat_zext:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __fixunsdfdi@plt ; RV64I-NEXT: call __fixunsdfdi@plt
; RV64I-NEXT: li s2, 0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: bltz s1, .LBB33_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: .LBB33_2: # %start
; RV64I-NEXT: li a0, 1055 ; RV64I-NEXT: li a0, 1055
; RV64I-NEXT: slli a0, a0, 31 ; RV64I-NEXT: slli a0, a0, 31
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: slli a1, a0, 21 ; RV64I-NEXT: slli a1, a0, 21
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: blez a0, .LBB33_4 ; RV64I-NEXT: bgtz a0, .LBB33_2
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: slti a0, s0, 0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: j .LBB33_3
; RV64I-NEXT: .LBB33_2:
; RV64I-NEXT: li a0, -1 ; RV64I-NEXT: li a0, -1
; RV64I-NEXT: srli s2, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: .LBB33_4: # %start ; RV64I-NEXT: .LBB33_3: # %start
; RV64I-NEXT: slli a0, s2, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
%0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a) %0 = tail call i32 @llvm.fptoui.sat.i32.f64(double %a)
ret i32 %0 ret i32 %0
} }
define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind { define signext i32 @fcvt_w_d_sat_sext(double %a) nounwind {
; CHECKIFD-LABEL: fcvt_w_d_sat_sext: ; CHECKIFD-LABEL: fcvt_w_d_sat_sext:
; CHECKIFD: # %bb.0: # %start ; CHECKIFD: # %bb.0: # %start
; CHECKIFD-NEXT: feq.d a0, fa0, fa0
; CHECKIFD-NEXT: beqz a0, .LBB34_2
; CHECKIFD-NEXT: # %bb.1:
; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz ; CHECKIFD-NEXT: fcvt.w.d a0, fa0, rtz
; CHECKIFD-NEXT: .LBB34_2: # %start ; CHECKIFD-NEXT: feq.d a1, fa0, fa0
; CHECKIFD-NEXT: seqz a1, a1
; CHECKIFD-NEXT: addi a1, a1, -1
; CHECKIFD-NEXT: and a0, a1, a0
; CHECKIFD-NEXT: ret ; CHECKIFD-NEXT: ret
; ;
; RV32I-LABEL: fcvt_w_d_sat_sext: ; RV32I-LABEL: fcvt_w_d_sat_sext:
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 269824 ; RV32I-NEXT: lui a0, 269824
; RV32I-NEXT: addi a3, a0, -1 ; RV32I-NEXT: addi a3, a0, -1
; RV32I-NEXT: lui a2, 1047552 ; RV32I-NEXT: lui a2, 1047552
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 794112 ; RV32I-NEXT: lui a3, 794112
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfsi@plt ; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: lui s5, 524288 ; RV32I-NEXT: lui s4, 524288
; RV32I-NEXT: bltz s4, .LBB34_2 ; RV32I-NEXT: bltz s3, .LBB34_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: .LBB34_2: # %start ; RV32I-NEXT: .LBB34_2: # %start
; RV32I-NEXT: bge s2, s3, .LBB34_4 ; RV32I-NEXT: blez s2, .LBB34_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: addi s5, a1, -1 ; RV32I-NEXT: addi s4, a1, -1
; RV32I-NEXT: .LBB34_4: # %start ; RV32I-NEXT: .LBB34_4: # %start
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bnez a0, .LBB34_6 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: mv s2, s5 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: .LBB34_6: # %start
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_w_d_sat_sext: ; RV64I-LABEL: fcvt_w_d_sat_sext:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
Show All 22 Lines
; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: blez a0, .LBB34_4 ; RV64I-NEXT: blez a0, .LBB34_4
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: addiw s2, s3, -1 ; RV64I-NEXT: addiw s2, s3, -1
; RV64I-NEXT: .LBB34_4: # %start ; RV64I-NEXT: .LBB34_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt ; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: bnez a0, .LBB34_6 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: # %bb.5: # %start ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: .LBB34_6: # %start
; RV64I-NEXT: sext.w a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
%0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a) %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
ret i32 %0 ret i32 %0
} }

llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

llvm/test/CodeGen/RISCV/float-convert.ll

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

llvm/test/CodeGen/RISCV/forced-atomics.ll

llvm/test/CodeGen/RISCV/fpclamptosat.ll

llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll

llvm/test/CodeGen/RISCV/half-convert.ll

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

llvm/test/CodeGen/RISCV/rotl-rotr.ll

llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll

llvm/test/CodeGen/RISCV/rv32zbs.ll

llvm/test/CodeGen/RISCV/rv64zbb.ll

llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll

llvm/test/CodeGen/RISCV/rvv/floor-vp.ll

llvm/test/CodeGen/RISCV/rvv/round-vp.ll

llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll

llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll

llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll

llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll

llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll

llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vpload.ll

llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vpstore.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll

llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll

llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll

llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll

llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll

llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll

llvm/test/CodeGen/RISCV/shift-masked-shamt.ll

llvm/test/CodeGen/RISCV/shifts.ll

llvm/test/CodeGen/RISCV/usub_sat.ll

llvm/test/CodeGen/RISCV/usub_sat_plus.ll

llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll