[RISCV] Disable SLP vectorization by default due to unresolved profitability issues

[reames]

Summary

This change implements a TTI query with the goal of disabling slp vectorization on RISCV. The current default configuration disables SLP already, but its current tied to the ability to lower fixed length vectors. Over in D131508, I want to enable fixed length vectors for purposes of LoopVectorizer, but preliminary analysis has revealed a couple of SLP specific issues we need to resolve before enabling it by default. This change exists to allow us to enable LV without SLP.

The major issues for SLP/RISCV I currently know of are:

• We have a cost modeling problem for vector constants. SLP mostly ignores the cost of materializing constants, and on most targets that works out mostly okay. RISCV has unusually expensive constant materialization for large constants, so we end up with common patterns (e.g. initializing adjacent unsigned fields with constants) being unprofitably vectorized. Work on this started under D126885, and there is ongoing discussion on follow ups there.
• We will vectorize sub-word parallel operations and don't have robust lowering support to re-scalarize. Consider a pair of i32 stores which could be vectorized as <2 x i32> or could be done as a single i64 store. The later is likely more profitable, but not what we currently generate. I have not fully dug into why yet.

Note that both of these issues could exist for LV in theory, but are significantly less likely. LV is strongly biased towards constant splats and longer vectors. Splats are significantly cheaper to lower (as a class), and longer vectors allows fixed cost errors to be amortized across more elements.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

public:
   }
   Optional<unsigned> getMaxVScale() const;
   Optional<unsigned> getVScaleForTuning() const;
 
   TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
 
   unsigned getRegUsageForType(Type *Ty);
 
+  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
+
   InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
                                         Align Alignment, unsigned AddressSpace,
                                         TTI::TargetCostKind CostKind);
 
   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                TTI::UnrollingPreferences &UP,
                                OptimizationRemarkEmitter *ORE);
 

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

 
 static cl::opt<unsigned> RVVRegisterWidthLMUL(
     "riscv-v-register-bit-width-lmul",
     cl::desc(
         "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
         "by autovectorized code. Fractional LMULs are not supported."),
     cl::init(1), cl::Hidden);
 
+static cl::opt<unsigned> SLPMaxVF(
+    "riscv-v-slp-max-vf",
+    cl::desc(
+        "Result used for getMaximumVF query which is used exclusively by "
+        "SLP vectorizer.  Defaults to 1 which disables SLP."),
+    cl::init(1), cl::Hidden);
+
 InstructionCost RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
                                             TTI::TargetCostKind CostKind) {
   assert(Ty->isIntegerTy() &&
          "getIntImmCost can only estimate cost of materialising integers");
 
   // We have a Zero register, so 0 is always free.
   if (Imm == 0)
     return TTI::TCC_Free;
if (Size.isScalable() && ST->hasVInstructions())
       return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
 
     if (ST->useRVVForFixedLengthVectors())
       return divideCeil(Size, ST->getRealMinVLen());
   }
 
   return BaseT::getRegUsageForType(Ty);
 }
+
+unsigned RISCVTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
+  // This interface is currently only used by SLP.  Returning 1 (which is the
+  // default value for SLPMaxVF) disables SLP. We currently have a cost modeling
+  // problem w/ constant materialization which causes SLP to perform majorly
+  // unprofitable transformations.
+  // TODO: Figure out constant materialization cost modeling and remove.
+  return SLPMaxVF;
+}

llvm/test/Transforms/SLPVectorizer/RISCV/load-store.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+v \
-; RUN: -riscv-v-vector-bits-min=-1 -S | FileCheck %s --check-prefixes=CHECK
+; RUN: -riscv-v-vector-bits-min=-1 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK
+; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+v -S | FileCheck %s --check-prefixes=DEFAULT
+
 
 define void @simple_copy(ptr %dest, ptr %p) {
 ; CHECK-LABEL: @simple_copy(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    store <2 x i16> [[TMP0]], ptr [[DEST:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
+; DEFAULT-LABEL: @simple_copy(
+; DEFAULT-NEXT:  entry:
+; DEFAULT-NEXT:    [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4
+; DEFAULT-NEXT:    [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1
+; DEFAULT-NEXT:    [[E1:%.*]] = load i16, ptr [[INC]], align 2
+; DEFAULT-NEXT:    store i16 [[E0]], ptr [[DEST:%.*]], align 4
+; DEFAULT-NEXT:    [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
+; DEFAULT-NEXT:    store i16 [[E1]], ptr [[INC2]], align 2
+; DEFAULT-NEXT:    ret void
+;
 entry:
   %e0 = load i16, ptr %p, align 4
   %inc = getelementptr inbounds i16, ptr %p, i64 1
   %e1 = load i16, ptr %inc, align 2
 
   store i16 %e0, ptr %dest, align 4
   %inc2 = getelementptr inbounds i16, ptr %dest, i64 1
   store i16 %e1, ptr %inc2, align 2
   ret void
 }
 
 define void @vec_add(ptr %dest, ptr %p) {
 ; CHECK-LABEL: @vec_add(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x i16>, ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i16> [[TMP0]], <i16 1, i16 1>
 ; CHECK-NEXT:    store <2 x i16> [[TMP1]], ptr [[DEST:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
+; DEFAULT-LABEL: @vec_add(
+; DEFAULT-NEXT:  entry:
+; DEFAULT-NEXT:    [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4
+; DEFAULT-NEXT:    [[INC:%.*]] = getelementptr inbounds i16, ptr [[P]], i64 1
+; DEFAULT-NEXT:    [[E1:%.*]] = load i16, ptr [[INC]], align 2
+; DEFAULT-NEXT:    [[A0:%.*]] = add i16 [[E0]], 1
+; DEFAULT-NEXT:    [[A1:%.*]] = add i16 [[E1]], 1
+; DEFAULT-NEXT:    store i16 [[A0]], ptr [[DEST:%.*]], align 4
+; DEFAULT-NEXT:    [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
+; DEFAULT-NEXT:    store i16 [[A1]], ptr [[INC2]], align 2
+; DEFAULT-NEXT:    ret void
+;
 entry:
   %e0 = load i16, ptr %p, align 4
   %inc = getelementptr inbounds i16, ptr %p, i64 1
   %e1 = load i16, ptr %inc, align 2
 
   %a0 = add i16 %e0, 1
   %a1 = add i16 %e1, 1
 
   store i16 %a0, ptr %dest, align 4
   %inc2 = getelementptr inbounds i16, ptr %dest, i64 1
   store i16 %a1, ptr %inc2, align 2
   ret void
 }
 
 
 define void @splat_store(ptr %dest, ptr %p) {
 ; CHECK-LABEL: @splat_store(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    store i16 [[E0]], ptr [[DEST:%.*]], align 4
 ; CHECK-NEXT:    [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
 ; CHECK-NEXT:    store i16 [[E0]], ptr [[INC2]], align 2
 ; CHECK-NEXT:    ret void
 ;
+; DEFAULT-LABEL: @splat_store(
+; DEFAULT-NEXT:  entry:
+; DEFAULT-NEXT:    [[E0:%.*]] = load i16, ptr [[P:%.*]], align 4
+; DEFAULT-NEXT:    store i16 [[E0]], ptr [[DEST:%.*]], align 4
+; DEFAULT-NEXT:    [[INC2:%.*]] = getelementptr inbounds i16, ptr [[DEST]], i64 1
+; DEFAULT-NEXT:    store i16 [[E0]], ptr [[INC2]], align 2
+; DEFAULT-NEXT:    ret void
+;
 entry:
   %e0 = load i16, ptr %p, align 4
 
   store i16 %e0, ptr %dest, align 4
   %inc2 = getelementptr inbounds i16, ptr %dest, i64 1
   store i16 %e0, ptr %inc2, align 2
   ret void
 }
 

llvm/test/Transforms/SLPVectorizer/RISCV/rvv-min-vector-size.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+v \
-; RUN: -riscv-v-vector-bits-min=128 -S | FileCheck %s --check-prefixes=CHECK,CHECK-128
+; RUN: -riscv-v-vector-bits-min=128 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK-128
 ; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+v \
-; RUN: -riscv-v-vector-bits-min=256 -S | FileCheck %s --check-prefixes=CHECK,CHECK-256
+; RUN: -riscv-v-vector-bits-min=256 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK-256
 ; RUN: opt < %s -slp-vectorizer -mtriple=riscv64 -mattr=+v \
-; RUN: -riscv-v-vector-bits-min=512 -S | FileCheck %s --check-prefixes=CHECK,CHECK-512
+; RUN: -riscv-v-vector-bits-min=512 -riscv-v-slp-max-vf=0 -S | FileCheck %s --check-prefixes=CHECK,CHECK-512
 
 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
 target triple = "riscv64"
 
 define void @foo(i64* nocapture writeonly %da) {
 ; CHECK-128-LABEL: @foo(
 ; CHECK-128-NEXT:  entry:
 ; CHECK-128-NEXT:    store i64 0, i64* [[DA:%.*]], align 8