[RISCV] Return true in hasBitTest when Zbs is enabled and update BEXTI pattern for resulting canonicalisation

[asb]

Summary

As the Zbs extension includes bext[i] for bit extract, we can
unconditionally return true from this hook. This hook causes the DAG
combiner to perform the following canonicalisation:

and (not (srl X, C)), 1 --> (and X, 1<<C) == 0
and (srl (not X), C)), 1 --> (and X, 1<<C) == 0

As simply changing the hook causes a codegen regression, this patch also
modifies a BEXTI pattern to match this canonicalised form.

As BSETINVMask is now used for BEXT as well as BSET and BINV, it has
been renamed to the more generic SingleBitSetMask.

There is one codegen change in bittest.ll for bittest_31_i64 (NOT+BEXTI
rather than NOT+SRLIW). This is neutral in terms of code quality.

[reames]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

896

I think this needs to use BSETINVMask. If I follow the existing logic right, we're preferring and/xor for immediate masks which fit within 12 bits.

902

This pattern looks to be matching the old canonicalization, but oddly, not using the BINV.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

896

BINVI just toggles the bit in place. It doesn’t produce 0 or 1.

902

We can’t use binvi. It doesn’t return a 0 or 1 value.

[asb]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

902

Oops, that's a silly mistake on my part. I'll respin this patch.

[asb]

Fix error in first version of this patch, update patch description.

[reames]

LGTM

Glancing at the pattern, I find myself wondering if we can generalize further. You have:

def : Pat<(seteq (and GPR:$rs1, SingleBitSetMask:$mask), 0),
          (BEXTI (XORI GPR:$rs1, -1), SingleBitSetMask:$mask)>;

Could we do something like:

def : Pat<(and GPR:$rs1, SingleBitSetMask:$mask),
          (BEXTI GPR:$rs1, SingleBitSetMask:$mask)>;

Follow up only to be clear.

[craig.topper]

In D131482#3712522, @reames wrote:

LGTM

Glancing at the pattern, I find myself wondering if we can generalize further. You have:

def : Pat<(seteq (and GPR:$rs1, SingleBitSetMask:$mask), 0),
          (BEXTI (XORI GPR:$rs1, -1), SingleBitSetMask:$mask)>;

Could we do something like:

def : Pat<(and GPR:$rs1, SingleBitSetMask:$mask),
          (BEXTI GPR:$rs1, SingleBitSetMask:$mask)>;

Follow up only to be clear.

That does not work. BEXTI returns 0 or 1. An And keeps the bit in the same place.

[reames]

In D131482#3713009, @craig.topper wrote:

In D131482#3712522, @reames wrote:

LGTM

Glancing at the pattern, I find myself wondering if we can generalize further. You have:

def : Pat<(seteq (and GPR:$rs1, SingleBitSetMask:$mask), 0),
          (BEXTI (XORI GPR:$rs1, -1), SingleBitSetMask:$mask)>;

Could we do something like:

def : Pat<(and GPR:$rs1, SingleBitSetMask:$mask),
          (BEXTI GPR:$rs1, SingleBitSetMask:$mask)>;

Follow up only to be clear.

That does not work. BEXTI returns 0 or 1. An And keeps the bit in the same place.

Doh. And the same mistake I already made once in this review as well. Oops.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (VT.isVector())
     return false;
 
   return (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp() ||
           Subtarget.hasStdExtZbkb()) &&
          !isa<ConstantSDNode>(Y);
 }
 
 bool RISCVTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
+  // Zbs provides bext[.i] and binv[.i].
+  if (Subtarget.hasStdExtZbs())
+    return X.getValueType().isScalarInteger();
   // We can use ANDI+SEQZ/SNEZ as a bit test. Y contains the bit position.
   auto *C = dyn_cast<ConstantSDNode>(Y);
   return C && C->getAPIntValue().ule(10);
 }
 
 bool RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                             Type *Ty) const {
   assert(Ty->isIntegerTy());

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 }]>;
 
 // Pattern to exclude simm12 immediates from matching.
 def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
   auto *C = dyn_cast<ConstantSDNode>(N);
   return !C || !isInt<12>(C->getSExtValue());
 }]>;
 
+def pow2_mask : ImmLeaf<XLenVT, [{
+  if (Subtarget->is64Bit())
+    return isPowerOf2_64(Imm);
+  return isPowerOf2_32(Imm);
+}], BSETINVXForm>;
+
 def sh1add_op : ComplexPattern<XLenVT, 1, "selectSH1ADDOp", [], [], 6>;
 def sh2add_op : ComplexPattern<XLenVT, 1, "selectSH2ADDOp", [], [], 6>;
 def sh3add_op : ComplexPattern<XLenVT, 1, "selectSH3ADDOp", [], [], 6>;
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
def : Pat<(shiftop<shl> 1, GPR:$rs2),
           (BSET X0, GPR:$rs2)>;
 
 def : Pat<(and GPR:$rs1, BCLRMask:$mask),
           (BCLRI GPR:$rs1, BCLRMask:$mask)>;
 def : Pat<(or GPR:$rs1, BSETINVMask:$mask),
           (BSETI GPR:$rs1, BSETINVMask:$mask)>;
 def : Pat<(xor GPR:$rs1, BSETINVMask:$mask),
           (BINVI GPR:$rs1, BSETINVMask:$mask)>;
+def : Pat<(seteq (and GPR:$rs1, pow2_mask:$mask), 0),
+          (BINVI GPR:$rs1, pow2_mask:$mask)>;
 
 def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
           (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
 
 def : Pat<(and (not (srl GPR:$rs1, uimmlog2xlen:$shamt)), (XLenVT 1)),
           (XORI (BEXTI GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1))>;
 
 def : Pat<(or GPR:$r, BSETINVTwoBitsMask:$i),
           (BSETI (BSETI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
 def : Pat<(xor GPR:$r, BSETINVTwoBitsMask:$i),
           (BINVI (BINVI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
                  (BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;

llvm/test/CodeGen/RISCV/bittest.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32,RV32I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64,RV64I
 ; RUN: llc -mtriple=riscv32 -mattr=+zbs -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,ZBS,RV32,RV32ZBS
 ; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,ZBS,RV64,RV64ZBS
 
 define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
-; CHECK-LABEL: bittest_7_i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    andi a0, a0, 128
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: bittest_7_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 128
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: bittest_7_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 128
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    ret
+;
+; ZBS-LABEL: bittest_7_i32:
+; ZBS:       # %bb.0:
+; ZBS-NEXT:    binvi a0, a0, 7
+; ZBS-NEXT:    ret
   %shr = lshr i32 %a, 7
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
 define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
-; CHECK-LABEL: bittest_10_i32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    andi a0, a0, 1024
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: bittest_10_i32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 1024
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: bittest_10_i32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 1024
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    ret
+;
+; ZBS-LABEL: bittest_10_i32:
+; ZBS:       # %bb.0:
+; ZBS-NEXT:    binvi a0, a0, 10
+; ZBS-NEXT:    ret
   %shr = lshr i32 %a, 10
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
 define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
 ; RV32I-LABEL: bittest_11_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    slli a0, a0, 20
 ; RV32I-NEXT:    srli a0, a0, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: bittest_11_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    slli a0, a0, 52
 ; RV64I-NEXT:    srli a0, a0, 63
 ; RV64I-NEXT:    ret
 ;
 ; ZBS-LABEL: bittest_11_i32:
 ; ZBS:       # %bb.0:
-; ZBS-NEXT:    not a0, a0
-; ZBS-NEXT:    bexti a0, a0, 11
+; ZBS-NEXT:    binvi a0, a0, 11
 ; ZBS-NEXT:    ret
   %shr = lshr i32 %a, 11
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
 define signext i32 @bittest_31_i32(i32 signext %a) nounwind {

 ; RV64-NEXT:    ret
   %shr = lshr i32 %a, 31
   %not = xor i32 %shr, -1
   %and = and i32 %not, 1
   ret i32 %and
 }
 
 define i64 @bittest_7_i64(i64 %a) nounwind {
-; RV32-LABEL: bittest_7_i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    andi a0, a0, 128
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    li a1, 0
-; RV32-NEXT:    ret
+; RV32I-LABEL: bittest_7_i64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 128
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    ret
 ;
-; RV64-LABEL: bittest_7_i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    andi a0, a0, 128
-; RV64-NEXT:    seqz a0, a0
-; RV64-NEXT:    ret
+; RV64I-LABEL: bittest_7_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 128
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bittest_7_i64:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    binvi a0, a0, 7
+; RV32ZBS-NEXT:    li a1, 0
+; RV32ZBS-NEXT:    ret
+;
+; RV64ZBS-LABEL: bittest_7_i64:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    binvi a0, a0, 7
+; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 7
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_10_i64(i64 %a) nounwind {
-; RV32-LABEL: bittest_10_i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    andi a0, a0, 1024
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    li a1, 0
-; RV32-NEXT:    ret
+; RV32I-LABEL: bittest_10_i64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 1024
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    li a1, 0
+; RV32I-NEXT:    ret
 ;
-; RV64-LABEL: bittest_10_i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    andi a0, a0, 1024
-; RV64-NEXT:    seqz a0, a0
-; RV64-NEXT:    ret
+; RV64I-LABEL: bittest_10_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 1024
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    ret
+;
+; RV32ZBS-LABEL: bittest_10_i64:
+; RV32ZBS:       # %bb.0:
+; RV32ZBS-NEXT:    binvi a0, a0, 10
+; RV32ZBS-NEXT:    li a1, 0
+; RV32ZBS-NEXT:    ret
+;
+; RV64ZBS-LABEL: bittest_10_i64:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    binvi a0, a0, 10
+; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 10
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_11_i64(i64 %a) nounwind {
 ; RV32I-LABEL: bittest_11_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    slli a0, a0, 20
 ; RV32I-NEXT:    srli a0, a0, 31
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: bittest_11_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    slli a0, a0, 52
 ; RV64I-NEXT:    srli a0, a0, 63
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBS-LABEL: bittest_11_i64:
 ; RV32ZBS:       # %bb.0:
-; RV32ZBS-NEXT:    not a0, a0
-; RV32ZBS-NEXT:    bexti a0, a0, 11
+; RV32ZBS-NEXT:    binvi a0, a0, 11
 ; RV32ZBS-NEXT:    li a1, 0
 ; RV32ZBS-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_11_i64:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    not a0, a0
-; RV64ZBS-NEXT:    bexti a0, a0, 11
+; RV64ZBS-NEXT:    binvi a0, a0, 11
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 11
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_31_i64(i64 %a) nounwind {
 ; RV32-LABEL: bittest_31_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    not a0, a0
 ; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: bittest_31_i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    not a0, a0
-; RV64-NEXT:    srliw a0, a0, 31
-; RV64-NEXT:    ret
+; RV64I-LABEL: bittest_31_i64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    srliw a0, a0, 31
+; RV64I-NEXT:    ret
+;
+; RV64ZBS-LABEL: bittest_31_i64:
+; RV64ZBS:       # %bb.0:
+; RV64ZBS-NEXT:    binvi a0, a0, 31
+; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 31
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_32_i64(i64 %a) nounwind {
 ; RV32-LABEL: bittest_32_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    not a0, a1
 ; RV32-NEXT:    andi a0, a0, 1
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    ret
 ;
 ; RV64I-LABEL: bittest_32_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    slli a0, a0, 31
 ; RV64I-NEXT:    srli a0, a0, 63
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bittest_32_i64:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    not a0, a0
-; RV64ZBS-NEXT:    bexti a0, a0, 32
+; RV64ZBS-NEXT:    binvi a0, a0, 32
 ; RV64ZBS-NEXT:    ret
   %shr = lshr i64 %a, 32
   %not = xor i64 %shr, -1
   %and = and i64 %not, 1
   ret i64 %and
 }
 
 define i64 @bittest_63_i64(i64 %a) nounwind {