[RISCV] Teach translateSetCCForBranch to help improve constant materialization.

[craig.topper]

Summary

InstCombine and DAGCombine both canonicalize setge X, C to
setgt X, C-1. C might be easier to materialize than C.

This patch teaches translateSetCCForBranch to reverse the canonicalize
if it will give us a single 'addi' or 'lui' to materialize the constant.

This was inspired by https://github.com/llvm/llvm-project/issues/56666
and wondering if we should do something like getAArch64Cmp.

[craig.topper]

Need to guard against adding 1 to INT64_MIN. Though I find it unlikely that would occur.

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1409

Please land the refactor to introduce the switch and rebase.

1417

Can't we generalize this to be if RISCVMatInt::getIntMatCost(C+1) < RISCVMatInt::getIntMatCost(C)?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1417

I was trying to be a little conservative if the constant required multiple instructions and was used by other instructions. Changing it could introduce multiple slightly different constants. I figured creating an LUI or ADDI wasn't as bad.

Maybe I should check one use and/or opaque constant?

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1417

I'd be fine with either the one use check, or a comment that says there deliberately isn't a one-use check and that's why this is restricted to the single instruction forms.

I think you could also restrict the single instruction case in terms of the getIntMatCost interface too, but that's not required.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (isPowerOf2_64(Mask) && !isInt<12>(Mask)) {
       LHS = LHS.getOperand(0);
       if (ShAmt != 0)
         LHS = DAG.getNode(ISD::SHL, DL, LHS.getValueType(), LHS,
                           DAG.getConstant(ShAmt, DL, LHS.getValueType()));
       return;
     }
   }
 
+  if (auto *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
+    int64_t C = RHSC->getSExtValue();
+    switch (CC) {
+    default: break;
+    case ISD::SETGT:
       // Convert X > -1 to X >= 0.
-  if (CC == ISD::SETGT && isAllOnesConstant(RHS)) {
-    RHS = DAG.getConstant(0, DL, RHS.getValueType());
+      // Convert X > -2049 to X >= -2048.
+      // Or X > C to C >= C+1 if it could use LUI.
+      if (C == -1 ||
+          (!isInt<12>(C) && isInt<12>(C + 1)) ||
+          (isInt<32>(C + 1) && (C & 0xfff) == 0xfff)) {
+        RHS = DAG.getConstant(C + 1, DL, RHS.getValueType());
         CC = ISD::SETGE;
         return;
       }
-  // Convert X < 1 to 0 >= X.
-  if (CC == ISD::SETLT && isOneConstant(RHS)) {
+      break;
+    case ISD::SETLT:
+      if (C == 1) {
         RHS = LHS;
         LHS = DAG.getConstant(0, DL, RHS.getValueType());
         CC = ISD::SETGE;
         return;
       }
+      break;
+    }
+  }
 
   switch (CC) {
   default:
     break;
   case ISD::SETGT:
   case ISD::SETLE:
   case ISD::SETUGT:
   case ISD::SETULE:

llvm/test/CodeGen/RISCV/rv32zbt.ll

; RV32ZBT-NEXT:    ret
   %tobool = icmp sgt i32 %b, 2046
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_sgt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
 ; RV32I-LABEL: cmov_sgt_i32_constant_neg_2049:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a3, 1048575
-; RV32I-NEXT:    addi a3, a3, 2047
-; RV32I-NEXT:    blt a3, a1, .LBB17_2
+; RV32I-NEXT:    li a3, -2048
+; RV32I-NEXT:    bge a1, a3, .LBB17_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB17_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sgt_i32_constant_neg_2049:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, -2048
; RV32ZBT-NEXT:    ret
   %tobool = icmp sge i32 %b, 2047
   %cond = select i1 %tobool, i32 %a, i32 %c
   ret i32 %cond
 }
 
 define i32 @cmov_sge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
 ; RV32I-LABEL: cmov_sge_i32_constant_neg_2048:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a3, 1048575
-; RV32I-NEXT:    addi a3, a3, 2047
-; RV32I-NEXT:    blt a3, a1, .LBB20_2
+; RV32I-NEXT:    li a3, -2048
+; RV32I-NEXT:    bge a1, a3, .LBB20_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB20_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sge_i32_constant_neg_2048:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    slti a1, a1, -2048

llvm/test/CodeGen/RISCV/rv64zbt.ll

; RV64ZBT-NEXT:    ret
   %tobool = icmp sgt i64 %b, 2046
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 define i64 @cmov_sgt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: cmov_sgt_i64_constant_neg_2049:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a3, 1048575
-; RV64I-NEXT:    addiw a3, a3, 2047
-; RV64I-NEXT:    blt a3, a1, .LBB21_2
+; RV64I-NEXT:    li a3, -2048
+; RV64I-NEXT:    bge a1, a3, .LBB21_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB21_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_sgt_i64_constant_neg_2049:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, -2048
; RV64ZBT-NEXT:    ret
   %tobool = icmp sge i64 %b, 2047
   %cond = select i1 %tobool, i64 %a, i64 %c
   ret i64 %cond
 }
 
 define i64 @cmov_sge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: cmov_sge_i64_constant_neg_2048:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a3, 1048575
-; RV64I-NEXT:    addiw a3, a3, 2047
-; RV64I-NEXT:    blt a3, a1, .LBB24_2
+; RV64I-NEXT:    li a3, -2048
+; RV64I-NEXT:    bge a1, a3, .LBB24_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB24_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: cmov_sge_i64_constant_neg_2048:
 ; RV64ZBT:       # %bb.0:
 ; RV64ZBT-NEXT:    slti a1, a1, -2048

llvm/test/CodeGen/RISCV/select-cc.ll

 }
 
 declare void @bar(i16 signext)
 
 define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z) {
 ; RV32I-LABEL: select_sge_int16min:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a3, 1048560
-; RV32I-NEXT:    addi a3, a3, -1
-; RV32I-NEXT:    blt a3, a0, .LBB2_2
+; RV32I-NEXT:    bge a0, a3, .LBB2_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:  .LBB2_2:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: select_sge_int16min:
 ; RV32ZBT:       # %bb.0:
 ; RV32ZBT-NEXT:    lui a3, 1048560
 ; RV32ZBT-NEXT:    addi a3, a3, -1
 ; RV32ZBT-NEXT:    slt a0, a3, a0
 ; RV32ZBT-NEXT:    cmov a0, a0, a1, a2
 ; RV32ZBT-NEXT:    ret
 ;
 ; RV64I-LABEL: select_sge_int16min:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 1048560
-; RV64I-NEXT:    addiw a3, a3, -1
-; RV64I-NEXT:    blt a3, a0, .LBB2_2
+; RV64I-NEXT:    bge a0, a3, .LBB2_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
 ; RV64I-NEXT:  .LBB2_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: select_sge_int16min:
 ; RV64ZBT:       # %bb.0:

 ; RV32ZBT-NEXT:    cmov a1, a6, a1, a0
 ; RV32ZBT-NEXT:    cmov a0, a1, a2, a4
 ; RV32ZBT-NEXT:    cmov a1, a1, a3, a5
 ; RV32ZBT-NEXT:    ret
 ;
 ; RV64I-LABEL: select_sge_int32min:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 524288
-; RV64I-NEXT:    addi a3, a3, -1
-; RV64I-NEXT:    blt a3, a0, .LBB3_2
+; RV64I-NEXT:    bge a0, a3, .LBB3_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
 ; RV64I-NEXT:  .LBB3_2:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBT-LABEL: select_sge_int32min:
 ; RV64ZBT:       # %bb.0: