[RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.

[craig.topper]

Summary

When lowering GlobalAddressNodes, we were removing a non-zero offset and
creating a separate ADD.

It already comes out of SelectionDAGBuilder with a separate ADD. The
ADD was being removed by DAGCombiner.

This patch disables the DAG combine so we don't have to reverse it.
Test changes all look to be instruction order changes. Probably due
to different DAG node ordering.

[craig.topper]

clang-format

[reames]

LGTM

[asb]

This introduced some compiler warnings for me, e.g. XlenVT no longer being used.

llvm/lib/Target/RISCV/RISCVISelLowering.h

 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
   bool hasAndNotCompare(SDValue Y) const override;
   bool hasBitTest(SDValue X, SDValue Y) const override;
   bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
       SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
       unsigned OldShiftOpcode, unsigned NewShiftOpcode,
       SelectionDAG &DAG) const override;
   bool shouldSinkOperands(Instruction *I,
                           SmallVectorImpl<Use *> &Ops) const override;
+  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
 
   bool softPromoteHalfType() const override { return true; }
 
   /// Return the register type for a given MVT, ensuring vectors are treated
   /// as a series of gpr sized integers.
   MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
for (auto OpIdx : enumerate(I->operands())) {
     }
 
     Ops.push_back(&Op->getOperandUse(0));
     Ops.push_back(&OpIdx.value());
   }
   return true;
 }
 
+bool
+RISCVTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
+  // In order to maximise the opportunity for common subexpression elimination,
+  // keep a separate ADD node for the global address offset instead of folding
+  // it in the global address node. Later peephole optimisations may choose to
+  // fold it back in when profitable.
+  return false;
+}
+
 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                        bool ForCodeSize) const {
   // FIXME: Change to Zfhmin once f16 becomes a legal type with Zfhmin.
   if (VT == MVT::f16 && !Subtarget.hasStdExtZfh())
     return false;
   if (VT == MVT::f32 && !Subtarget.hasStdExtF())
     return false;
   if (VT == MVT::f64 && !Subtarget.hasStdExtD())

 template SDValue RISCVTargetLowering::getAddr<JumpTableSDNode>(
     JumpTableSDNode *N, SelectionDAG &DAG, bool IsLocal) const;
 
 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
                                                 SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT Ty = Op.getValueType();
   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
-  int64_t Offset = N->getOffset();
+  assert(N->getOffset() == 0 && "unexpected offset in global node");
   MVT XLenVT = Subtarget.getXLenVT();
 
   const GlobalValue *GV = N->getGlobal();
   bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
-  SDValue Addr = getAddr(N, DAG, IsLocal);
-
-  // In order to maximise the opportunity for common subexpression elimination,
-  // emit a separate ADD node for the global address offset instead of folding
-  // it in the global address node. Later peephole optimisations may choose to
-  // fold it back in when profitable.
-  if (Offset != 0)
-    return DAG.getNode(ISD::ADD, DL, Ty, Addr,
-                       DAG.getConstant(Offset, DL, XLenVT));
-  return Addr;
+  return getAddr(N, DAG, IsLocal);
 }
 
 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
                                                SelectionDAG &DAG) const {
   BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
 
   return getAddr(N, DAG);
 }
SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
   return LowerCallTo(CLI).first;
 }
 
 SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
                                                    SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT Ty = Op.getValueType();
   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
-  int64_t Offset = N->getOffset();
+  assert(N->getOffset() == 0 && "unexpected offset in global node");
   MVT XLenVT = Subtarget.getXLenVT();
 
   TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal());
 
   if (DAG.getMachineFunction().getFunction().getCallingConv() ==
       CallingConv::GHC)
     report_fatal_error("In GHC calling convention TLS is not supported");
 
   SDValue Addr;
   switch (Model) {
   case TLSModel::LocalExec:
     Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/false);
     break;
   case TLSModel::InitialExec:
     Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/true);
     break;
   case TLSModel::LocalDynamic:
   case TLSModel::GeneralDynamic:
     Addr = getDynamicTLSAddr(N, DAG);
     break;
   }
 
-  // In order to maximise the opportunity for common subexpression elimination,
-  // emit a separate ADD node for the global address offset instead of folding
-  // it in the global address node. Later peephole optimisations may choose to
-  // fold it back in when profitable.
-  if (Offset != 0)
-    return DAG.getNode(ISD::ADD, DL, Ty, Addr,
-                       DAG.getConstant(Offset, DL, XLenVT));
   return Addr;
 }
 
 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   SDValue CondV = Op.getOperand(0);
   SDValue TrueV = Op.getOperand(1);
   SDValue FalseV = Op.getOperand(2);
   SDLoc DL(Op);

llvm/test/CodeGen/RISCV/double-mem.ll

 @G = dso_local global double 0.0
 
 define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fld_fsd_global:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    fadd.d fa0, fa0, fa1
 ; RV32IFD-NEXT:    lui a0, %hi(G)
 ; RV32IFD-NEXT:    fld ft0, %lo(G)(a0)
+; RV32IFD-NEXT:    addi a1, a0, %lo(G)
 ; RV32IFD-NEXT:    fsd fa0, %lo(G)(a0)
-; RV32IFD-NEXT:    addi a0, a0, %lo(G)
-; RV32IFD-NEXT:    fld ft0, 72(a0)
-; RV32IFD-NEXT:    fsd fa0, 72(a0)
+; RV32IFD-NEXT:    fld ft0, 72(a1)
+; RV32IFD-NEXT:    fsd fa0, 72(a1)
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fld_fsd_global:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fadd.d fa0, fa0, fa1
 ; RV64IFD-NEXT:    lui a0, %hi(G)
 ; RV64IFD-NEXT:    fld ft0, %lo(G)(a0)
+; RV64IFD-NEXT:    addi a1, a0, %lo(G)
 ; RV64IFD-NEXT:    fsd fa0, %lo(G)(a0)
-; RV64IFD-NEXT:    addi a0, a0, %lo(G)
-; RV64IFD-NEXT:    fld ft0, 72(a0)
-; RV64IFD-NEXT:    fsd fa0, 72(a0)
+; RV64IFD-NEXT:    fld ft0, 72(a1)
+; RV64IFD-NEXT:    fsd fa0, 72(a1)
 ; RV64IFD-NEXT:    ret
 ; Use %a and %b in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
   %1 = fadd double %a, %b
   %2 = load volatile double, double* @G
   store double %1, double* @G
   %3 = getelementptr double, double* @G, i32 9
   %4 = load volatile double, double* %3

llvm/test/CodeGen/RISCV/float-mem.ll

 define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
 ; Use %a and %b in an FP op to ensure floating point registers are used, even
 ; for the soft float ABI
 ; RV32IF-LABEL: flw_fsw_global:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fadd.s fa0, fa0, fa1
 ; RV32IF-NEXT:    lui a0, %hi(G)
 ; RV32IF-NEXT:    flw ft0, %lo(G)(a0)
+; RV32IF-NEXT:    addi a1, a0, %lo(G)
 ; RV32IF-NEXT:    fsw fa0, %lo(G)(a0)
-; RV32IF-NEXT:    addi a0, a0, %lo(G)
-; RV32IF-NEXT:    flw ft0, 36(a0)
-; RV32IF-NEXT:    fsw fa0, 36(a0)
+; RV32IF-NEXT:    flw ft0, 36(a1)
+; RV32IF-NEXT:    fsw fa0, 36(a1)
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: flw_fsw_global:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fadd.s fa0, fa0, fa1
 ; RV64IF-NEXT:    lui a0, %hi(G)
 ; RV64IF-NEXT:    flw ft0, %lo(G)(a0)
+; RV64IF-NEXT:    addi a1, a0, %lo(G)
 ; RV64IF-NEXT:    fsw fa0, %lo(G)(a0)
-; RV64IF-NEXT:    addi a0, a0, %lo(G)
-; RV64IF-NEXT:    flw ft0, 36(a0)
-; RV64IF-NEXT:    fsw fa0, 36(a0)
+; RV64IF-NEXT:    flw ft0, 36(a1)
+; RV64IF-NEXT:    fsw fa0, 36(a1)
 ; RV64IF-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = load volatile float, float* @G
   store float %1, float* @G
   %3 = getelementptr float, float* @G, i32 9
   %4 = load volatile float, float* %3
   store float %1, float* %3
   ret float %1

llvm/test/CodeGen/RISCV/half-mem.ll

 define half @flh_fsh_global(half %a, half %b) nounwind {
 ; Use %a and %b in an FP op to ensure half precision floating point registers
 ; are used, even for the soft half ABI
 ; RV32IZFH-LABEL: flh_fsh_global:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fadd.h fa0, fa0, fa1
 ; RV32IZFH-NEXT:    lui a0, %hi(G)
 ; RV32IZFH-NEXT:    flh ft0, %lo(G)(a0)
+; RV32IZFH-NEXT:    addi a1, a0, %lo(G)
 ; RV32IZFH-NEXT:    fsh fa0, %lo(G)(a0)
-; RV32IZFH-NEXT:    addi a0, a0, %lo(G)
-; RV32IZFH-NEXT:    flh ft0, 18(a0)
-; RV32IZFH-NEXT:    fsh fa0, 18(a0)
+; RV32IZFH-NEXT:    flh ft0, 18(a1)
+; RV32IZFH-NEXT:    fsh fa0, 18(a1)
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: flh_fsh_global:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fadd.h fa0, fa0, fa1
 ; RV64IZFH-NEXT:    lui a0, %hi(G)
 ; RV64IZFH-NEXT:    flh ft0, %lo(G)(a0)
+; RV64IZFH-NEXT:    addi a1, a0, %lo(G)
 ; RV64IZFH-NEXT:    fsh fa0, %lo(G)(a0)
-; RV64IZFH-NEXT:    addi a0, a0, %lo(G)
-; RV64IZFH-NEXT:    flh ft0, 18(a0)
-; RV64IZFH-NEXT:    fsh fa0, 18(a0)
+; RV64IZFH-NEXT:    flh ft0, 18(a1)
+; RV64IZFH-NEXT:    fsh fa0, 18(a1)
 ; RV64IZFH-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = load volatile half, half* @G
   store half %1, half* @G
   %3 = getelementptr half, half* @G, i32 9
   %4 = load volatile half, half* %3
   store half %1, half* %3
   ret half %1

llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

 ; RV32-LABEL: big_offset_one_use:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    lui a0, %hi(s+16572)
 ; RV32-NEXT:    addi a0, a0, %lo(s+16572)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: big_offset_one_use:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    lui a0, 4
-; RV64-NEXT:    addiw a0, a0, 188
-; RV64-NEXT:    lui a1, %hi(s)
-; RV64-NEXT:    addi a1, a1, %lo(s)
-; RV64-NEXT:    add a0, a1, a0
+; RV64-NEXT:    lui a0, %hi(s)
+; RV64-NEXT:    addi a0, a0, %lo(s)
+; RV64-NEXT:    lui a1, 4
+; RV64-NEXT:    addiw a1, a1, 188
+; RV64-NEXT:    add a0, a0, a1
 ; RV64-NEXT:    ret
 entry:
   ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 5)
 }
 
 define dso_local i32* @small_offset_one_use() local_unnamed_addr nounwind {
 ; CHECK-LABEL: small_offset_one_use:
 ; CHECK:       # %bb.0: # %entry

llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll

 ; RV32-NEXT:    lui a3, 2
 ; RV32-NEXT:    blt a3, a1, .LBB0_3
 ; RV32-NEXT:  # %bb.1: # %bb.preheader
 ; RV32-NEXT:    lui a2, %hi(flags2)
 ; RV32-NEXT:    addi a2, a2, %lo(flags2)
 ; RV32-NEXT:    addi a3, a3, 1
 ; RV32-NEXT:  .LBB0_2: # %bb
 ; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32-NEXT:    add a4, a1, a2
+; RV32-NEXT:    add a4, a2, a1
 ; RV32-NEXT:    add a1, a1, a0
 ; RV32-NEXT:    sb zero, 0(a4)
 ; RV32-NEXT:    blt a1, a3, .LBB0_2
 ; RV32-NEXT:  .LBB0_3: # %return
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    slliw a1, a0, 1
 ; RV64-NEXT:    lui a4, 2
 ; RV64-NEXT:    blt a4, a1, .LBB0_3
 ; RV64-NEXT:  # %bb.1: # %bb.preheader
 ; RV64-NEXT:    li a2, 0
 ; RV64-NEXT:    lui a3, %hi(flags2)
 ; RV64-NEXT:    addi a3, a3, %lo(flags2)
 ; RV64-NEXT:    addiw a4, a4, 1
 ; RV64-NEXT:  .LBB0_2: # %bb
 ; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64-NEXT:    mulw a5, a2, a0
 ; RV64-NEXT:    addw a5, a5, a1
 ; RV64-NEXT:    slli a6, a5, 32
 ; RV64-NEXT:    srli a6, a6, 32
-; RV64-NEXT:    add a6, a6, a3
+; RV64-NEXT:    add a6, a3, a6
 ; RV64-NEXT:    sb zero, 0(a6)
 ; RV64-NEXT:    addw a5, a5, a0
 ; RV64-NEXT:    addiw a2, a2, 1
 ; RV64-NEXT:    blt a5, a4, .LBB0_2
 ; RV64-NEXT:  .LBB0_3: # %return
 ; RV64-NEXT:    ret
 entry:
   %k_addr.012 = shl i32 %i, 1

llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll

 ; RV32-NEXT:  .LBB0_3: # %return
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    blez a1, .LBB0_3
 ; RV64-NEXT:  # %bb.1: # %cond_true.preheader
 ; RV64-NEXT:    li a4, 0
+; RV64-NEXT:    slli a0, a0, 6
 ; RV64-NEXT:    lui a2, %hi(A)
 ; RV64-NEXT:    addi a2, a2, %lo(A)
-; RV64-NEXT:    slli a0, a0, 6
-; RV64-NEXT:    add a0, a0, a2
+; RV64-NEXT:    add a0, a2, a0
 ; RV64-NEXT:    li a2, 4
 ; RV64-NEXT:    li a3, 5
 ; RV64-NEXT:  .LBB0_2: # %cond_true
 ; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64-NEXT:    addiw a5, a4, 1
 ; RV64-NEXT:    slli a6, a5, 2
 ; RV64-NEXT:    add a6, a0, a6
 ; RV64-NEXT:    sw a2, 0(a6)

llvm/test/CodeGen/RISCV/mem.ll

 ; Check load and store to a global
 @G = dso_local global i32 0
 
 define dso_local i32 @lw_sw_global(i32 %a) nounwind {
 ; RV32I-LABEL: lw_sw_global:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, %hi(G)
 ; RV32I-NEXT:    lw a1, %lo(G)(a2)
+; RV32I-NEXT:    addi a3, a2, %lo(G)
 ; RV32I-NEXT:    sw a0, %lo(G)(a2)
-; RV32I-NEXT:    addi a2, a2, %lo(G)
-; RV32I-NEXT:    lw a3, 36(a2)
-; RV32I-NEXT:    sw a0, 36(a2)
+; RV32I-NEXT:    lw a2, 36(a3)
+; RV32I-NEXT:    sw a0, 36(a3)
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    ret
   %1 = load volatile i32, i32* @G
   store i32 %a, i32* @G
   %2 = getelementptr i32, i32* @G, i32 9
   %3 = load volatile i32, i32* %2
   store i32 %a, i32* %2
   ret i32 %1

llvm/test/CodeGen/RISCV/mem64.ll

 ; Check load and store to a global
 @G = dso_local global i64 0
 
 define dso_local i64 @ld_sd_global(i64 %a) nounwind {
 ; RV64I-LABEL: ld_sd_global:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a2, %hi(G)
 ; RV64I-NEXT:    ld a1, %lo(G)(a2)
+; RV64I-NEXT:    addi a3, a2, %lo(G)
 ; RV64I-NEXT:    sd a0, %lo(G)(a2)
-; RV64I-NEXT:    addi a2, a2, %lo(G)
-; RV64I-NEXT:    ld a3, 72(a2)
-; RV64I-NEXT:    sd a0, 72(a2)
+; RV64I-NEXT:    ld a2, 72(a3)
+; RV64I-NEXT:    sd a0, 72(a3)
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
   %1 = load volatile i64, i64* @G
   store i64 %a, i64* @G
   %2 = getelementptr i64, i64* @G, i64 9
   %3 = load volatile i64, i64* %2
   store i64 %a, i64* %2
   ret i64 %1

llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 
 ; TODO: lbu and lhu should be selected to avoid the unnecessary masking.
 
 @bytes = dso_local global [5 x i8] zeroinitializer, align 1
 
 define dso_local i32 @test_zext_i8() nounwind {
 ; RV32I-LABEL: test_zext_i8:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(bytes)
-; RV32I-NEXT:    lbu a1, %lo(bytes)(a0)
-; RV32I-NEXT:    addi a0, a0, %lo(bytes)
-; RV32I-NEXT:    lbu a0, 1(a0)
-; RV32I-NEXT:    xori a1, a1, 136
-; RV32I-NEXT:    xori a0, a0, 7
-; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    addi a1, a0, %lo(bytes)
+; RV32I-NEXT:    lbu a0, %lo(bytes)(a0)
+; RV32I-NEXT:    lbu a1, 1(a1)
+; RV32I-NEXT:    xori a0, a0, 136
+; RV32I-NEXT:    xori a1, a1, 7
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    beqz a0, .LBB0_2
 ; RV32I-NEXT:  # %bb.1: # %if.then
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:  .LBB0_2: # %if.end
 ; RV32I-NEXT:    ret
 entry:
   %0 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 0), align 1
   %cmp = icmp eq i8 %0, -120

 }
 
 @shorts = dso_local global [5 x i16] zeroinitializer, align 2
 
 define dso_local i32 @test_zext_i16() nounwind {
 ; RV32I-LABEL: test_zext_i16:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(shorts)
-; RV32I-NEXT:    lhu a1, %lo(shorts)(a0)
-; RV32I-NEXT:    addi a0, a0, %lo(shorts)
-; RV32I-NEXT:    lhu a0, 2(a0)
+; RV32I-NEXT:    addi a1, a0, %lo(shorts)
+; RV32I-NEXT:    lhu a0, %lo(shorts)(a0)
+; RV32I-NEXT:    lhu a1, 2(a1)
 ; RV32I-NEXT:    lui a2, 16
 ; RV32I-NEXT:    addi a2, a2, -120
-; RV32I-NEXT:    xor a1, a1, a2
-; RV32I-NEXT:    xori a0, a0, 7
-; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    xor a0, a0, a2
+; RV32I-NEXT:    xori a1, a1, 7
+; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    beqz a0, .LBB1_2
 ; RV32I-NEXT:  # %bb.1: # %if.then
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:  .LBB1_2: # %if.end
 ; RV32I-NEXT:    ret
 entry:
   %0 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 0), align 2
   %cmp = icmp eq i16 %0, -120