[RISCV] Use default promotion for (i32 (shl 1, X)) on RV64 when Zbs is enabled.

[craig.topper]

Summary

This improves opportunities to use bset/bclr/binv. Unfortunately,
there are no W versions of these instrcutions so this isn't always
a clear win. If we use SLLW we get free sign extend and shift masking,
but need to put a 1 in a register and can't remove an or/xor. If
we use bset/bclr/binv we remove the immediate materializationg and
logic op, but might need a mask on the shift amount and sext.w.

[luismarques]

LGTM.

[Miss_Grape]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

6827

clang-format

[Miss_Grape]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

6827

sorry，I didn't look carefully

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case ISD::SUB:
     Results.push_back(customLegalizeToWOpWithSExt(N, DAG));
     break;
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
     assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
            "Unexpected custom legalisation");
     if (N->getOperand(1).getOpcode() != ISD::Constant) {
+      // If we can use a BSET instruction, allow default promotion to apply.
+      if (N->getOpcode() == ISD::SHL && Subtarget.hasStdExtZbs() &&
+          isOneConstant(N->getOperand(0)))
+        break;
       Results.push_back(customLegalizeToWOp(N, DAG));
       break;
     }
 
     // Custom legalize ISD::SHL by placing a SIGN_EXTEND_INREG after. This is
     // similar to customLegalizeToWOpWithSExt, but we must zero_extend the
     // shift amount.
     if (N->getOpcode() == ISD::SHL) {

llvm/test/CodeGen/RISCV/rv64zbs.ll

 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bclr_i32:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a2, 1
-; RV64ZBS-NEXT:    sllw a1, a2, a1
-; RV64ZBS-NEXT:    not a1, a1
-; RV64ZBS-NEXT:    and a0, a1, a0
+; RV64ZBS-NEXT:    andi a1, a1, 31
+; RV64ZBS-NEXT:    bclr a0, a0, a1
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %neg = xor i32 %shl, -1
   %and1 = and i32 %neg, %a
   ret i32 %and1
 }
 
 define signext i32 @bclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: bclr_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bclr_i32_no_mask:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a2, 1
-; RV64ZBS-NEXT:    sllw a1, a2, a1
-; RV64ZBS-NEXT:    not a1, a1
-; RV64ZBS-NEXT:    and a0, a1, a0
+; RV64ZBS-NEXT:    bclr a0, a0, a1
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %shl = shl i32 1, %b
   %neg = xor i32 %shl, -1
   %and1 = and i32 %neg, %a
   ret i32 %and1
 }
 
 define signext i32 @bclr_i32_load(i32* %p, i32 signext %b) nounwind {
 ; RV64I-LABEL: bclr_i32_load:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bclr_i32_load:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lw a0, 0(a0)
-; RV64ZBS-NEXT:    li a2, 1
-; RV64ZBS-NEXT:    sllw a1, a2, a1
-; RV64ZBS-NEXT:    not a1, a1
-; RV64ZBS-NEXT:    and a0, a1, a0
+; RV64ZBS-NEXT:    bclr a0, a0, a1
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %a = load i32, i32* %p
   %shl = shl i32 1, %b
   %neg = xor i32 %shl, -1
   %and1 = and i32 %neg, %a
   ret i32 %and1
 }
 

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bset_i32:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a2, 1
-; RV64ZBS-NEXT:    sllw a1, a2, a1
-; RV64ZBS-NEXT:    or a0, a1, a0
+; RV64ZBS-NEXT:    andi a1, a1, 31
+; RV64ZBS-NEXT:    bset a0, a0, a1
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %or = or i32 %shl, %a
   ret i32 %or
 }
 
 define signext i32 @bset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: bset_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bset_i32_no_mask:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a2, 1
-; RV64ZBS-NEXT:    sllw a1, a2, a1
-; RV64ZBS-NEXT:    or a0, a1, a0
+; RV64ZBS-NEXT:    bset a0, a0, a1
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %shl = shl i32 1, %b
   %or = or i32 %shl, %a
   ret i32 %or
 }
 
 define signext i32 @bset_i32_load(i32* %p, i32 signext %b) nounwind {
 ; RV64I-LABEL: bset_i32_load:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bset_i32_load:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lw a0, 0(a0)
-; RV64ZBS-NEXT:    li a2, 1
-; RV64ZBS-NEXT:    sllw a1, a2, a1
-; RV64ZBS-NEXT:    or a0, a1, a0
+; RV64ZBS-NEXT:    bset a0, a0, a1
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %a = load i32, i32* %p
   %shl = shl i32 1, %b
   %or = or i32 %shl, %a
   ret i32 %or
 }
 
 ; We can use bsetw for 1 << x by setting the first source to zero.
 define signext i32 @bset_i32_zero(i32 signext %a) nounwind {
 ; RV64I-LABEL: bset_i32_zero:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 1
 ; RV64I-NEXT:    sllw a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bset_i32_zero:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a1, 1
-; RV64ZBS-NEXT:    sllw a0, a1, a0
+; RV64ZBS-NEXT:    bset a0, zero, a0
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %shl = shl i32 1, %a
   ret i32 %shl
 }
 
 define i64 @bset_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: bset_i64:
 ; RV64I:       # %bb.0:

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: binv_i32:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a2, 1
-; RV64ZBS-NEXT:    sllw a1, a2, a1
-; RV64ZBS-NEXT:    xor a0, a1, a0
+; RV64ZBS-NEXT:    andi a1, a1, 31
+; RV64ZBS-NEXT:    binv a0, a0, a1
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %xor = xor i32 %shl, %a
   ret i32 %xor
 }
 
 define signext i32 @binv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: binv_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: binv_i32_no_mask:
 ; RV64ZBS:       # %bb.0:
-; RV64ZBS-NEXT:    li a2, 1
-; RV64ZBS-NEXT:    sllw a1, a2, a1
-; RV64ZBS-NEXT:    xor a0, a1, a0
+; RV64ZBS-NEXT:    binv a0, a0, a1
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %shl = shl i32 1, %b
   %xor = xor i32 %shl, %a
   ret i32 %xor
 }
 
 define signext i32 @binv_i32_load(i32* %p, i32 signext %b) nounwind {
 ; RV64I-LABEL: binv_i32_load:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    li a2, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: binv_i32_load:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    lw a0, 0(a0)
-; RV64ZBS-NEXT:    li a2, 1
-; RV64ZBS-NEXT:    sllw a1, a2, a1
-; RV64ZBS-NEXT:    xor a0, a1, a0
+; RV64ZBS-NEXT:    binv a0, a0, a1
+; RV64ZBS-NEXT:    sext.w a0, a0
 ; RV64ZBS-NEXT:    ret
   %a = load i32, i32* %p
   %shl = shl i32 1, %b
   %xor = xor i32 %shl, %a
   ret i32 %xor
 }
 
 define i64 @binv_i64(i64 %a, i64 %b) nounwind {