[RISCV] Pre-RA expand pseudos pass

[luismarques]

Summary

As discussed before, we aren't optimizing the LLA+Load/Stores (i.e. AUIPC+ADDI+Load/Stores) instruction sequences that we get with medany because:

• the pseudo instruction expansion pass runs late (in premit2, i.e. post-ra);
• the pass to merge the offset of address calculations into the offset of load/stores runs pre-ra, in SSA form.

Ideally, we want to expand the LLA pseudo instruction earlier and extend the offset folding pass to handle the AUIPC case. This patch implements that earlier expansion.

Just doing the same expansion we were doing but earlier, with virtual registers, runs into problems. It's easy for optimizations to separate the AUIPC instruction from the label of the BB that should point to the AUIPC.

Earlier passes don't know about LabelMustBeEmitted. Originally I solved that by making that flag also imply AddressTaken. But creating BBs earlier was messing with various optimizations, so I ended up going for an implementation based on createNamedTempSymbol + setPreInstrSymbol.

[luismarques]

Ping?

[HsiangKai]

llvm/include/llvm/CodeGen/MachineInstr.h

1212 ↗

(On Diff #421024)

Is it enough to only add checking of getPreInstrSymbol()?

[HsiangKai]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

389

redundant?

[luismarques]

llvm/include/llvm/CodeGen/MachineInstr.h

1212 ↗

(On Diff #421024)

What do you mean, enough for what? (This patch also checks getPostInstrSymbol()).
In my testing that was enough to ensure that the label always pointed to the correct upper instruction, but feedback about this is welcome.

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

389

Thanks. I'll remove it in the next revision.

[HsiangKai]

llvm/include/llvm/CodeGen/MachineInstr.h

1212 ↗

(On Diff #421024)

Just curious why checking getPostInstrSymbol() here. There is no setPostInstrSymbol() in this patch.

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

97–98

Do we still need to handle PseudoLLA in RISCVExpandPseudo?

[luismarques]

llvm/include/llvm/CodeGen/MachineInstr.h

1212 ↗

(On Diff #421024)

It was just for regularity. My reasoning was that if some_label: INSTR; is a position then INSTR; some_label: also is (assuming the label is attached to the INSTR), so this change made sense for both. But it's not necessary for *this* particular patch. Thanks for checking that oddity :)

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

97–98

Possibly not. I'll have to more carefully check if there aren't passes that can reintroduce those instructions. I wonder if it just isn't safer to leave it for now, anyway? In any case, if this patch is accepted and proves stable then it might make sense to eventually move more/all of these expansions to Pre-RA, as that unlocks various optimizations. Sam Elliot had explored that possibility some time ago but he had run into the issue of the instructions and the labels getting out of sync. That seems solved now with my isPosition change.

[HsiangKai]

llvm/include/llvm/CodeGen/MachineInstr.h

1212 ↗

(On Diff #421024)

To change the condition of isPosition() will have side effects in other passes. One example is instruction scheduling. isPosition() is one of the condition to decide region boundaries for instruction scheduling. Refer to https://github.com/llvm/llvm-project/blob/be5c15c7aee1ef4964c88031555ed6b0f59ebc23/llvm/lib/CodeGen/TargetInstrInfo.cpp#L1025

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

143

Here is an example that to change isPosition() will change instruction scheduling behavior. After the patch, auipc will become the boundary of scheduling regions. fmv.w.x will become the only instruction in its own region. If there are multiple latencies in load-to-use in the microarchitecture, fmv.w.x will not be able to fill the latencies after flw. It will have negative impact on the performance.

[StephenFan]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

442

Using createTempSymbol to create a symbol will cause the object code's string table to have an empty name for the symbol. Maybe you could use the MF.getPICBaseSymbol() function to create the PIC base symbol. It can create the function local symbol by using the unique function id.

[StephenFan]

This comment has been deleted.

llvm/include/llvm/CodeGen/MachineInstr.h

1212 ↗

(On Diff #421024)

What do you mean, enough for what? (This patch also checks getPostInstrSymbol()).
In my testing that was enough to ensure that the label always pointed to the correct upper instruction, but feedback about this is welcome.

I'm curious about by setPreInstrSymbol, the compiler still can't ensure that the label always pointed
to the correct upper instruction? I think after setPreInstrSymbol, the AsmPrinter will always emit the symbol label before this instruction.

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

446

Because we have set a pre-instr symbol and this symbol is unique, I think we need to make the AUIPC instruction not duplicable. If auipc instruction were duplicated, the unique symbol would also have multiple definitions. It is in conflict with the symbol is unique.

[luismarques]

Don't mess with isPosition. Create named temp labels. Remove cruft.

[luismarques]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

442

I'll look into this more carefully later. I thought (but didn't verify) that createNamedTempSymbol would emit the symbol like you wanted, even if that symbol wasn't then function-local. But then I looked at object files built with the original patch and they seemed already have the .LPCRelHi0 etc in .symtab. So I'm not sure I follow your point. As I said, I need to look into this more carefully.

446

That makes sense. It wasn't immediately obvious how to dynamically set the not duplicable flag per instruction instance, so I'll handle this one later. There seemed to be fewer passes that checked the isNotDuplicable property than I would expect, though.

[luismarques]

llvm/include/llvm/CodeGen/MachineInstr.h

1212 ↗

(On Diff #421024)

I'm curious about by setPreInstrSymbol, the compiler still can't ensure that the label always pointed
to the correct upper instruction? I think after setPreInstrSymbol, the AsmPrinter will always emit the symbol label before this instruction.

Indeed. There was an issue where the label for the upper instruction was being removed, and it was seemingly caused by the branch folder pass. I think I misinterpreted what was going on there, possibly because I was originally using a different implementation and got confused. When I looked again into that it seemed that the invalid transformation made sense if two AUIPCs were actually the same. They were, except for the pre and post-instruction symbols. Sure enough, extending the MI comparison to check for the pre- and post-instruction symbols solved the issue without messing with the isPosition predicate. Thanks.

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

439

As a quick non-technical comment, if we're going to give names to these symbols, can we please use .Lpcrel_hiN to match what you get from expanding the pseudos in RISCVAsmParser rather than a different spelling of the same thing?

[jrtc27]

• Although I haven't run into that problem, I think it's still possible for an ADDI to become out of range of the AUIPC it refers to, if other passes move them too far apart. For branches we have the branch relaxation pass to solve essentially the same problem. Are we going to need a similar pass for AUIPC/ADDI? Or can we prevent this from happening?

This doesn't make sense to me? The immediate for the ADDI is unused in the .o file, and in the linked file it's just the low 12 bits of the 32-bit offset of the symbol from the AUIPC. Where you put the ADDI never matters, so long as it's in the same input section as the AUIPC its relocation refers to.

llvm/lib/CodeGen/MachineInstr.cpp

634

This is overly strict in the specific case being addressed by this patch:

1: auipc a0, %pcrel_hi(foo)
   lw a1, %pcrel_lo(1b)(a0)
   addi a1, a1, 1
2: auipc a0, %pcrel_hi(foo)
   sw a1, %pcrel_lo(2b)(a0)

can legally be optimised to

1: auipc a0, %pcrel_hi(foo)
   lw a1, %pcrel_lo(1b)(a0)
   addi a1, a1, 1
   sw a1, %pcrel_lo(1b)(a0)

[luismarques]

In D123264#3459427, @jrtc27 wrote:

This doesn't make sense to me?

Right, that was silly, I was confused. I'll remove it from the summary.

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

439

Yes, I'll update it in the next revision.

[luismarques]

llvm/lib/CodeGen/MachineInstr.cpp

634

That is a generic MachineInstr comparison function. We don't make use of it to reason about these address generation instructions sequences, it's here only to tighten the checks for other passes (namely the branch folder pass, possibly others) that would break once we start using pre-instruction symbols. So I guess it's fine as it? It's also not immediately obvious to me in which ways we could be more clever about the comparison and still keep it conservative enough to be target and "context" independent.

[craig.topper]

llvm/test/CodeGen/RISCV/O3-pipeline.ll

102

Can we say that the new pass preserves the CFG? Will that prevent this change?

[luismarques]

• Rebase
• Apply suggestion to rename label name
• Set AnalysisUsage CFG preserved

I think the only big thing missing is that the instructions with labels must be marked as non-copyable.

[luismarques]

Make instructions with pre- and post-instructions symbols not duplicable

[luismarques]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

442

Using createTempSymbol to create a symbol will cause the object code's string table to have an empty name for the symbol.

That doesn't seem to be the case.

[luismarques]

Ping.

[luismarques]

Ping.

[craig.topper]

LGTM

[jrtc27]

LA should follow LLA; at least the LA-as-LLA expansion should follow the same behaviour as they are supposed to be equivalent for non-fPIC.

[jrtc27]

(though I would prefer _all_ LA-like instructions be expanded at the same point, not just the ones where you can fold the immediate in; both the -fPIC LA and the TLS ones would ideally be expanded at the same time as LLA)

[luismarques]

• Move the other LA-like instructions to the pre-ra expansion pass
• Merge back the mir-target-flags.ll test. The splitting done in previous versions of the patch is no longer needed as the pre-instruction symbol printing now seems to be implemented.

[craig.topper]

In D123264#3682868, @jrtc27 wrote:

LA should follow LLA; at least the LA-as-LLA expansion should follow the same behaviour as they are supposed to be equivalent for non-fPIC.

Does the compiler ever emit an LA-as-LLA? The branch in RISCVExpandPseudoInst is untested according to the coverage report https://lab.llvm.org/coverage/coverage-reports/coverage/Users/buildslave/jenkins/workspace/coverage/llvm-project/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp.html#L217

[craig.topper]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

466

Should preserve the memoperand the call may have had if this is a load? The original expansion was late in the pipe so probably didn't matter. That may be different now that its earlier.

[luismarques]

In D123264#3688467, @craig.topper wrote:

In D123264#3682868, @jrtc27 wrote:

LA should follow LLA; at least the LA-as-LLA expansion should follow the same behaviour as they are supposed to be equivalent for non-fPIC.

Does the compiler ever emit an LA-as-LLA? The branch in RISCVExpandPseudoInst is untested according to the coverage report https://lab.llvm.org/coverage/coverage-reports/coverage/Users/buildslave/jenkins/workspace/coverage/llvm-project/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp.html#L217

In D123264#3688467, @craig.topper wrote:

In D123264#3682868, @jrtc27 wrote:

LA should follow LLA; at least the LA-as-LLA expansion should follow the same behaviour as they are supposed to be equivalent for non-fPIC.

Does the compiler ever emit an LA-as-LLA? The branch in RISCVExpandPseudoInst is untested according to the coverage report https://lab.llvm.org/coverage/coverage-reports/coverage/Users/buildslave/jenkins/workspace/coverage/llvm-project/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp.html#L217

I think that branch was already dead when it was originally added: https://reviews.llvm.org/D55303
RISCV::PseudoLA was only emitted inside an if (isPositionIndependent()), and the dead branch is the negation of that condition.
Should we remove the dead branch in a separate patch?

[luismarques]

• Remove the unused RISCVExpandPseudo::expandAuipcInstPair
• Delete the dead branch from the RISCVPreRAExpandPseudo::expandAuipcInstPair
• Try to address the feedback regarding preserving the memoperands
• Update mir-target-flags.ll due to reorderings caused by the memoperands

[luismarques]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

466

Does the change below address this feedback?

llvm/test/CodeGen/RISCV/mir-target-flags.ll

26–27

I tried to add flags to llc to disable any scheduling reorderings but failed to preserve the original order. Any suggestions?

[luismarques]

• Add missing initialization/registration of the new pass
• Update the mir-target-flags.ll to make it insensitive to the machine-scheduler reorderings that happened once the patch started to preserve the memoperands.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

471

nit: drop curly braces

[leonardchan]

Hi I think this patch led to the following ICEs seen on our windows builders (https://luci-milo.appspot.com/ui/p/fuchsia/builders/toolchain.ci/clang-windows-x64/b8807088318544910865/overview):

96/151] Building C object CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj
FAILED: CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj 
C:\b\s\w\ir\x\w\staging\llvm_build\.\bin\clang.exe -DVISIBILITY_HIDDEN  --target=riscv64-unknown-fuchsia -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/sync/include -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/fdio/include   -DCOMPILER_RT_HAS_FLOAT16 -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -o CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj   -c C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c
Unhandled encodeInstruction length!
UNREACHABLE executed at C:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV\MCTargetDesc\RISCVMCCodeEmitter.cpp:209!
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
Stack dump:
0.	Program arguments: C:\\b\\s\\w\\ir\\x\\w\\staging\\llvm_build\\.\\bin\\clang.exe -DVISIBILITY_HIDDEN --target=riscv64-unknown-fuchsia -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/sync/include -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/fdio/include -DCOMPILER_RT_HAS_FLOAT16 -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -o CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj -c C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c
1.	<eof> parser at end of file
2.	Code generation
3.	Running pass 'Function Pass Manager' on module 'C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c'.
4.	Running pass 'RISCV Assembly Printer' on function '@__floatdidf'
Exception Code: 0xC000001D
 #0 0x00007ff6a2ebbcb6 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x6dbcb6)
 #1 0x00007ff6a6d19bcb (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4539bcb)
 #2 0x00007ff6a6d0f0d0 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x452f0d0)
 #3 0x00007ff6a2e7e175 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x69e175)
 #4 0x00007ff6a374a155 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0xf6a155)
 #5 0x00007ff6a2c350aa (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4550aa)
 #6 0x00007ff6a3b6669c (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x138669c)
 #7 0x00007ff6a29197c8 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1397c8)
 #8 0x00007ff6a30cd61e (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x8ed61e)
 #9 0x00007ff6a2918d43 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x138d43)
#10 0x00007ff6a31301ca (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x9501ca)
#11 0x00007ff6a2b000f8 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x3200f8)
#12 0x00007ff6a2b070cc (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x3270cc)
#13 0x00007ff6a2b00829 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x320829)
#14 0x00007ff6a3d77231 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1597231)
#15 0x00007ff6a4176f58 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1996f58)
#16 0x00007ff6a58a9e4e (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x30c9e4e)
#17 0x00007ff6a40d5484 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x18f5484)
#18 0x00007ff6a302fc23 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x84fc23)
#19 0x00007ff6a30c4dc4 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x8e4dc4)
#20 0x00007ff6a27e7abe (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x7abe)
#21 0x00007ff6a27e4848 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4848)
#22 0x00007ff6a3e87636 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x16a7636)
#23 0x00007ff6a2e7ca22 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x69ca22)
#24 0x00007ff6a3e872cf (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x16a72cf)
#25 0x00007ff6a2fed54a (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x80d54a)
#26 0x00007ff6a2fed7af (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x80d7af)
#27 0x00007ff6a3006cfb (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x826cfb)
#28 0x00007ff6a27e418f (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x418f)
#29 0x00007ff6a6cfadf0 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x451adf0)
#30 0x00007ff90b9f7974 (C:\Windows\System32\KERNEL32.DLL+0x17974)
#31 0x00007ff90e73a2f1 (C:\Windows\SYSTEM32\ntdll.dll+0x5a2f1)
clang: error: clang frontend command failed due to signal (use -v to see invocation)
Fuchsia clang version 16.0.0 (https://llvm.googlesource.com/llvm-project 260a64106854986a981e49ed87ee740460a23eb5)
Target: riscv64-unknown-fuchsia
Thread model: posix
InstalledDir: C:\b\s\w\ir\x\w\staging\llvm_build\.\bin
clang: note: diagnostic msg: 
********************

PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang: note: diagnostic msg: C:\b\s\w\ir\x\t\floatdidf-9493d4.c
clang: note: diagnostic msg: C:\b\s\w\ir\x\t\floatdidf-9493d4.sh

clang: note: diagnostic msg: 



********************

Would you be able to send out a fix or revert?

[craig.topper]

In D123264#3691798, @leonardchan wrote:

Hi I think this patch led to the following ICEs seen on our windows builders (https://luci-milo.appspot.com/ui/p/fuchsia/builders/toolchain.ci/clang-windows-x64/b8807088318544910865/overview):

96/151] Building C object CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj
FAILED: CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj 
C:\b\s\w\ir\x\w\staging\llvm_build\.\bin\clang.exe -DVISIBILITY_HIDDEN  --target=riscv64-unknown-fuchsia -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/sync/include -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/fdio/include   -DCOMPILER_RT_HAS_FLOAT16 -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -o CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj   -c C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c
Unhandled encodeInstruction length!
UNREACHABLE executed at C:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV\MCTargetDesc\RISCVMCCodeEmitter.cpp:209!
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
Stack dump:
0.	Program arguments: C:\\b\\s\\w\\ir\\x\\w\\staging\\llvm_build\\.\\bin\\clang.exe -DVISIBILITY_HIDDEN --target=riscv64-unknown-fuchsia -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/sync/include -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/fdio/include -DCOMPILER_RT_HAS_FLOAT16 -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -o CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj -c C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c
1.	<eof> parser at end of file
2.	Code generation
3.	Running pass 'Function Pass Manager' on module 'C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c'.
4.	Running pass 'RISCV Assembly Printer' on function '@__floatdidf'
Exception Code: 0xC000001D
 #0 0x00007ff6a2ebbcb6 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x6dbcb6)
 #1 0x00007ff6a6d19bcb (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4539bcb)
 #2 0x00007ff6a6d0f0d0 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x452f0d0)
 #3 0x00007ff6a2e7e175 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x69e175)
 #4 0x00007ff6a374a155 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0xf6a155)
 #5 0x00007ff6a2c350aa (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4550aa)
 #6 0x00007ff6a3b6669c (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x138669c)
 #7 0x00007ff6a29197c8 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1397c8)
 #8 0x00007ff6a30cd61e (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x8ed61e)
 #9 0x00007ff6a2918d43 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x138d43)
#10 0x00007ff6a31301ca (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x9501ca)
#11 0x00007ff6a2b000f8 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x3200f8)
#12 0x00007ff6a2b070cc (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x3270cc)
#13 0x00007ff6a2b00829 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x320829)
#14 0x00007ff6a3d77231 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1597231)
#15 0x00007ff6a4176f58 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1996f58)
#16 0x00007ff6a58a9e4e (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x30c9e4e)
#17 0x00007ff6a40d5484 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x18f5484)
#18 0x00007ff6a302fc23 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x84fc23)
#19 0x00007ff6a30c4dc4 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x8e4dc4)
#20 0x00007ff6a27e7abe (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x7abe)
#21 0x00007ff6a27e4848 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4848)
#22 0x00007ff6a3e87636 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x16a7636)
#23 0x00007ff6a2e7ca22 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x69ca22)
#24 0x00007ff6a3e872cf (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x16a72cf)
#25 0x00007ff6a2fed54a (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x80d54a)
#26 0x00007ff6a2fed7af (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x80d7af)
#27 0x00007ff6a3006cfb (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x826cfb)
#28 0x00007ff6a27e418f (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x418f)
#29 0x00007ff6a6cfadf0 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x451adf0)
#30 0x00007ff90b9f7974 (C:\Windows\System32\KERNEL32.DLL+0x17974)
#31 0x00007ff90e73a2f1 (C:\Windows\SYSTEM32\ntdll.dll+0x5a2f1)
clang: error: clang frontend command failed due to signal (use -v to see invocation)
Fuchsia clang version 16.0.0 (https://llvm.googlesource.com/llvm-project 260a64106854986a981e49ed87ee740460a23eb5)
Target: riscv64-unknown-fuchsia
Thread model: posix
InstalledDir: C:\b\s\w\ir\x\w\staging\llvm_build\.\bin
clang: note: diagnostic msg: 
********************

PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang: note: diagnostic msg: C:\b\s\w\ir\x\t\floatdidf-9493d4.c
clang: note: diagnostic msg: C:\b\s\w\ir\x\t\floatdidf-9493d4.sh

clang: note: diagnostic msg: 



********************

Would you be able to send out a fix or revert?

Are you able to provide the preprocessed source file floatdidf-9493d4.c from the crash dump?

[leonardchan]

In D123264#3691824, @craig.topper wrote:

In D123264#3691798, @leonardchan wrote:

Hi I think this patch led to the following ICEs seen on our windows builders (https://luci-milo.appspot.com/ui/p/fuchsia/builders/toolchain.ci/clang-windows-x64/b8807088318544910865/overview):

96/151] Building C object CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj
FAILED: CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj 
C:\b\s\w\ir\x\w\staging\llvm_build\.\bin\clang.exe -DVISIBILITY_HIDDEN  --target=riscv64-unknown-fuchsia -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/sync/include -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/fdio/include   -DCOMPILER_RT_HAS_FLOAT16 -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -o CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj   -c C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c
Unhandled encodeInstruction length!
UNREACHABLE executed at C:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV\MCTargetDesc\RISCVMCCodeEmitter.cpp:209!
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
Stack dump:
0.	Program arguments: C:\\b\\s\\w\\ir\\x\\w\\staging\\llvm_build\\.\\bin\\clang.exe -DVISIBILITY_HIDDEN --target=riscv64-unknown-fuchsia -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/sync/include -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/fdio/include -DCOMPILER_RT_HAS_FLOAT16 -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -o CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj -c C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c
1.	<eof> parser at end of file
2.	Code generation
3.	Running pass 'Function Pass Manager' on module 'C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c'.
4.	Running pass 'RISCV Assembly Printer' on function '@__floatdidf'
Exception Code: 0xC000001D
 #0 0x00007ff6a2ebbcb6 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x6dbcb6)
 #1 0x00007ff6a6d19bcb (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4539bcb)
 #2 0x00007ff6a6d0f0d0 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x452f0d0)
 #3 0x00007ff6a2e7e175 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x69e175)
 #4 0x00007ff6a374a155 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0xf6a155)
 #5 0x00007ff6a2c350aa (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4550aa)
 #6 0x00007ff6a3b6669c (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x138669c)
 #7 0x00007ff6a29197c8 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1397c8)
 #8 0x00007ff6a30cd61e (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x8ed61e)
 #9 0x00007ff6a2918d43 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x138d43)
#10 0x00007ff6a31301ca (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x9501ca)
#11 0x00007ff6a2b000f8 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x3200f8)
#12 0x00007ff6a2b070cc (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x3270cc)
#13 0x00007ff6a2b00829 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x320829)
#14 0x00007ff6a3d77231 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1597231)
#15 0x00007ff6a4176f58 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1996f58)
#16 0x00007ff6a58a9e4e (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x30c9e4e)
#17 0x00007ff6a40d5484 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x18f5484)
#18 0x00007ff6a302fc23 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x84fc23)
#19 0x00007ff6a30c4dc4 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x8e4dc4)
#20 0x00007ff6a27e7abe (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x7abe)
#21 0x00007ff6a27e4848 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4848)
#22 0x00007ff6a3e87636 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x16a7636)
#23 0x00007ff6a2e7ca22 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x69ca22)
#24 0x00007ff6a3e872cf (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x16a72cf)
#25 0x00007ff6a2fed54a (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x80d54a)
#26 0x00007ff6a2fed7af (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x80d7af)
#27 0x00007ff6a3006cfb (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x826cfb)
#28 0x00007ff6a27e418f (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x418f)
#29 0x00007ff6a6cfadf0 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x451adf0)
#30 0x00007ff90b9f7974 (C:\Windows\System32\KERNEL32.DLL+0x17974)
#31 0x00007ff90e73a2f1 (C:\Windows\SYSTEM32\ntdll.dll+0x5a2f1)
clang: error: clang frontend command failed due to signal (use -v to see invocation)
Fuchsia clang version 16.0.0 (https://llvm.googlesource.com/llvm-project 260a64106854986a981e49ed87ee740460a23eb5)
Target: riscv64-unknown-fuchsia
Thread model: posix
InstalledDir: C:\b\s\w\ir\x\w\staging\llvm_build\.\bin
clang: note: diagnostic msg: 
********************

PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang: note: diagnostic msg: C:\b\s\w\ir\x\t\floatdidf-9493d4.c
clang: note: diagnostic msg: C:\b\s\w\ir\x\t\floatdidf-9493d4.sh

clang: note: diagnostic msg: 



********************

Would you be able to send out a fix or revert?

Are you able to provide the preprocessed source file floatdidf-9493d4.c from the crash dump?

At the moment, no. I can try to reproduce it though that will take some time.

[craig.topper]

In D123264#3691830, @leonardchan wrote:

In D123264#3691824, @craig.topper wrote:

In D123264#3691798, @leonardchan wrote:

Hi I think this patch led to the following ICEs seen on our windows builders (https://luci-milo.appspot.com/ui/p/fuchsia/builders/toolchain.ci/clang-windows-x64/b8807088318544910865/overview):

96/151] Building C object CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj
FAILED: CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj 
C:\b\s\w\ir\x\w\staging\llvm_build\.\bin\clang.exe -DVISIBILITY_HIDDEN  --target=riscv64-unknown-fuchsia -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/sync/include -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/fdio/include   -DCOMPILER_RT_HAS_FLOAT16 -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -o CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj   -c C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c
Unhandled encodeInstruction length!
UNREACHABLE executed at C:\b\s\w\ir\x\w\llvm-llvm-project\llvm\lib\Target\RISCV\MCTargetDesc\RISCVMCCodeEmitter.cpp:209!
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
Stack dump:
0.	Program arguments: C:\\b\\s\\w\\ir\\x\\w\\staging\\llvm_build\\.\\bin\\clang.exe -DVISIBILITY_HIDDEN --target=riscv64-unknown-fuchsia -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/sync/include -IC:/b/s/w/ir/x/w/cipd/sdk/pkg/fdio/include -DCOMPILER_RT_HAS_FLOAT16 -std=c11 -fPIC -fno-builtin -fvisibility=hidden -fomit-frame-pointer -o CMakeFiles/clang_rt.builtins-riscv64.dir/floatdidf.c.obj -c C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c
1.	<eof> parser at end of file
2.	Code generation
3.	Running pass 'Function Pass Manager' on module 'C:/b/s/w/ir/x/w/llvm-llvm-project/compiler-rt/lib/builtins/floatdidf.c'.
4.	Running pass 'RISCV Assembly Printer' on function '@__floatdidf'
Exception Code: 0xC000001D
 #0 0x00007ff6a2ebbcb6 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x6dbcb6)
 #1 0x00007ff6a6d19bcb (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4539bcb)
 #2 0x00007ff6a6d0f0d0 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x452f0d0)
 #3 0x00007ff6a2e7e175 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x69e175)
 #4 0x00007ff6a374a155 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0xf6a155)
 #5 0x00007ff6a2c350aa (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4550aa)
 #6 0x00007ff6a3b6669c (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x138669c)
 #7 0x00007ff6a29197c8 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1397c8)
 #8 0x00007ff6a30cd61e (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x8ed61e)
 #9 0x00007ff6a2918d43 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x138d43)
#10 0x00007ff6a31301ca (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x9501ca)
#11 0x00007ff6a2b000f8 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x3200f8)
#12 0x00007ff6a2b070cc (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x3270cc)
#13 0x00007ff6a2b00829 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x320829)
#14 0x00007ff6a3d77231 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1597231)
#15 0x00007ff6a4176f58 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x1996f58)
#16 0x00007ff6a58a9e4e (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x30c9e4e)
#17 0x00007ff6a40d5484 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x18f5484)
#18 0x00007ff6a302fc23 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x84fc23)
#19 0x00007ff6a30c4dc4 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x8e4dc4)
#20 0x00007ff6a27e7abe (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x7abe)
#21 0x00007ff6a27e4848 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x4848)
#22 0x00007ff6a3e87636 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x16a7636)
#23 0x00007ff6a2e7ca22 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x69ca22)
#24 0x00007ff6a3e872cf (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x16a72cf)
#25 0x00007ff6a2fed54a (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x80d54a)
#26 0x00007ff6a2fed7af (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x80d7af)
#27 0x00007ff6a3006cfb (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x826cfb)
#28 0x00007ff6a27e418f (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x418f)
#29 0x00007ff6a6cfadf0 (C:\b\s\w\ir\x\w\staging\llvm_build\bin\clang.exe+0x451adf0)
#30 0x00007ff90b9f7974 (C:\Windows\System32\KERNEL32.DLL+0x17974)
#31 0x00007ff90e73a2f1 (C:\Windows\SYSTEM32\ntdll.dll+0x5a2f1)
clang: error: clang frontend command failed due to signal (use -v to see invocation)
Fuchsia clang version 16.0.0 (https://llvm.googlesource.com/llvm-project 260a64106854986a981e49ed87ee740460a23eb5)
Target: riscv64-unknown-fuchsia
Thread model: posix
InstalledDir: C:\b\s\w\ir\x\w\staging\llvm_build\.\bin
clang: note: diagnostic msg: 
********************

PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang: note: diagnostic msg: C:\b\s\w\ir\x\t\floatdidf-9493d4.c
clang: note: diagnostic msg: C:\b\s\w\ir\x\t\floatdidf-9493d4.sh

clang: note: diagnostic msg: 



********************

Would you be able to send out a fix or revert?

Are you able to provide the preprocessed source file floatdidf-9493d4.c from the crash dump?

At the moment, no. I can try to reproduce it though that will take some time.

Nevermind, that reproduced quite easily with ./bin/clang --target=riscv64-unknown-fuchsia ../compiler-rt/lib/builtins/floatdidf.c. I'll look at it right after I finish lunch.

[craig.topper]

Looks like we aren't running the pass at -O0. I didn't think about the fact that only O3-pipeline.ll and not O0-pipeline.ll was updated.

[craig.topper]

@leonardchan I pushed e07a8155f5168fdaff9346152d7805a47cb49405 to enable for -O0. Hopefully that resolves the crash.

[luismarques]

In D123264#3691976, @craig.topper wrote:

@leonardchan I pushed e07a8155f5168fdaff9346152d7805a47cb49405 to enable for -O0. Hopefully that resolves the crash.

Thanks Craig. Facepalm moment for me...

llvm/lib/CodeGen/MachineInstr.cpp

if (MO.isDef()) {
         return false;
     }
   }
   // If DebugLoc does not match then two debug instructions are not identical.
   if (isDebugInstr())
     if (getDebugLoc() && Other.getDebugLoc() &&
         getDebugLoc() != Other.getDebugLoc())
       return false;
+  // If pre- or post-instruction symbols do not match then the two instructions
+  // are not identical.
+  if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
+      getPostInstrSymbol() != Other.getPostInstrSymbol())
+    return false;
   return true;
 }
 
 const MachineFunction *MachineInstr::getMF() const {
   return getParent()->getParent();
 }
 
 MachineInstr *MachineInstr::removeFromParent() {

llvm/lib/Target/RISCV/RISCV.h

 void initializeRISCVSExtWRemovalPass(PassRegistry &);
 
 FunctionPass *createRISCVMergeBaseOffsetOptPass();
 void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
 
 FunctionPass *createRISCVExpandPseudoPass();
 void initializeRISCVExpandPseudoPass(PassRegistry &);
 
+FunctionPass *createRISCVPreRAExpandPseudoPass();
+void initializeRISCVPreRAExpandPseudoPass(PassRegistry &);
+
 FunctionPass *createRISCVExpandAtomicPseudoPass();
 void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
 
 FunctionPass *createRISCVInsertVSETVLIPass();
 void initializeRISCVInsertVSETVLIPass(PassRegistry &);
 
 FunctionPass *createRISCVRedundantCopyEliminationPass();
 void initializeRISCVRedundantCopyEliminationPass(PassRegistry &);
 
 InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
                                                     RISCVSubtarget &,
                                                     RISCVRegisterBankInfo &);
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

 
 #include "RISCV.h"
 #include "RISCVInstrInfo.h"
 #include "RISCVTargetMachine.h"
 
 #include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/MC/MCContext.h"
 
 using namespace llvm;
 
 #define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass"
+#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISCV Pre-RA pseudo instruction expansion pass"
 
 namespace {
 
 class RISCVExpandPseudo : public MachineFunctionPass {
 public:
   const RISCVInstrInfo *TII;
   static char ID;
 
   RISCVExpandPseudo() : MachineFunctionPass(ID) {
     initializeRISCVExpandPseudoPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
 
 private:
   bool expandMBB(MachineBasicBlock &MBB);
   bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                 MachineBasicBlock::iterator &NextMBBI);
   bool expandAuipcInstPair(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            MachineBasicBlock::iterator &NextMBBI,
                            unsigned FlagsHi, unsigned SecondOpcode);
-  bool expandLoadLocalAddress(MachineBasicBlock &MBB,
-                              MachineBasicBlock::iterator MBBI,
-                              MachineBasicBlock::iterator &NextMBBI);
   bool expandLoadAddress(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MBBI,
                          MachineBasicBlock::iterator &NextMBBI);
   bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MBBI,
                               MachineBasicBlock::iterator &NextMBBI);
   bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MBBI,

 }
 
 bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MBBI,
                                  MachineBasicBlock::iterator &NextMBBI) {
   // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
   // expanded instructions for each pseudo is correct in the Size field of the
   // tablegen definition for the pseudo.
   switch (MBBI->getOpcode()) {
-  case RISCV::PseudoLLA:
-    return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
   case RISCV::PseudoLA:
     return expandLoadAddress(MBB, MBBI, NextMBBI);
   case RISCV::PseudoLA_TLS_IE:
     return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
   case RISCV::PseudoLA_TLS_GD:
     return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
   case RISCV::PseudoVSETVLI:
   case RISCV::PseudoVSETVLIX0:
   case RISCV::PseudoVSETIVLI:
bool RISCVExpandPseudo::expandAuipcInstPair(
   LivePhysRegs LiveRegs;
   computeAndAddLiveIns(LiveRegs, *NewMBB);
 
   NextMBBI = MBB.end();
   MI.eraseFromParent();
   return true;
 }
 
-bool RISCVExpandPseudo::expandLoadLocalAddress(
-    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
-    MachineBasicBlock::iterator &NextMBBI) {
-  return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
-                             RISCV::ADDI);
-}
-
 bool RISCVExpandPseudo::expandLoadAddress(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     MachineBasicBlock::iterator &NextMBBI) {
   MachineFunction *MF = MBB.getParent();
 
   unsigned SecondOpcode;
   unsigned FlagsHi;
   if (MF->getTarget().isPositionIndependent()) {
if (I != NF - 1)
       BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), Base)
           .addReg(Base)
           .addReg(VL);
   }
   MBBI->eraseFromParent();
   return true;
 }
 
+class RISCVPreRAExpandPseudo : public MachineFunctionPass {
+public:
+  const RISCVInstrInfo *TII;
+  static char ID;
+
+  RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {
+    initializeRISCVPreRAExpandPseudoPass(*PassRegistry::getPassRegistry());
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override { return RISCV_PRERA_EXPAND_PSEUDO_NAME; }
+
+private:
+  bool expandMBB(MachineBasicBlock &MBB);
+  bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+                MachineBasicBlock::iterator &NextMBBI);
+  bool expandAuipcInstPair(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MBBI,
+                           MachineBasicBlock::iterator &NextMBBI,
+                           unsigned FlagsHi, unsigned SecondOpcode);
+  bool expandLoadLocalAddress(MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator MBBI,
+                              MachineBasicBlock::iterator &NextMBBI);
+};
+
+char RISCVPreRAExpandPseudo::ID = 0;
+
+bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
+  TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
+  bool Modified = false;
+  for (auto &MBB : MF)
+    Modified |= expandMBB(MBB);
+  return Modified;
+}
+
+bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
+  bool Modified = false;
+
+  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+  while (MBBI != E) {
+    MachineBasicBlock::iterator NMBBI = std::next(MBBI);
+    Modified |= expandMI(MBB, MBBI, NMBBI);
+    MBBI = NMBBI;
+  }
+
+  return Modified;
+}
+
+bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
+                                      MachineBasicBlock::iterator MBBI,
+                                      MachineBasicBlock::iterator &NextMBBI) {
+
+  switch (MBBI->getOpcode()) {
+  case RISCV::PseudoLLA:
+    return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
+  }
+  return false;
+}
+
+bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
+    unsigned SecondOpcode) {
+  MachineFunction *MF = MBB.getParent();
+  MachineInstr &MI = *MBBI;
+  DebugLoc DL = MI.getDebugLoc();
+
+  Register DestReg = MI.getOperand(0).getReg();
+  Register ScratchReg =
+      MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
+
+  MachineOperand &Symbol = MI.getOperand(1);
+  Symbol.setTargetFlags(FlagsHi);
+  MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("PCRelHi");
+
+  MachineInstr *MIAUIPC =
+      BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
+  MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
+
+  BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
+      .addReg(ScratchReg)
+      .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
+
+  MI.eraseFromParent();
+  return true;
+}
+
+bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    MachineBasicBlock::iterator &NextMBBI) {
+  return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
+                             RISCV::ADDI);
+}
+
 } // end of anonymous namespace
 
 INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
                 RISCV_EXPAND_PSEUDO_NAME, false, false)
+
+INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
+                RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
+
 namespace llvm {
 
 FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
+FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
 
 } // end of namespace llvm

llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

MCOp = lowerSymbolOperand(
         MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
     break;
   case MachineOperand::MO_ConstantPoolIndex:
     MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
     break;
   case MachineOperand::MO_JumpTableIndex:
     MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
     break;
+  case MachineOperand::MO_MCSymbol:
+    MCOp = lowerSymbolOperand(MO, MO.getMCSymbol(), AP);
+    break;
   }
   return true;
 }
 
 static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
                                             MCInst &OutMI) {
   const RISCVVPseudosTable::PseudoInfo *RVV =
       RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

void RISCVPassConfig::addPreEmitPass2() {
   addPass(createRISCVExpandAtomicPseudoPass());
 }
 
 void RISCVPassConfig::addMachineSSAOptimization() {
   TargetPassConfig::addMachineSSAOptimization();
 
   if (TM->getTargetTriple().getArch() == Triple::riscv64)
     addPass(createRISCVSExtWRemovalPass());
+  addPass(createRISCVPreRAExpandPseudoPass());
 }
 
 void RISCVPassConfig::addPreRegAlloc() {
   if (TM->getOptLevel() != CodeGenOpt::None)
     addPass(createRISCVMergeBaseOffsetOptPass());
   addPass(createRISCVInsertVSETVLIPass());
 }
 

llvm/test/CodeGen/RISCV/O3-pipeline.ll

 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Machine Common Subexpression Elimination
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Machine code sinking
 ; CHECK-NEXT:       Peephole Optimizations
 ; CHECK-NEXT:       Remove dead machine instructions
 ; RV64-NEXT:        RISCV sext.w Removal
+; CHECK-NEXT:       RISCV Pre-RA pseudo instruction expansion pass
 ; CHECK-NEXT:       RISCV Merge Base Offset
 ; CHECK-NEXT:       RISCV Insert VSETVLI pass
 ; CHECK-NEXT:       Detect Dead Lanes
 ; CHECK-NEXT:       Process Implicit Definitions
 ; CHECK-NEXT:       Remove unreachable machine basic blocks
 ; CHECK-NEXT:       Live Variable Analysis
+; CHECK-NEXT:       MachineDominator Tree Construction
+; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       Eliminate PHI nodes for register allocation
 ; CHECK-NEXT:       Two-Address instruction pass
-; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       Slot index numbering
 ; CHECK-NEXT:       Live Interval Analysis
 ; CHECK-NEXT:       Simple Register Coalescing
 ; CHECK-NEXT:       Rename Disconnected Subregister Components
 ; CHECK-NEXT:       Machine Instruction Scheduler
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       Debug Variable Analysis
 ; CHECK-NEXT:       Live Stack Slot Analysis

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

 ; RV32I-SMALL-LABEL: lower_global:
 ; RV32I-SMALL:       # %bb.0:
 ; RV32I-SMALL-NEXT:    lui a0, %hi(G)
 ; RV32I-SMALL-NEXT:    lw a0, %lo(G)(a0)
 ; RV32I-SMALL-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: lower_global:
 ; RV32I-MEDIUM:       # %bb.0:
-; RV32I-MEDIUM-NEXT:  .LBB0_1: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT:  .LPCRelHi0:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(G)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.LBB0_1)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi0)
 ; RV32I-MEDIUM-NEXT:    lw a0, 0(a0)
 ; RV32I-MEDIUM-NEXT:    ret
   %1 = load volatile i32, i32* @G
   ret i32 %1
 }
 
 ; Check lowering of blockaddresses
 
 @addr = global i8* null
 
 define void @lower_blockaddress() nounwind {
 ; RV32I-SMALL-LABEL: lower_blockaddress:
 ; RV32I-SMALL:       # %bb.0:
 ; RV32I-SMALL-NEXT:    lui a0, %hi(addr)
 ; RV32I-SMALL-NEXT:    li a1, 1
 ; RV32I-SMALL-NEXT:    sw a1, %lo(addr)(a0)
 ; RV32I-SMALL-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: lower_blockaddress:
 ; RV32I-MEDIUM:       # %bb.0:
-; RV32I-MEDIUM-NEXT:  .LBB1_1: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT:  .LPCRelHi1:
 ; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(addr)
-; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV32I-MEDIUM-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi1)
 ; RV32I-MEDIUM-NEXT:    li a1, 1
 ; RV32I-MEDIUM-NEXT:    sw a1, 0(a0)
 ; RV32I-MEDIUM-NEXT:    ret
   store volatile i8* blockaddress(@lower_blockaddress, %block), i8** @addr
   ret void
 
 block:
   unreachable

 ; RV32I-SMALL-NEXT:  .LBB2_3: # %return.clone
 ; RV32I-SMALL-NEXT:    li a0, 3
 ; RV32I-SMALL-NEXT:    addi sp, sp, 16
 ; RV32I-SMALL-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: lower_blockaddress_displ:
 ; RV32I-MEDIUM:       # %bb.0: # %entry
 ; RV32I-MEDIUM-NEXT:    addi sp, sp, -16
-; RV32I-MEDIUM-NEXT:  .LBB2_4: # %entry
-; RV32I-MEDIUM-NEXT:    # Label of block must be emitted
+; RV32I-MEDIUM-NEXT:  .LPCRelHi2:
 ; RV32I-MEDIUM-NEXT:    auipc a1, %pcrel_hi(.Ltmp0)
-; RV32I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.LBB2_4)
+; RV32I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.LPCRelHi2)
 ; RV32I-MEDIUM-NEXT:    li a2, 101
 ; RV32I-MEDIUM-NEXT:    sw a1, 8(sp)
 ; RV32I-MEDIUM-NEXT:    blt a0, a2, .LBB2_3
 ; RV32I-MEDIUM-NEXT:  # %bb.1: # %if.then
 ; RV32I-MEDIUM-NEXT:    lw a0, 8(sp)
 ; RV32I-MEDIUM-NEXT:    jr a0
 ; RV32I-MEDIUM-NEXT:  .Ltmp0: # Block address taken
 ; RV32I-MEDIUM-NEXT:  .LBB2_2: # %return

 ; RV32I-SMALL-NEXT:    flw ft0, %lo(.LCPI3_0)(a1)
 ; RV32I-SMALL-NEXT:    fmv.w.x ft1, a0
 ; RV32I-SMALL-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32I-SMALL-NEXT:    fmv.x.w a0, ft0
 ; RV32I-SMALL-NEXT:    ret
 ;
 ; RV32I-MEDIUM-LABEL: lower_constantpool:
 ; RV32I-MEDIUM:       # %bb.0:
-; RV32I-MEDIUM-NEXT:  .LBB3_1: # Label of block must be emitted
+; RV32I-MEDIUM-NEXT:  .LPCRelHi3:
 ; RV32I-MEDIUM-NEXT:    auipc a1, %pcrel_hi(.LCPI3_0)
-; RV32I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.LBB3_1)
+; RV32I-MEDIUM-NEXT:    addi a1, a1, %pcrel_lo(.LPCRelHi3)
 ; RV32I-MEDIUM-NEXT:    flw ft0, 0(a1)
 ; RV32I-MEDIUM-NEXT:    fmv.w.x ft1, a0
 ; RV32I-MEDIUM-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32I-MEDIUM-NEXT:    fmv.x.w a0, ft0
 ; RV32I-MEDIUM-NEXT:    ret
   %1 = fadd float %a, 1.0
   ret float %1
 }

llvm/test/CodeGen/RISCV/elf-preemption.ll

 ; RV32-STATIC-LABEL: get_dsolocal_var:
 ; RV32-STATIC:       # %bb.0:
 ; RV32-STATIC-NEXT:    lui a0, %hi(dsolocal_var)
 ; RV32-STATIC-NEXT:    addi a0, a0, %lo(dsolocal_var)
 ; RV32-STATIC-NEXT:    ret
 ;
 ; RV32-PIC-LABEL: get_dsolocal_var:
 ; RV32-PIC:       # %bb.0:
-; RV32-PIC-NEXT:  .LBB1_1: # Label of block must be emitted
+; RV32-PIC-NEXT:  .LPCRelHi0:
 ; RV32-PIC-NEXT:    auipc a0, %pcrel_hi(.Ldsolocal_var$local)
-; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi0)
 ; RV32-PIC-NEXT:    ret
 ;
 ; RV64-STATIC-LABEL: get_dsolocal_var:
 ; RV64-STATIC:       # %bb.0:
 ; RV64-STATIC-NEXT:    lui a0, %hi(dsolocal_var)
 ; RV64-STATIC-NEXT:    addi a0, a0, %lo(dsolocal_var)
 ; RV64-STATIC-NEXT:    ret
 ;
 ; RV64-PIC-LABEL: get_dsolocal_var:
 ; RV64-PIC:       # %bb.0:
-; RV64-PIC-NEXT:  .LBB1_1: # Label of block must be emitted
+; RV64-PIC-NEXT:  .LPCRelHi0:
 ; RV64-PIC-NEXT:    auipc a0, %pcrel_hi(.Ldsolocal_var$local)
-; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi0)
 ; RV64-PIC-NEXT:    ret
   ret i32* @dsolocal_var
 }
 
 @weak_dsolocal_var = weak dso_local global i32 42
 define i32* @get_weak_dsolocal_var() nounwind {
 ; RV32-STATIC-LABEL: get_weak_dsolocal_var:
 ; RV32-STATIC:       # %bb.0:
 ; RV32-STATIC-NEXT:    lui a0, %hi(weak_dsolocal_var)
 ; RV32-STATIC-NEXT:    addi a0, a0, %lo(weak_dsolocal_var)
 ; RV32-STATIC-NEXT:    ret
 ;
 ; RV32-PIC-LABEL: get_weak_dsolocal_var:
 ; RV32-PIC:       # %bb.0:
-; RV32-PIC-NEXT:  .LBB2_1: # Label of block must be emitted
+; RV32-PIC-NEXT:  .LPCRelHi1:
 ; RV32-PIC-NEXT:    auipc a0, %pcrel_hi(weak_dsolocal_var)
-; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB2_1)
+; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi1)
 ; RV32-PIC-NEXT:    ret
 ;
 ; RV64-STATIC-LABEL: get_weak_dsolocal_var:
 ; RV64-STATIC:       # %bb.0:
 ; RV64-STATIC-NEXT:    lui a0, %hi(weak_dsolocal_var)
 ; RV64-STATIC-NEXT:    addi a0, a0, %lo(weak_dsolocal_var)
 ; RV64-STATIC-NEXT:    ret
 ;
 ; RV64-PIC-LABEL: get_weak_dsolocal_var:
 ; RV64-PIC:       # %bb.0:
-; RV64-PIC-NEXT:  .LBB2_1: # Label of block must be emitted
+; RV64-PIC-NEXT:  .LPCRelHi1:
 ; RV64-PIC-NEXT:    auipc a0, %pcrel_hi(weak_dsolocal_var)
-; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB2_1)
+; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi1)
 ; RV64-PIC-NEXT:    ret
   ret i32* @weak_dsolocal_var
 }
 
 @hidden_var = hidden global i32 42
 define i32* @get_hidden_var() nounwind {
 ; RV32-STATIC-LABEL: get_hidden_var:
 ; RV32-STATIC:       # %bb.0:
 ; RV32-STATIC-NEXT:    lui a0, %hi(hidden_var)
 ; RV32-STATIC-NEXT:    addi a0, a0, %lo(hidden_var)
 ; RV32-STATIC-NEXT:    ret
 ;
 ; RV32-PIC-LABEL: get_hidden_var:
 ; RV32-PIC:       # %bb.0:
-; RV32-PIC-NEXT:  .LBB3_1: # Label of block must be emitted
+; RV32-PIC-NEXT:  .LPCRelHi2:
 ; RV32-PIC-NEXT:    auipc a0, %pcrel_hi(hidden_var)
-; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB3_1)
+; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi2)
 ; RV32-PIC-NEXT:    ret
 ;
 ; RV64-STATIC-LABEL: get_hidden_var:
 ; RV64-STATIC:       # %bb.0:
 ; RV64-STATIC-NEXT:    lui a0, %hi(hidden_var)
 ; RV64-STATIC-NEXT:    addi a0, a0, %lo(hidden_var)
 ; RV64-STATIC-NEXT:    ret
 ;
 ; RV64-PIC-LABEL: get_hidden_var:
 ; RV64-PIC:       # %bb.0:
-; RV64-PIC-NEXT:  .LBB3_1: # Label of block must be emitted
+; RV64-PIC-NEXT:  .LPCRelHi2:
 ; RV64-PIC-NEXT:    auipc a0, %pcrel_hi(hidden_var)
-; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB3_1)
+; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi2)
 ; RV64-PIC-NEXT:    ret
   ret i32* @hidden_var
 }
 
 @protected_var = protected global i32 42
 define i32* @get_protected_var() nounwind {
 ; RV32-STATIC-LABEL: get_protected_var:
 ; RV32-STATIC:       # %bb.0:
 ; RV32-STATIC-NEXT:    lui a0, %hi(protected_var)
 ; RV32-STATIC-NEXT:    addi a0, a0, %lo(protected_var)
 ; RV32-STATIC-NEXT:    ret
 ;
 ; RV32-PIC-LABEL: get_protected_var:
 ; RV32-PIC:       # %bb.0:
-; RV32-PIC-NEXT:  .LBB4_1: # Label of block must be emitted
+; RV32-PIC-NEXT:  .LPCRelHi3:
 ; RV32-PIC-NEXT:    auipc a0, %pcrel_hi(protected_var)
-; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB4_1)
+; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi3)
 ; RV32-PIC-NEXT:    ret
 ;
 ; RV64-STATIC-LABEL: get_protected_var:
 ; RV64-STATIC:       # %bb.0:
 ; RV64-STATIC-NEXT:    lui a0, %hi(protected_var)
 ; RV64-STATIC-NEXT:    addi a0, a0, %lo(protected_var)
 ; RV64-STATIC-NEXT:    ret
 ;
 ; RV64-PIC-LABEL: get_protected_var:
 ; RV64-PIC:       # %bb.0:
-; RV64-PIC-NEXT:  .LBB4_1: # Label of block must be emitted
+; RV64-PIC-NEXT:  .LPCRelHi3:
 ; RV64-PIC-NEXT:    auipc a0, %pcrel_hi(protected_var)
-; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB4_1)
+; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi3)
 ; RV64-PIC-NEXT:    ret
   ret i32* @protected_var
 }
 
 define dso_preemptable void()* @preemptable_func() nounwind {
 ; RV32-STATIC-LABEL: preemptable_func:
 ; RV32-STATIC:       # %bb.0:
 ; RV32-STATIC-NEXT:    lui a0, %hi(preemptable_func)

 ; RV32-STATIC-LABEL: dsolocal_func:
 ; RV32-STATIC:       # %bb.0:
 ; RV32-STATIC-NEXT:    lui a0, %hi(dsolocal_func)
 ; RV32-STATIC-NEXT:    addi a0, a0, %lo(dsolocal_func)
 ; RV32-STATIC-NEXT:    ret
 ;
 ; RV32-PIC-LABEL: dsolocal_func:
 ; RV32-PIC:       # %bb.0:
-; RV32-PIC-NEXT:  .LBB6_1: # Label of block must be emitted
+; RV32-PIC-NEXT:  .LPCRelHi4:
 ; RV32-PIC-NEXT:    auipc a0, %pcrel_hi(.Ldsolocal_func$local)
-; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB6_1)
+; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi4)
 ; RV32-PIC-NEXT:    ret
 ;
 ; RV64-STATIC-LABEL: dsolocal_func:
 ; RV64-STATIC:       # %bb.0:
 ; RV64-STATIC-NEXT:    lui a0, %hi(dsolocal_func)
 ; RV64-STATIC-NEXT:    addi a0, a0, %lo(dsolocal_func)
 ; RV64-STATIC-NEXT:    ret
 ;
 ; RV64-PIC-LABEL: dsolocal_func:
 ; RV64-PIC:       # %bb.0:
-; RV64-PIC-NEXT:  .LBB6_1: # Label of block must be emitted
+; RV64-PIC-NEXT:  .LPCRelHi4:
 ; RV64-PIC-NEXT:    auipc a0, %pcrel_hi(.Ldsolocal_func$local)
-; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB6_1)
+; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi4)
 ; RV64-PIC-NEXT:    ret
   ret void()* bitcast(void()*()* @dsolocal_func to void()*)
 }
 
 define weak dso_local void()* @weak_dsolocal_func() nounwind {
 ; RV32-STATIC-LABEL: weak_dsolocal_func:
 ; RV32-STATIC:       # %bb.0:
 ; RV32-STATIC-NEXT:    lui a0, %hi(weak_dsolocal_func)
 ; RV32-STATIC-NEXT:    addi a0, a0, %lo(weak_dsolocal_func)
 ; RV32-STATIC-NEXT:    ret
 ;
 ; RV32-PIC-LABEL: weak_dsolocal_func:
 ; RV32-PIC:       # %bb.0:
-; RV32-PIC-NEXT:  .LBB7_1: # Label of block must be emitted
+; RV32-PIC-NEXT:  .LPCRelHi5:
 ; RV32-PIC-NEXT:    auipc a0, %pcrel_hi(weak_dsolocal_func)
-; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB7_1)
+; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi5)
 ; RV32-PIC-NEXT:    ret
 ;
 ; RV64-STATIC-LABEL: weak_dsolocal_func:
 ; RV64-STATIC:       # %bb.0:
 ; RV64-STATIC-NEXT:    lui a0, %hi(weak_dsolocal_func)
 ; RV64-STATIC-NEXT:    addi a0, a0, %lo(weak_dsolocal_func)
 ; RV64-STATIC-NEXT:    ret
 ;
 ; RV64-PIC-LABEL: weak_dsolocal_func:
 ; RV64-PIC:       # %bb.0:
-; RV64-PIC-NEXT:  .LBB7_1: # Label of block must be emitted
+; RV64-PIC-NEXT:  .LPCRelHi5:
 ; RV64-PIC-NEXT:    auipc a0, %pcrel_hi(weak_dsolocal_func)
-; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB7_1)
+; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi5)
 ; RV64-PIC-NEXT:    ret
   ret void()* bitcast(void()*()* @weak_dsolocal_func to void()*)
 }
 
 ;; call .Ldsolocal_func$local either resolves to a constant at assembly time
 ;; or produces a relocation referencing a non-preemptible local symbol.
 define dso_local void @call_dsolocal_func() nounwind {
 ; RV32-STATIC-LABEL: call_dsolocal_func:

llvm/test/CodeGen/RISCV/jumptable.ll

 ;
 ; RV32I-MEDIUM-LABEL: above_threshold:
 ; RV32I-MEDIUM:       # %bb.0: # %entry
 ; RV32I-MEDIUM-NEXT:    addi a0, a0, -1
 ; RV32I-MEDIUM-NEXT:    li a2, 5
 ; RV32I-MEDIUM-NEXT:    bltu a2, a0, .LBB1_9
 ; RV32I-MEDIUM-NEXT:  # %bb.1: # %entry
 ; RV32I-MEDIUM-NEXT:    slli a0, a0, 2
-; RV32I-MEDIUM-NEXT:  .LBB1_10: # %entry
-; RV32I-MEDIUM-NEXT:    # Label of block must be emitted
+; RV32I-MEDIUM-NEXT:  .LPCRelHi0:
 ; RV32I-MEDIUM-NEXT:    auipc a2, %pcrel_hi(.LJTI1_0)
-; RV32I-MEDIUM-NEXT:    addi a2, a2, %pcrel_lo(.LBB1_10)
+; RV32I-MEDIUM-NEXT:    addi a2, a2, %pcrel_lo(.LPCRelHi0)
 ; RV32I-MEDIUM-NEXT:    add a0, a0, a2
 ; RV32I-MEDIUM-NEXT:    lw a0, 0(a0)
 ; RV32I-MEDIUM-NEXT:    jr a0
 ; RV32I-MEDIUM-NEXT:  .LBB1_2: # %bb1
 ; RV32I-MEDIUM-NEXT:    li a0, 4
 ; RV32I-MEDIUM-NEXT:    j .LBB1_8
 ; RV32I-MEDIUM-NEXT:  .LBB1_3: # %bb2
 ; RV32I-MEDIUM-NEXT:    li a0, 3

 ; RV64I-MEDIUM-LABEL: above_threshold:
 ; RV64I-MEDIUM:       # %bb.0: # %entry
 ; RV64I-MEDIUM-NEXT:    sext.w a0, a0
 ; RV64I-MEDIUM-NEXT:    addi a0, a0, -1
 ; RV64I-MEDIUM-NEXT:    li a2, 5
 ; RV64I-MEDIUM-NEXT:    bltu a2, a0, .LBB1_9
 ; RV64I-MEDIUM-NEXT:  # %bb.1: # %entry
 ; RV64I-MEDIUM-NEXT:    slli a0, a0, 3
-; RV64I-MEDIUM-NEXT:  .LBB1_10: # %entry
-; RV64I-MEDIUM-NEXT:    # Label of block must be emitted
+; RV64I-MEDIUM-NEXT:  .LPCRelHi0:
 ; RV64I-MEDIUM-NEXT:    auipc a2, %pcrel_hi(.LJTI1_0)
-; RV64I-MEDIUM-NEXT:    addi a2, a2, %pcrel_lo(.LBB1_10)
+; RV64I-MEDIUM-NEXT:    addi a2, a2, %pcrel_lo(.LPCRelHi0)
 ; RV64I-MEDIUM-NEXT:    add a0, a0, a2
 ; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
 ; RV64I-MEDIUM-NEXT:    jr a0
 ; RV64I-MEDIUM-NEXT:  .LBB1_2: # %bb1
 ; RV64I-MEDIUM-NEXT:    li a0, 4
 ; RV64I-MEDIUM-NEXT:    j .LBB1_8
 ; RV64I-MEDIUM-NEXT:  .LBB1_3: # %bb2
 ; RV64I-MEDIUM-NEXT:    li a0, 3

llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV32I %s
 ; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV64I %s
 
 ; Verifies that MachineLICM can hoist address generation pseudos out of loops.
 
 @l = protected global i32 0, align 4
 
 define void @test_lla(i32 signext %n) {
 ; RV32I-LABEL: test_lla:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    li a1, 0
-; RV32I-NEXT:  .LBB0_3: # %entry
-; RV32I-NEXT:    # Label of block must be emitted
+; RV32I-NEXT:  .LPCRelHi0:
 ; RV32I-NEXT:    auipc a2, %pcrel_hi(l)
-; RV32I-NEXT:    addi a2, a2, %pcrel_lo(.LBB0_3)
+; RV32I-NEXT:    addi a2, a2, %pcrel_lo(.LPCRelHi0)
 ; RV32I-NEXT:  .LBB0_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    lw a3, 0(a2)
 ; RV32I-NEXT:    addi a1, a1, 1
 ; RV32I-NEXT:    blt a1, a0, .LBB0_1
 ; RV32I-NEXT:  # %bb.2: # %ret
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_lla:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    li a1, 0
-; RV64I-NEXT:  .LBB0_3: # %entry
-; RV64I-NEXT:    # Label of block must be emitted
+; RV64I-NEXT:  .LPCRelHi0:
 ; RV64I-NEXT:    auipc a2, %pcrel_hi(l)
-; RV64I-NEXT:    addi a2, a2, %pcrel_lo(.LBB0_3)
+; RV64I-NEXT:    addi a2, a2, %pcrel_lo(.LPCRelHi0)
 ; RV64I-NEXT:  .LBB0_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    lw a3, 0(a2)
 ; RV64I-NEXT:    addiw a1, a1, 1
 ; RV64I-NEXT:    blt a1, a0, .LBB0_1
 ; RV64I-NEXT:  # %bb.2: # %ret
 ; RV64I-NEXT:    ret
 entry:

llvm/test/CodeGen/RISCV/mir-target-flags-medium.ll

+; RUN: llc -mtriple=riscv32 --code-model=medium --relocation-model=pic \
+; RUN:   -stop-after riscv-expand-pseudo %s -o %t.mir
+; RUN: llc -mtriple=riscv32 -run-pass none %t.mir -o - | \
+; RUN:   FileCheck %s -check-prefix=RV32-MED
+
+; This tests the RISC-V-specific serialization and deserialization of
+; `target-flags(...)` with the medium code model. We currently can't test
+; `internal global` variables with this model because MIR printing doesn't
+; yet support temporary MCSymbols, which we now emit during the PseudoLLA
+; expansion into AUIPC+ADDI instructions.
+
+@g_e = external global i32
+@t_un = external thread_local global i32
+@t_ld = external thread_local(localdynamic) global i32
+@t_ie = external thread_local(initialexec) global i32
+@t_le = external thread_local(localexec) global i32
+
+declare i32 @callee(i32) nounwind
+
+define i32 @caller(i32 %a) nounwind {
+; RV32-MED-LABEL: name: caller
+; RV32-MED:      target-flags(riscv-got-hi) @g_e
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.1
+; RV32-MED:      target-flags(riscv-tls-gd-hi) @t_un
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.2
+; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
+; RV32-MED:      target-flags(riscv-tls-gd-hi) @t_ld
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.3
+; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
+; RV32-MED:      target-flags(riscv-tls-got-hi) @t_ie
+; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.4
+; RV32-MED:      target-flags(riscv-tprel-hi) @t_le
+; RV32-MED-NEXT: target-flags(riscv-tprel-add) @t_le
+; RV32-MED-NEXT: target-flags(riscv-tprel-lo) @t_le
+; RV32-MED:      target-flags(riscv-plt) @callee
+;
+  %b = load i32, i32* @g_e
+  %c = load i32, i32* @t_un
+  %d = load i32, i32* @t_ld
+  %e = load i32, i32* @t_ie
+  %f = load i32, i32* @t_le
+  %sum = bitcast i32 0 to i32
+  %sum.a = add i32 %sum, %a
+  %sum.b = add i32 %sum.a, %b
+  %sum.c = add i32 %sum.b, %c
+  %sum.d = add i32 %sum.c, %d
+  %sum.e = add i32 %sum.d, %e
+  %sum.f = add i32 %sum.e, %f
+  %retval = call i32 @callee(i32 %sum.f)
+  ret i32 %retval
+}

llvm/test/CodeGen/RISCV/mir-target-flags-small.ll

 ; RUN: llc -mtriple=riscv32 --code-model=small \
 ; RUN:    -stop-after riscv-expand-pseudo %s -o %t.mir
 ; RUN: llc -mtriple=riscv32 -run-pass none %t.mir -o - | \
 ; RUN:   FileCheck %s -check-prefix=RV32-SMALL
 ;
-; RUN: llc -mtriple=riscv32 --code-model=medium --relocation-model=pic \
-; RUN:   -stop-after riscv-expand-pseudo %s -o %t.mir
-; RUN: llc -mtriple=riscv32 -run-pass none %t.mir -o - | \
-; RUN:   FileCheck %s -check-prefix=RV32-MED
-
 ; This tests the RISC-V-specific serialization and deserialization of
-; `target-flags(...)`
+; `target-flags(...)` with the small code model.
 
 @g_e = external global i32
 @g_i = internal global i32 0
 @t_un = external thread_local global i32
 @t_ld = external thread_local(localdynamic) global i32
 @t_ie = external thread_local(initialexec) global i32
 @t_le = external thread_local(localexec) global i32
 

 ; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) %bb.2
 ; RV32-SMALL:      target-flags(riscv-tls-got-hi) @t_ie
 ; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) %bb.3
 ; RV32-SMALL:      target-flags(riscv-tprel-hi) @t_le
 ; RV32-SMALL-NEXT: target-flags(riscv-tprel-add) @t_le
 ; RV32-SMALL-NEXT: target-flags(riscv-tprel-lo) @t_le
 ; RV32-SMALL:      target-flags(riscv-plt) @callee
 ;
-; RV32-MED-LABEL: name: caller
-; RV32-MED:      target-flags(riscv-got-hi) @g_e
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.1
-; RV32-MED:      target-flags(riscv-pcrel-hi) @g_i
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.2
-; RV32-MED:      target-flags(riscv-tls-gd-hi) @t_un
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.3
-; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
-; RV32-MED:      target-flags(riscv-tls-gd-hi) @t_ld
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.4
-; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
-; RV32-MED:      target-flags(riscv-tls-got-hi) @t_ie
-; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.5
-; RV32-MED:      target-flags(riscv-tprel-hi) @t_le
-; RV32-MED-NEXT: target-flags(riscv-tprel-add) @t_le
-; RV32-MED-NEXT: target-flags(riscv-tprel-lo) @t_le
-; RV32-MED:      target-flags(riscv-plt) @callee
-;
   %b = load i32, i32* @g_e
   %c = load i32, i32* @g_i
   %d = load i32, i32* @t_un
   %e = load i32, i32* @t_ld
   %f = load i32, i32* @t_ie
   %g = load i32, i32* @t_le
   %sum = bitcast i32 0 to i32
   %sum.a = add i32 %sum, %a

llvm/test/CodeGen/RISCV/pic-models.ll

 ; RV32-STATIC-LABEL: f2:
 ; RV32-STATIC:       # %bb.0: # %entry
 ; RV32-STATIC-NEXT:    lui a0, %hi(internal_var)
 ; RV32-STATIC-NEXT:    addi a0, a0, %lo(internal_var)
 ; RV32-STATIC-NEXT:    ret
 ;
 ; RV32-PIC-LABEL: f2:
 ; RV32-PIC:       # %bb.0: # %entry
-; RV32-PIC-NEXT:  .LBB1_1: # %entry
-; RV32-PIC-NEXT:    # Label of block must be emitted
+; RV32-PIC-NEXT:  .LPCRelHi0:
 ; RV32-PIC-NEXT:    auipc a0, %pcrel_hi(internal_var)
-; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi0)
 ; RV32-PIC-NEXT:    ret
 ;
 ; RV64-STATIC-LABEL: f2:
 ; RV64-STATIC:       # %bb.0: # %entry
 ; RV64-STATIC-NEXT:    lui a0, %hi(internal_var)
 ; RV64-STATIC-NEXT:    addi a0, a0, %lo(internal_var)
 ; RV64-STATIC-NEXT:    ret
 ;
 ; RV64-PIC-LABEL: f2:
 ; RV64-PIC:       # %bb.0: # %entry
-; RV64-PIC-NEXT:  .LBB1_1: # %entry
-; RV64-PIC-NEXT:    # Label of block must be emitted
+; RV64-PIC-NEXT:  .LPCRelHi0:
 ; RV64-PIC-NEXT:    auipc a0, %pcrel_hi(internal_var)
-; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LPCRelHi0)
 ; RV64-PIC-NEXT:    ret
 entry:
   ret i32* @internal_var
 }