[RISCV] add support for zbkx subextension in MC layer.

[SForeKeeper]

Summary

This patch adds support for zbkx extension from K extension(v1.0.0) in MC layer.
Instructions with same functionality and same encoding is defined in the bitmanip extension.
It defines {Xperm8, Xperm4} as instruction aliases for xperm.* in Zbp extension. When Zbkx is enabled while Zbp is not, xperm.h will not be available. When Zbkx and Zbp are both enabled, the instructions will be decoded in Zbp format.

D94999 this is the patch that introduces xperm.* instructions.

[SForeKeeper]

Update comments in tablegen file.

[SForeKeeper]

Fixes faulty commit that removes previous commit.

[SForeKeeper]

Fixes incorrect update.

[craig.topper]

Please upload patches with full context using -U99999 as described here https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

432

"Float in Integer"?

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

9

This should be Zk not K. But since I think these should be in Zb. It doesn't really matter.

19

This extension name starts with Zb so I think it should be in RISCVInstrInfoZb.

llvm/test/MC/RISCV/rv32zbkx-valid.s

12

How do these get disassembled when Zbkx and Zbp are both enabled?

[VincentWu]

Revision Contents look weired. Does this patch upload by git diff -U99999?
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

9

agree, i also think it should be put to Zb

[VincentWu]

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

18

it will be better to organize it in the same order as RISCVSchedRocket.td

[SForeKeeper]

In D117889#3261763, @craig.topper wrote:

Please upload patches with full context using -U99999 as described here https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

Understood, will apply in next update. Since there are xperm.* instructions in RISCVInstrInfoZb.td, should them be removal since Zbp doesn't exist anymore?

[SForeKeeper]

Now xperm8 and xperm4 are aliases for xperm.* instructions in Zbp extension. They will be decoded to xperm8 and xperm4 when both extensions are enabled.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

742 ↗

(On Diff #402212)

I'd rename the instructions in Zbp to xperm4 and xperm8 and add xperm.n and xperm.b aliases for Zbp. If Zbp gets picked up in the future, the instructions will likely be renamed to match Zbkx.

llvm/test/MC/RISCV/attribute-arch.s

136

Blank line before to keep consistency.

[SForeKeeper]

Changed instrucions' name from xperm.* to xperm8 and xperm4 and use xperm.* as instruction aliases.
Now when both are enabled they would be decoded in Zbp format.

[craig.topper]

llvm/lib/Target/RISCV/RISCV.td

191

Replace 'B' with 'Zb'. I have a patch to fix the existing locations here D117822

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

20 ↗

(On Diff #402273)

Please add Zbkx to the header. I just pushed a commit to add a spot for Zbk* extensions.

741 ↗

(On Diff #402273)

I wouldn't speculate on whether Zbp will be ratified or not. Just say Zbp is unratified and that it would likely adopt the already ratified Zbkx names.

[craig.topper]

Please remove [RFC] from the title.

[SForeKeeper]

Fix comments.

[craig.topper]

LGTM

[VincentWu]

llvm/lib/Target/RISCV/RISCV.td

166

you may need rebase again and include zbxk into subTargeteature list of FeatureStdExtZks & FeatureStdExtZkn which is added in https://reviews.llvm.org/D98136.

llvm/test/CodeGen/RISCV/attributes.ll

93

same here

llvm/test/MC/RISCV/attribute-arch.s

135

again

[VincentWu]

llvm/lib/Target/RISCV/RISCV.td

166

*zbkx

[SForeKeeper]

Rebase and add Zbkx in Zks, Zkn.

llvm/lib/Support/RISCVISAInfo.cpp

     {"zbs", RISCVExtensionVersion{1, 0}},
 
     {"zbkb", RISCVExtensionVersion{1, 0}},
+    {"zbkx", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

       return MCDisassembler::Fail;
     }
     Insn = support::endian::read32le(Bytes.data());
+
+    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbkx]) {
+      LLVM_DEBUG(dbgs() << "Trying RVK table (Float in Integer):\n");
+      // Calling the auto-generated decoder function.
+      Result =
+          decodeInstruction(DecoderTableRVK32, MI, Insn, Address, this, STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
+
     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
     Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
     Size = 4;

llvm/lib/Target/RISCV/RISCV.td

                              AssemblerPredicate<(all_of FeatureStdExtZbkb),
                              "'Zbkb' (Bitmanip instructions for Cryptography)">;
 
+def FeatureStdExtZbkx
+    : SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
+                       "'Zbkx' (Crossbar permutation instructions)">;
+def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
+                             AssemblerPredicate<(all_of FeatureStdExtZbkx),
+                             "'Zbkx' (Crossbar permutation instructions)">;
+
 def HasStdExtZbpOrZbkb
     : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
                 AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb),

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoZb.td"
+include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

+//===-- RISCVInstrInfoZk.td - RISC-V 'Zk' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'K',
+// Cryptography Instructions extension, version 1.0.0
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "RVK" in {
+let Predicates = [HasStdExtZbkx] in {
+def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;
+def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;
+} // Predicates = [HasStdExtZbkx]
+} // DecoderNamespace = "RVK"

llvm/lib/Target/RISCV/RISCVSchedRocket.td

   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = false;
-  let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions, HasVInstructionsI64];
+  let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkx, HasVInstructions,
+                             HasVInstructionsI64];
 }
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 0;
-  let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions];
+  let UnsupportedFeatures = [HasStdExtZbkb, HasVInstructions, HasStdExtZbkx];
 }
 
 // The SiFive7 microarchitecture has two pipelines: A and B.

llvm/lib/Target/RISCV/RISCVSubtarget.h

   bool HasStdExtZfhmin = false;
   bool HasStdExtZfh = false;
   bool HasStdExtZbkb = false;
+  bool HasStdExtZbkx = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;

   bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool hasStdExtZbkb() const { return HasStdExtZbkb; }
+  bool hasStdExtZbkx() const { return HasStdExtZbkx; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zbkx %s -o - | FileCheck --check-prefix=RV32ZBKX %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s

 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s
-
+; RUN: llc -mtriple=riscv64 -mattr=+zbkx %s -o - | FileCheck --check-prefix=RV64ZBKX %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"

 ; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
+; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"

 ; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 ; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
+; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1

llvm/test/MC/RISCV/attribute-arch.s

 
 .attribute arch, "rv32i_zbkb1p0"
 # CHECK: attribute      5, "rv32i2p0_zbkb1p0"
+
+.attribute arch, "rv32i_zbkx1p0"
+# CHECK: attribute      5, "rv32i2p0_zbkx1p0"

llvm/test/MC/RISCV/rv32zbkx-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbkx -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbkx -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=zbkx < %s \
+# RUN:     | llvm-objdump --mattr=+zbkx -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=zbkx < %s \
+# RUN:     | llvm-objdump --mattr=+zbkx -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: xperm8 t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28]
+xperm8 t0, t1, t2
+# CHECK-ASM-AND-OBJ: xperm4 t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x28]
+xperm4 t0, t1, t2