[RISCV] [NFC] Add a function to customLegalizeToWOp by Intrinsic

[Chenbing.Zheng]

Summary

These cases follows the same pattern，add a function to do it.

[Chenbing.Zheng]

modify CASE_EXTEND_TWO_OPERAND to CASE_EXTEND_TWO_OPERANDS

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

6288–6297

Would a helper function be better?

[Chenbing.Zheng]

use a helper function instead of macro

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5760

I think "Intrinsic" is typically shortened to either "Intrin" or "Intr". I don't recall seeing "Intri" anywhere.

[Chenbing.Zheng]

modify Intri to Intr

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5760

Thanks, I will modify it and pay more attention

[craig.topper]

LGTM with that one comment

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5779

This line needs to be reformatted to decrease indentation after the rename.

[benshi001]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5779

I will correct that format issue when help him commiting.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op,
   SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT,
                                 DAG.getConstant(Table, DL, XLenVT), Shift);
   RMValue = DAG.getNode(ISD::AND, DL, XLenVT, Shifted,
                         DAG.getConstant(0x7, DL, XLenVT));
   return DAG.getNode(RISCVISD::WRITE_CSR, DL, MVT::Other, Chain, SysRegNo,
                      RMValue);
 }
 
 // Returns the opcode of the target-specific SDNode that implements the 32-bit
 // form of the given Opcode.
 static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
   switch (Opcode) {
   default:
     llvm_unreachable("Unexpected opcode");
   case ISD::SHL:
     return RISCVISD::SLLW;
   case ISD::SRA:
     return RISCVISD::SRAW;
   case ISD::SRL:
     return RISCVISD::SRLW;
   case ISD::SDIV:
     return RISCVISD::DIVW;
   case ISD::UDIV:
     return RISCVISD::DIVUW;
   case ISD::UREM:
     return RISCVISD::REMUW;
   case ISD::ROTL:
     return RISCVISD::ROLW;
   case ISD::ROTR:
     return RISCVISD::RORW;
   case RISCVISD::GREV:
     return RISCVISD::GREVW;
   case RISCVISD::GORC:
     return RISCVISD::GORCW;
   }
 }
case Intrinsic::riscv_orc_b: {
       // If Zbp is enabled, use GORCIW which will sign extend the result.
       unsigned Opc =
           Subtarget.hasStdExtZbp() ? RISCVISD::GORCW : RISCVISD::GORC;
       SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp,
                                 DAG.getConstant(7, DL, MVT::i64));
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       return;
     }
-    case Intrinsic::riscv_grev:
-    case Intrinsic::riscv_gorc: {
-      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
-             "Unexpected custom legalisation");
-      SDValue NewOp1 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue NewOp2 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
-      unsigned Opc =
-          IntNo == Intrinsic::riscv_grev ? RISCVISD::GREVW : RISCVISD::GORCW;
-      SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
-      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
-      break;
-    }
     case Intrinsic::riscv_shfl:
     case Intrinsic::riscv_unshfl: {
       assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
              "Unexpected custom legalisation");
       SDValue NewOp1 =
           DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
       SDValue NewOp2 =
           DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
       unsigned Opc =
           IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFLW : RISCVISD::UNSHFLW;
       if (isa<ConstantSDNode>(N->getOperand(2))) {
         NewOp2 = DAG.getNode(ISD::AND, DL, MVT::i64, NewOp2,
                              DAG.getConstant(0xf, DL, MVT::i64));
         Opc =
             IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
       }
       SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       break;
     }
-    case Intrinsic::riscv_bcompress:
-    case Intrinsic::riscv_bdecompress: {
-      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
-             "Unexpected custom legalisation");
-      SDValue NewOp1 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue NewOp2 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
-      unsigned Opc = IntNo == Intrinsic::riscv_bcompress
-                         ? RISCVISD::BCOMPRESSW
-                         : RISCVISD::BDECOMPRESSW;
-      SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
-      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
-      break;
-    }
-    case Intrinsic::riscv_bfp: {
-      assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
-             "Unexpected custom legalisation");
-      SDValue NewOp1 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
-      SDValue NewOp2 =
-          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
-      SDValue Res = DAG.getNode(RISCVISD::BFPW, DL, MVT::i64, NewOp1, NewOp2);
-      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
-      break;
-    }
     case Intrinsic::riscv_vmv_x_s: {
       EVT VT = N->getValueType(0);
       MVT XLenVT = Subtarget.getXLenVT();
       if (VT.bitsLT(XLenVT)) {
         // Simple case just extract using vmv.x.s and truncate.
         SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL,
                                       Subtarget.getXLenVT(), N->getOperand(1));
         Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract));
case Intrinsic::riscv_vmv_x_s: {
       SDValue LShr32 =
           DAG.getNode(RISCVISD::SRL_VL, DL, VecVT, Vec, ThirtyTwoV, Mask, VL);
       SDValue EltHi = DAG.getNode(RISCVISD::VMV_X_S, DL, XLenVT, LShr32);
 
       Results.push_back(
           DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi));
       break;
     }
-    }
-    break;
+#define CASE_EXTEND_TWO_OPERAND(intrinsic, opcode)                             \
+  case Intrinsic::intrinsic: {                                                 \
+    assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&            \
+           "Unexpected custom legalisation");                                  \
+    SDValue NewOp1 =                                                           \
+        DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));          \
+    SDValue NewOp2 =                                                           \
+        DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));          \
+    SDValue Res = DAG.getNode(RISCVISD::opcode, DL, MVT::i64, NewOp1, NewOp2); \
+    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));          \
+    break;
+    }
+    CASE_EXTEND_TWO_OPERAND(riscv_grev, GREVW)
+    CASE_EXTEND_TWO_OPERAND(riscv_gorc, GORCW)
+    CASE_EXTEND_TWO_OPERAND(riscv_bcompress, BCOMPRESSW)
+    CASE_EXTEND_TWO_OPERAND(riscv_bdecompress, BDECOMPRESSW)
+    CASE_EXTEND_TWO_OPERAND(riscv_bfp, BFPW)
+#undef CASE_EXTEND_TWO_OPERAND
+  } break;
   }
   case ISD::VECREDUCE_ADD:
   case ISD::VECREDUCE_AND:
   case ISD::VECREDUCE_OR:
   case ISD::VECREDUCE_XOR:
   case ISD::VECREDUCE_SMAX:
   case ISD::VECREDUCE_UMAX:
   case ISD::VECREDUCE_SMIN: