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Differential D117377

[RISCV] Legalize fixed length (insert_subvector undef, X, 0) to a scalable insert.
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Authored by craig.topper on Jan 14 2022, 6:03 PM.

Details

Reviewers
frasercrmck
Commits
rG9c410838d2bc: [RISCV] Legalize fixed length (insert_subvector undef, X, 0) to a scalable…
Summary

We were considering this legal, but later the undef would become an all
zeros vector. This would cause us to need to re-legalize the insert later
into a vslideup with zero vector.

This patch catches the case and directly legalizes it to a scalable
insert.

Diff Detail

Unit TestsFailed

TimeTest
1,000 msx64 debian > SanitizerCommon-tsan-x86_64-Linux.Linux::decorate_proc_maps.cpp

Event Timeline

craig.topper created this revision.Jan 14 2022, 6:03 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 26 others. · View Herald TranscriptJan 14 2022, 6:03 PM
craig.topper requested review of this revision.Jan 14 2022, 6:03 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2022, 6:03 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B143545: Diff 400216.Jan 14 2022, 6:47 PM
frasercrmck accepted this revision.Jan 17 2022, 3:50 AM

LGTM, cheers

This revision is now accepted and ready to land.Jan 17 2022, 3:50 AM
Herald added subscribers: alextsao1999, eopXD. · View Herald TranscriptJan 17 2022, 3:50 AM
This revision was landed with ongoing or failed builds.Jan 17 2022, 2:40 PM
Closed by commit rG9c410838d2bc: [RISCV] Legalize fixed length (insert_subvector undef, X, 0) to a scalable… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG9c410838d2bc: [RISCV] Legalize fixed length (insert_subvector undef, X, 0) to a scalable….

Revision Contents

Diff 400216

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===// //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation --------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 4,810 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
} }
// If the subvector vector is a fixed-length type, we cannot use subregister // If the subvector vector is a fixed-length type, we cannot use subregister
// manipulation to simplify the codegen; we don't know which register of a // manipulation to simplify the codegen; we don't know which register of a
// LMUL group contains the specific subvector as we only know the minimum // LMUL group contains the specific subvector as we only know the minimum
// register size. Therefore we must slide the vector group up the full // register size. Therefore we must slide the vector group up the full
// amount. // amount.
if (SubVecVT.isFixedLengthVector()) { if (SubVecVT.isFixedLengthVector()) {
if (OrigIdx == 0 && Vec.isUndef()) if (OrigIdx == 0 && Vec.isUndef() && !VecVT.isFixedLengthVector())
return Op; return Op;
MVT ContainerVT = VecVT; MVT ContainerVT = VecVT;
if (VecVT.isFixedLengthVector()) { if (VecVT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(VecVT); ContainerVT = getContainerForFixedLengthVector(VecVT);
Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget); Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget);
} }
SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), SubVec, DAG.getUNDEF(ContainerVT), SubVec,
DAG.getConstant(0, DL, XLenVT)); DAG.getConstant(0, DL, XLenVT));
if (OrigIdx == 0 && Vec.isUndef() && VecVT.isFixedLengthVector()) {
SubVec = convertFromScalableVector(VecVT, SubVec, DAG, Subtarget);
return DAG.getBitcast(Op.getValueType(), SubVec);
}
SDValue Mask = SDValue Mask =
getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).first; getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget).first;
// Set the vector length to only the number of elements we care about. Note // Set the vector length to only the number of elements we care about. Note
// that for slideup this includes the offset. // that for slideup this includes the offset.
SDValue VL = SDValue VL =
DAG.getConstant(OrigIdx + SubVecVT.getVectorNumElements(), DL, XLenVT); DAG.getConstant(OrigIdx + SubVecVT.getVectorNumElements(), DL, XLenVT);
SDValue SlideupAmt = DAG.getConstant(OrigIdx, DL, XLenVT); SDValue SlideupAmt = DAG.getConstant(OrigIdx, DL, XLenVT);
SDValue Slideup = DAG.getNode(RISCVISD::VSLIDEUP_VL, DL, ContainerVT, Vec, SDValue Slideup = DAG.getNode(RISCVISD::VSLIDEUP_VL, DL, ContainerVT, Vec,
▲ Show 20 Lines • Show All 5,801 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

Show First 20 Lines • Show All 841 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
%z = zext <8 x i16> %y to <8 x i64> %z = zext <8 x i16> %y to <8 x i64>
ret <8 x i64> %z ret <8 x i64> %z
} }
define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %z) { define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i16_v16i8: ; LMULMAX1-LABEL: truncstore_v16i16_v16i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 8
; LMULMAX1-NEXT: vse8.v v10, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i16_v16i8: ; LMULMAX4-LABEL: truncstore_v16i16_v16i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX4-NEXT: vse8.v v10, (a0) ; LMULMAX4-NEXT: vse8.v v10, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
▲ Show 20 Lines • Show All 289 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
%z = zext <4 x i32> %y to <4 x i64> %z = zext <4 x i32> %y to <4 x i64>
ret <4 x i64> %z ret <4 x i64> %z
} }
define void @truncstore_v8i32_v8i8(<8 x i32> %x, <8 x i8>* %z) { define void @truncstore_v8i32_v8i8(<8 x i32> %x, <8 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v8i32_v8i8: ; LMULMAX1-LABEL: truncstore_v8i32_v8i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vse8.v v10, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i32_v8i8: ; LMULMAX4-LABEL: truncstore_v8i32_v8i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i32> %x to <8 x i8> %y = trunc <8 x i32> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z store <8 x i8> %y, <8 x i8>* %z
ret void ret void
} }
define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %z) { define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v8i32_v8i16: ; LMULMAX1-LABEL: truncstore_v8i32_v8i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vse16.v v10, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i32_v8i16: ; LMULMAX4-LABEL: truncstore_v8i32_v8i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX4-NEXT: vse16.v v10, (a0) ; LMULMAX4-NEXT: vse16.v v10, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; LMULMAX4-NEXT: ret
%z = zext <8 x i32> %y to <8 x i64> %z = zext <8 x i32> %y to <8 x i64>
ret <8 x i64> %z ret <8 x i64> %z
} }
define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %z) { define void @truncstore_v16i32_v16i8(<16 x i32> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i32_v16i8: ; LMULMAX1-LABEL: truncstore_v16i32_v16i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 12 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 12
; LMULMAX1-NEXT: vse8.v v12, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i32_v16i8: ; LMULMAX4-LABEL: truncstore_v16i32_v16i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i32> %x to <16 x i8> %y = trunc <16 x i32> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z store <16 x i8> %y, <16 x i8>* %z
ret void ret void
} }
define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %z) { define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v16i32_v16i16: ; LMULMAX1-LABEL: truncstore_v16i32_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vmv1r.v v13, v12
; LMULMAX1-NEXT: vslideup.vi v13, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v13, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v12, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: vse16.v v13, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i32_v16i16: ; LMULMAX4-LABEL: truncstore_v16i32_v16i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vse16.v v12, (a0) ; LMULMAX4-NEXT: vse16.v v12, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
store <2 x i32> %y, <2 x i32>* %z store <2 x i32> %y, <2 x i32>* %z
ret void ret void
} }
define void @truncstore_v4i64_v4i8(<4 x i64> %x, <4 x i8>* %z) { define void @truncstore_v4i64_v4i8(<4 x i64> %x, <4 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i8: ; LMULMAX1-LABEL: truncstore_v4i64_v4i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf4, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vse8.v v10, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v4i64_v4i8: ; LMULMAX4-LABEL: truncstore_v4i64_v4i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i8> %y = trunc <4 x i64> %x to <4 x i8>
store <4 x i8> %y, <4 x i8>* %z store <4 x i8> %y, <4 x i8>* %z
ret void ret void
} }
define void @truncstore_v4i64_v4i16(<4 x i64> %x, <4 x i16>* %z) { define void @truncstore_v4i64_v4i16(<4 x i64> %x, <4 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i16: ; LMULMAX1-LABEL: truncstore_v4i64_v4i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vse16.v v10, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v4i64_v4i16: ; LMULMAX4-LABEL: truncstore_v4i64_v4i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i16> %y = trunc <4 x i64> %x to <4 x i16>
store <4 x i16> %y, <4 x i16>* %z store <4 x i16> %y, <4 x i16>* %z
ret void ret void
} }
define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %z) { define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i32: ; LMULMAX1-LABEL: truncstore_v4i64_v4i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vse32.v v10, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v4i64_v4i32: ; LMULMAX4-LABEL: truncstore_v4i64_v4i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v10, v8, 0
; LMULMAX4-NEXT: vse32.v v10, (a0) ; LMULMAX4-NEXT: vse32.v v10, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i32> %y = trunc <4 x i64> %x to <4 x i32>
store <4 x i32> %y, <4 x i32>* %z store <4 x i32> %y, <4 x i32>* %z
ret void ret void
} }
define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %z) { define void @truncstore_v8i64_v8i8(<8 x i64> %x, <8 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i8: ; LMULMAX1-LABEL: truncstore_v8i64_v8i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vse8.v v12, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i64_v8i8: ; LMULMAX4-LABEL: truncstore_v8i64_v8i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i8> %y = trunc <8 x i64> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z store <8 x i8> %y, <8 x i8>* %z
ret void ret void
} }
define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %z) { define void @truncstore_v8i64_v8i16(<8 x i64> %x, <8 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i16: ; LMULMAX1-LABEL: truncstore_v8i64_v8i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vse16.v v12, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i64_v8i16: ; LMULMAX4-LABEL: truncstore_v8i64_v8i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v12, 0
; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i16> %y = trunc <8 x i64> %x to <8 x i16>
store <8 x i16> %y, <8 x i16>* %z store <8 x i16> %y, <8 x i16>* %z
ret void ret void
} }
define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %z) { define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i32: ; LMULMAX1-LABEL: truncstore_v8i64_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; LMULMAX1-NEXT: vmv1r.v v13, v12
; LMULMAX1-NEXT: vslideup.vi v13, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v13, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 2
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v12, (a1) ; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: vse32.v v13, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i64_v8i32: ; LMULMAX4-LABEL: truncstore_v8i64_v8i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vse32.v v12, (a0) ; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i32> %y = trunc <8 x i64> %x to <8 x i32>
store <8 x i32> %y, <8 x i32>* %z store <8 x i32> %y, <8 x i32>* %z
ret void ret void
} }
define void @truncstore_v16i64_v16i8(<16 x i64> %x, <16 x i8>* %z) { define void @truncstore_v16i64_v16i8(<16 x i64> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i8: ; LMULMAX1-LABEL: truncstore_v16i64_v16i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v16, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v16, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
Show All 40 Lines
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 14 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 14
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i64_v16i8: ; LMULMAX4-LABEL: truncstore_v16i64_v16i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v16, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v16, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v16, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v12, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX4-NEXT: vmv.v.i v9, 0 ; LMULMAX4-NEXT: vnsrl.wi v14, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e8, m1, tu, mu
; LMULMAX4-NEXT: vslideup.vi v9, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v10, v12, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v14, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, tu, mu
; LMULMAX4-NEXT: vslideup.vi v9, v8, 8 ; LMULMAX4-NEXT: vslideup.vi v8, v12, 8
; LMULMAX4-NEXT: vse8.v v9, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i8> %y = trunc <16 x i64> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z store <16 x i8> %y, <16 x i8>* %z
ret void ret void
} }
define void @truncstore_v16i64_v16i16(<16 x i64> %x, <16 x i16>* %z) { define void @truncstore_v16i64_v16i16(<16 x i64> %x, <16 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i16: ; LMULMAX1-LABEL: truncstore_v16i64_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v16, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; LMULMAX1-NEXT: vmv1r.v v17, v16
; LMULMAX1-NEXT: vslideup.vi v17, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v17, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v17, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v17, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v12, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v13, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v16, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v13, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v16, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v14, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v14, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v16, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v15, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v15, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v16, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 6
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v16, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: vse16.v v17, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i64_v16i16: ; LMULMAX4-LABEL: truncstore_v16i64_v16i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0 ; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v12, v16, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v16, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v14, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v14, v8, 0
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v8, v14, 0 ; LMULMAX4-NEXT: vnsrl.wi v8, v14, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX4-NEXT: vmv.v.i v10, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m2, tu, mu
; LMULMAX4-NEXT: vslideup.vi v10, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, tu, mu
; LMULMAX4-NEXT: vslideup.vi v10, v12, 8 ; LMULMAX4-NEXT: vslideup.vi v8, v12, 8
; LMULMAX4-NEXT: vse16.v v10, (a0) ; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i16> %y = trunc <16 x i64> %x to <16 x i16>
store <16 x i16> %y, <16 x i16>* %z store <16 x i16> %y, <16 x i16>* %z
ret void ret void
} }
define void @truncstore_v16i64_v16i32(<16 x i64> %x, <16 x i32>* %z) { define void @truncstore_v16i64_v16i32(<16 x i64> %x, <16 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i32: ; LMULMAX1-LABEL: truncstore_v16i64_v16i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vmv.v.i v16, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; LMULMAX1-NEXT: vmv1r.v v17, v16
; LMULMAX1-NEXT: vslideup.vi v17, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v17, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; LMULMAX1-NEXT: vmv1r.v v9, v16
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v11, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; LMULMAX1-NEXT: vmv1r.v v10, v16
; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v13, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v13, 0
; LMULMAX1-NEXT: vnsrl.wi v11, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v11, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v14, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v15, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; LMULMAX1-NEXT: vnsrl.wi v12, v14, 0
; LMULMAX1-NEXT: vslideup.vi v16, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v15, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v16, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v12, v9, 2
; LMULMAX1-NEXT: addi a1, a0, 48 ; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vse32.v v16, (a1) ; LMULMAX1-NEXT: vse32.v v12, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32 ; LMULMAX1-NEXT: addi a1, a0, 32
; LMULMAX1-NEXT: vse32.v v10, (a1) ; LMULMAX1-NEXT: vse32.v v11, (a1)
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v9, (a1) ; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: vse32.v v17, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i64_v16i32: ; LMULMAX4-LABEL: truncstore_v16i64_v16i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0 ; LMULMAX4-NEXT: vnsrl.wi v16, v12, 0
; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0 ; LMULMAX4-NEXT: vnsrl.wi v12, v8, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: vmv.v.i v8, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m4, tu, mu
; LMULMAX4-NEXT: vslideup.vi v8, v12, 0
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, tu, mu
; LMULMAX4-NEXT: vslideup.vi v8, v16, 8 ; LMULMAX4-NEXT: vslideup.vi v12, v16, 8
; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i32> %y = trunc <16 x i64> %x to <16 x i32>
store <16 x i32> %y, <16 x i32>* %z store <16 x i32> %y, <16 x i32>* %z
ret void ret void
} }
define <vscale x 2 x float> @extload_nxv2f16_nxv2f32(<vscale x 2 x half>* %x) { define <vscale x 2 x float> @extload_nxv2f16_nxv2f32(<vscale x 2 x half>* %x) {
; CHECK-LABEL: extload_nxv2f16_nxv2f32: ; CHECK-LABEL: extload_nxv2f16_nxv2f32:
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

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; LMULMAX8-NEXT: vle32.v v8, (a0) ; LMULMAX8-NEXT: vle32.v v8, (a0)
; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX8-NEXT: vfncvt.f.f.w v10, v8 ; LMULMAX8-NEXT: vfncvt.f.f.w v10, v8
; LMULMAX8-NEXT: vse16.v v10, (a1) ; LMULMAX8-NEXT: vse16.v v10, (a1)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fpround_v8f32_v8f16: ; LMULMAX1-LABEL: fpround_v8f32_v8f16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, a0, 16
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: vle32.v v9, (a2)
; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v10, v8 ; LMULMAX1-NEXT: vfncvt.f.f.w v10, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v10, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v8, v10, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 4
; LMULMAX1-NEXT: vse16.v v8, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x %a = load <8 x float>, <8 x float>* %x
%d = fptrunc <8 x float> %a to <8 x half> %d = fptrunc <8 x float> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }
define void @fpround_v8f64_v8f16(<8 x double>* %x, <8 x half>* %y) { define void @fpround_v8f64_v8f16(<8 x double>* %x, <8 x half>* %y) {
Show All 17 Lines
; LMULMAX1-NEXT: vle64.v v9, (a2) ; LMULMAX1-NEXT: vle64.v v9, (a2)
; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v10 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12 ; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v11, v10 ; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v10, v9 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v9, v10 ; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v9, v8 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse16.v v12, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%d = fptrunc <8 x double> %a to <8 x half> %d = fptrunc <8 x double> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

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; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v10, v8 ; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v10, v8
; LMULMAX8-NEXT: vand.vi v8, v10, 1 ; LMULMAX8-NEXT: vand.vi v8, v10, 1
; LMULMAX8-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX8-NEXT: vmsne.vi v0, v8, 0
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fp2si_v8f32_v8i1: ; LMULMAX1-LABEL: fp2si_v8f32_v8i1:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmclr.m v0
; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vmerge.vim v11, v10, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v8 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v8
; LMULMAX1-NEXT: vand.vi v8, v12, 1 ; LMULMAX1-NEXT: vand.vi v8, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v11, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v11, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v11, v9 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v9
; LMULMAX1-NEXT: vand.vi v9, v11, 1 ; LMULMAX1-NEXT: vand.vi v9, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%z = fptosi <8 x float> %x to <8 x i1> %z = fptosi <8 x float> %x to <8 x i1>
ret <8 x i1> %z ret <8 x i1> %z
} }
define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) { define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) {
; LMULMAX8-LABEL: fp2ui_v8f32_v8i1: ; LMULMAX8-LABEL: fp2ui_v8f32_v8i1:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v10, v8
; LMULMAX8-NEXT: vand.vi v8, v10, 1 ; LMULMAX8-NEXT: vand.vi v8, v10, 1
; LMULMAX8-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX8-NEXT: vmsne.vi v0, v8, 0
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fp2ui_v8f32_v8i1: ; LMULMAX1-LABEL: fp2ui_v8f32_v8i1:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmclr.m v0
; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vmerge.vim v11, v10, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v8
; LMULMAX1-NEXT: vand.vi v8, v12, 1 ; LMULMAX1-NEXT: vand.vi v8, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v11, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v11, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v11, v9 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v9
; LMULMAX1-NEXT: vand.vi v9, v11, 1 ; LMULMAX1-NEXT: vand.vi v9, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%z = fptoui <8 x float> %x to <8 x i1> %z = fptoui <8 x float> %x to <8 x i1>
ret <8 x i1> %z ret <8 x i1> %z
} }
define void @fp2si_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) { define void @fp2si_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) {
; CHECK-LABEL: fp2si_v2f32_v2i64: ; CHECK-LABEL: fp2si_v2f32_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v10 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v11, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v11, v11, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v10, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v9 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v9, v8 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse8.v v12, (a1) ; LMULMAX1-NEXT: vse8.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%d = fptosi <8 x double> %a to <8 x i8> %d = fptosi <8 x double> %a to <8 x i8>
store <8 x i8> %d, <8 x i8>* %y store <8 x i8> %d, <8 x i8>* %y
ret void ret void
} }
define void @fp2ui_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) { define void @fp2ui_v8f64_v8i8(<8 x double>* %x, <8 x i8>* %y) {
Show All 21 Lines
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v10 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0 ; LMULMAX1-NEXT: vnsrl.wi v10, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v11, v12, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v10, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v11, v11, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v10, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v9 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v11, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse8.v v12, (a1) ; LMULMAX1-NEXT: vse8.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%d = fptoui <8 x double> %a to <8 x i8> %d = fptoui <8 x double> %a to <8 x i8>
store <8 x i8> %d, <8 x i8>* %y store <8 x i8> %d, <8 x i8>* %y
ret void ret void
} }
define <8 x i1> @fp2si_v8f64_v8i1(<8 x double> %x) { define <8 x i1> @fp2si_v8f64_v8i1(<8 x double> %x) {
; LMULMAX8-LABEL: fp2si_v8f64_v8i1: ; LMULMAX8-LABEL: fp2si_v8f64_v8i1:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v12, v8 ; LMULMAX8-NEXT: vfncvt.rtz.x.f.w v12, v8
; LMULMAX8-NEXT: vand.vi v8, v12, 1 ; LMULMAX8-NEXT: vand.vi v8, v12, 1
; LMULMAX8-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX8-NEXT: vmsne.vi v0, v8, 0
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fp2si_v8f64_v8i1: ; LMULMAX1-LABEL: fp2si_v8f64_v8i1:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmclr.m v0
; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v14, v8 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v8
; LMULMAX1-NEXT: vand.vi v8, v14, 1 ; LMULMAX1-NEXT: vand.vi v8, v12, 1
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v14, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v13, v14, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v13, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v14, v9 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v9
; LMULMAX1-NEXT: vand.vi v9, v14, 1 ; LMULMAX1-NEXT: vand.vi v9, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v9, v8, 1, v0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v13, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v13, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v12, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v13, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v10 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v10
; LMULMAX1-NEXT: vand.vi v10, v13, 1 ; LMULMAX1-NEXT: vand.vi v10, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v10, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v10, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v10, 4 ; LMULMAX1-NEXT: vslideup.vi v12, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v11 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v11
; LMULMAX1-NEXT: vand.vi v10, v10, 1 ; LMULMAX1-NEXT: vand.vi v10, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%z = fptosi <8 x double> %x to <8 x i1> %z = fptosi <8 x double> %x to <8 x i1>
ret <8 x i1> %z ret <8 x i1> %z
} }
define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) { define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) {
; LMULMAX8-LABEL: fp2ui_v8f64_v8i1: ; LMULMAX8-LABEL: fp2ui_v8f64_v8i1:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v12, v8 ; LMULMAX8-NEXT: vfncvt.rtz.xu.f.w v12, v8
; LMULMAX8-NEXT: vand.vi v8, v12, 1 ; LMULMAX8-NEXT: vand.vi v8, v12, 1
; LMULMAX8-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX8-NEXT: vmsne.vi v0, v8, 0
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: fp2ui_v8f64_v8i1: ; LMULMAX1-LABEL: fp2ui_v8f64_v8i1:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmclr.m v0
; LMULMAX1-NEXT: vmv.v.i v12, 0
; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v14, v8 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v8
; LMULMAX1-NEXT: vand.vi v8, v14, 1 ; LMULMAX1-NEXT: vand.vi v8, v12, 1
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v14, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v13, v14, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v13, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v13, v12, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v14, v9 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v9
; LMULMAX1-NEXT: vand.vi v9, v14, 1 ; LMULMAX1-NEXT: vand.vi v9, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v9, v8, 1, v0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v13, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v13, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v12, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v13, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v10 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v10
; LMULMAX1-NEXT: vand.vi v10, v13, 1 ; LMULMAX1-NEXT: vand.vi v10, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v10, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v10, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v10, 4 ; LMULMAX1-NEXT: vslideup.vi v12, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vmerge.vim v9, v12, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v11 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v11
; LMULMAX1-NEXT: vand.vi v10, v10, 1 ; LMULMAX1-NEXT: vand.vi v10, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%z = fptoui <8 x double> %x to <8 x i1> %z = fptoui <8 x double> %x to <8 x i1>
ret <8 x i1> %z ret <8 x i1> %z
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

Show First 20 Lines • Show All 472 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vle64.v v9, (a2) ; LMULMAX1-NEXT: vle64.v v9, (a2)
; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v12, v10 ; LMULMAX1-NEXT: vfncvt.f.x.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12 ; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vfncvt.f.x.w v12, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v11, v10 ; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v10, v9 ; LMULMAX1-NEXT: vfncvt.f.x.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v9, v10 ; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v9, v8 ; LMULMAX1-NEXT: vfncvt.f.x.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse16.v v12, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%d = sitofp <8 x i64> %a to <8 x half> %d = sitofp <8 x i64> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }
define void @ui2fp_v8i64_v8f16(<8 x i64>* %x, <8 x half>* %y) { define void @ui2fp_v8i64_v8f16(<8 x i64>* %x, <8 x half>* %y) {
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; LMULMAX1-NEXT: vle64.v v9, (a2) ; LMULMAX1-NEXT: vle64.v v9, (a2)
; LMULMAX1-NEXT: vle64.v v10, (a0) ; LMULMAX1-NEXT: vle64.v v10, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle64.v v11, (a0) ; LMULMAX1-NEXT: vle64.v v11, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v12, v10 ; LMULMAX1-NEXT: vfncvt.f.xu.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12 ; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v12, 0 ; LMULMAX1-NEXT: vfncvt.f.xu.w v12, v11
; LMULMAX1-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v10, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v10, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v11, v10 ; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v10, v9 ; LMULMAX1-NEXT: vfncvt.f.xu.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v9, v10 ; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v9, v8 ; LMULMAX1-NEXT: vfncvt.f.xu.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v12, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse16.v v12, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%d = uitofp <8 x i64> %a to <8 x half> %d = uitofp <8 x i64> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }
define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) { define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

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} }
define void @insert_v4i32_undef_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v4i32_undef_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) {
; CHECK-LABEL: insert_v4i32_undef_v2i32_0: ; CHECK-LABEL: insert_v4i32_undef_v2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0) %v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0)
store <4 x i32> %v, <4 x i32>* %vp store <4 x i32> %v, <4 x i32>* %vp
ret void ret void
} }
define void @insert_v8i32_v2i32_0(<8 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v8i32_v2i32_0(<8 x i32>* %vp, <2 x i32>* %svp) {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

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; The align keeps the type legalizer from using a 256 bit load so we must split ; The align keeps the type legalizer from using a 256 bit load so we must split
; it. This some operations that weren't support for scalable vectors when ; it. This some operations that weren't support for scalable vectors when
; this test was written. ; this test was written.
define void @insertelt_v3i64(<3 x i64>* %x, i64 %y) { define void @insertelt_v3i64(<3 x i64>* %x, i64 %y) {
; RV32-LABEL: insertelt_v3i64: ; RV32-LABEL: insertelt_v3i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, mu
; RV32-NEXT: vslideup.vi v10, v8, 0
; RV32-NEXT: lw a3, 16(a0) ; RV32-NEXT: lw a3, 16(a0)
; RV32-NEXT: addi a4, a0, 20 ; RV32-NEXT: addi a4, a0, 20
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vlse32.v v8, (a4), zero ; RV32-NEXT: vlse32.v v10, (a4), zero
; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV32-NEXT: vmv.s.x v8, a3 ; RV32-NEXT: vmv.s.x v10, a3
; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; RV32-NEXT: vslideup.vi v10, v8, 2 ; RV32-NEXT: vslideup.vi v8, v10, 2
; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu
; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vslide1up.vx v12, v8, a2 ; RV32-NEXT: vslide1up.vx v12, v10, a2
; RV32-NEXT: vslide1up.vx v8, v12, a1 ; RV32-NEXT: vslide1up.vx v10, v12, a1
; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu ; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu
; RV32-NEXT: vslideup.vi v10, v8, 2 ; RV32-NEXT: vslideup.vi v8, v10, 2
; RV32-NEXT: sw a1, 16(a0) ; RV32-NEXT: sw a1, 16(a0)
; RV32-NEXT: sw a2, 20(a0) ; RV32-NEXT: sw a2, 20(a0)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vse64.v v10, (a0) ; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_v3i64: ; RV64-LABEL: insertelt_v3i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: sd a1, 16(a0) ; RV64-NEXT: sd a1, 16(a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <3 x i64>, <3 x i64>* %x, align 8 %a = load <3 x i64>, <3 x i64>* %x, align 8
%b = insertelement <3 x i64> %a, i64 %y, i32 2 %b = insertelement <3 x i64> %a, i64 %y, i32 2
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

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; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vnsrl.wi v8, v8, 0 ; LMULMAX1-NEXT: vnsrl.wi v9, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vse8.v v10, (a1) ; LMULMAX1-NEXT: vse8.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x %a = load <8 x i32>, <8 x i32>* %x
%b = trunc <8 x i32> %a to <8 x i8> %b = trunc <8 x i32> %a to <8 x i8>
store <8 x i8> %b, <8 x i8>* %z store <8 x i8> %b, <8 x i8>* %z
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

Show First 20 Lines • Show All 2,167 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_v32i8: ; RV64-LABEL: mgather_baseidx_v32i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vmv1r.v v12, v10
; RV64-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, mu ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, mu
; RV64-NEXT: vslidedown.vi v14, v10, 16 ; RV64-NEXT: vslidedown.vi v10, v10, 16
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v24, v16 ; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v14, (a0), v24, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vmv1r.v v0, v12
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: li a0, 32 ; RV64-NEXT: li a0, 32
; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vsetivli zero, 16, e8, m2, tu, mu
; RV64-NEXT: vslideup.vi v8, v10, 0
; RV64-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; RV64-NEXT: vsetvli zero, a0, e8, m2, tu, mu
; RV64-NEXT: vslideup.vi v8, v14, 16 ; RV64-NEXT: vslideup.vi v12, v10, 16
; RV64-NEXT: vmv2r.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs %ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs
%v = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> %ptrs, i32 2, <32 x i1> %m, <32 x i8> %passthru) %v = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> %ptrs, i32 2, <32 x i1> %m, <32 x i8> %passthru)
ret <32 x i8> %v ret <32 x i8> %v
} }