[RISCV] Initial support .insn directive for the assembler.

[craig.topper]

Summary

This allows for a custom encoding to be emitted. It can also be
used with inline assembly to allow the custom instruction to be
register allocated like other instructions.

I initially started from SystemZ's implementation, but some of
the formats allow operands to be specified in multiple ways so I
had to add support for matching different operand class lists for
the same format. That implementation is a simplified version of
what is emitted by tablegen for regular instructions.

I've left out the compressed formats. And I haven't supported the
named opcodes like LUI or OP_IMM_32. Those can be added in future
patches.

Documentation can be found here https://sourceware.org/binutils/docs-2.37/as/RISC_002dV_002dFormats.html

[craig.topper]

Remove stray SystemZ changes.

[craig.topper]

Remove debug print

[craig.topper]

Rebase

[jrtc27]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2267

I guess MCK__40_ is because of '(' in ASCII... not immediately obvious

2323

Does this not mean you can't, say, have .insn b with a symbol whose name happens to be a register? This seems like it needs to pay more attention to Kind.

2341

Unfortunately it *doesn't* have that first comma, it's a bit ugly like that, though I can see why that was chosen

2353

Plural?

2425

No assignment here, no double parens needed

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1450

Hm, MC stuff is at the top, then CodeGen patterns+pseudos, not sure whether I like having them here or not, but I can see the argument for it, they're their own separate thing...

1474

isCodeGenOnly should be 0 and isAsmParserOnly should be 1, surely?

1479

You could factor out the ".insn X" bit into the directive's class so this just provides an argstr. Also do we want a tab anywhere in the string (either before or after the type) or not?

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2267

Yep. I'll add a comment.

2323

Is that an existing bug in instruction parsing?

2341

Yeah, that was copied from SystemZ where I started this patch from before it snowballed. Thanks.

2425

Oops. That must have evolved out of hacking on the code emitted in RISCVGenAsmMatcher.inc

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1474

isAsmParserOnly = 1 would let it go into the tables in RISCVGenAsmMatcher.inc, but we don't want that here.

[jrtc27]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2273

Didn't notice this quirk the first time though but eww why was this deemed a good idea all those years ago...

2323

No, that works because the cases where you have bare symbols that require context to know whether to parse a symbol or a register all use custom parsers, which are what MatchOperandParserImpl calls. Only after it's decided it's not a special case does it then return no match and fall back to the generic code like this.

... except it's currently broken for branches. For j sym we make sure to use SImm21Lsb0JAL, but for beq reg, reg, sym we don't use something with a custom parser, just a generic immediate operand. So I guess this does have feature parity after all. Now on my mental list of things to fix...

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1450

some of the "CodeGen pseudos" are also used by MC, like PseudoLLA.

I'll move these up.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1474

Ah, I've finally gone and looked at what these actually do in the TableGen backends. isCodeGenOnly is more isNotAsmParserNorDisasm and isAsmParserOnly is more isNotDisasm; there isn't really anything to do to opt in/out of CodeGen stuff because that just stems from whether you use it in patterns or custom selection. So yes this is the right option despite what its name says.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2323

Yeah I saw we used the custom parser for j sym so I matched it.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1450

Yeah, that's a good point, we do have a few that have crept into the wrong place. Some of them might have started as CodeGen-only pseudos that later became visible to the AsmParser, but I'm pretty sure they weren't all like that.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1507

This should have been .insn s

llvm/test/MC/RISCV/insn.s

45

This should be .insn s

[craig.topper]

Address review comments

Still need to decide on whether to use a tab.

[craig.topper]

Fix comment I forgot update

[asb]

I made a start on .insn support quite some time ago (and unfortunately got distracted with other things and didn't get it to the point it was worth sharing - apologies for that).

I actually had an idea for doing it in a slightly different way vs SystemZ (that SystemZ could hopefully be moved towards as well). Essentially, if we parse .insn like an instruction and not like a directive, we can reuse most of the existing tablegen machinery for asm parsing.

e.g. adding a new hook to AsmParser:

--- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
+++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
@@ -416,6 +416,13 @@ public:
   /// \param DirectiveID - the identifier token of the directive.
   virtual bool ParseDirective(AsmToken DirectiveID) = 0;
 
+  /// Return true if the given IDVal should be parsed as a directive. Called
+  /// whenever a "normal" directive is encountered (i.e. not conditional
+  /// assembly directives). Targets may use this to override default parsing
+  /// behaviour, for instance to allow instruction-like directives such as
+  /// .insn to be parsed as an instruction.
+  virtual bool shouldParseAsDirective(StringRef IDVal) { return true; }
+
   /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
   /// instruction as an actual MCInst and emit it to the specified MCStreamer.
   /// This returns false on success and returns true on failure to match.
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp
index c05f26cbdda5..c3fd85f4a9e0 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -1889,7 +1889,8 @@ bool AsmParser::parseStatement(ParseStatementInfo &Info,
   // Otherwise, we have a normal instruction or directive.
 
   // Directives start with "."
-  if (IDVal.startswith(".") && IDVal != ".") {
+  if (IDVal.startswith(".") && IDVal != "." &&
+      getTargetParser().shouldParseAsDirective(IDVal)) {
     // There are several entities interested in parsing directives:
     //
     // 1. The target-specific assembly parser. Some directives are target

Then implement that hook in RISCVAsmParser:

@@ -1756,6 +1808,17 @@ bool RISCVAsmParser::ParseInstruction(ParseInstructionInfo &Info,
   // First operand is token for instruction
   Operands.push_back(RISCVOperand::createToken(Name, NameLoc, isRV64()));
 
+  // If parsing a .insn directive, then create a token containing the
+  // instruction format identifier.
+  if (Name == ".insn") {
+    SMLoc Loc = getLoc();
+    if (!getLexer().is(AsmToken::Identifier))
+      return Error(Loc, ".insn should be followed by an instruction format");
+    StringRef InstFormat = getParser().getTok().getIdentifier();
+    getParser().Lex();
+    Operands.push_back(RISCVOperand::createToken(InstFormat, Loc, isRV64()));
+  }
+
   // If there are no more operands, then finish
   if (getLexer().is(AsmToken::EndOfStatement))
     return false;
@@ -1847,6 +1910,10 @@ bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) {
   return true;
 }
 
+bool RISCVAsmParser::shouldParseAsDirective(StringRef IDVal) {
+  return IDVal != ".insn";
+}
+

Then with some extra machinery for printing opcode values etc, you can make definitions in RISCVInstrInfo.td like:

+//===----------------------------------------------------------------------===//
+// .insn directive
+//===----------------------------------------------------------------------===//
+
+class OpcodeVal<string name, bits<7> enc> {
+  string Name = name;
+  bits<7> Encoding = enc;
+}
+
+def OpcodeValList : GenericTable {
+  let FilterClass = "OpcodeVal";
+  let Fields = [ "Name", "Encoding" ];
+
+  let PrimaryKey = [ "Encoding" ];
+  let PrimaryKeyName = "lookupOpcodeValByEncoding";
+}
+
+def lookupOpcodeValByName : SearchIndex {
+  let Table = OpcodeValList;
+  let Key = [ "Name" ];
+}
+
+// These names match those accepted by the GNU assembler's .insn directive.
+def : OpcodeVal<"C0", 0x0>;
+def : OpcodeVal<"C1", 0x1>;
+def : OpcodeVal<"C2", 0x2>;
+def : OpcodeVal<"LOAD", 0x03>;
+def : OpcodeVal<"LOAD_FP", 0x07>;
+def : OpcodeVal<"CUSTOM_0", 0x0b>;
+def : OpcodeVal<"MISC_MEM", 0x0f>;
+def : OpcodeVal<"OP_IMM", 0x13>;
+def : OpcodeVal<"AUIPC", 0x17>;
+def : OpcodeVal<"OP_IMM_32", 0x1b>;
+def : OpcodeVal<"STORE", 0x23>;
+def : OpcodeVal<"STORE_FP", 0x27>;
+def : OpcodeVal<"CUSTOM_1", 0x2b>;
+def : OpcodeVal<"AMO", 0x2f>;
+def : OpcodeVal<"OP", 0x33>;
+def : OpcodeVal<"LUI", 0x37>;
+def : OpcodeVal<"OP_32", 0x3b>;
+def : OpcodeVal<"MADD", 0x43>;
+def : OpcodeVal<"MSUB", 0x47>;
+def : OpcodeVal<"NMADD", 0x4f>;
+def : OpcodeVal<"NMSUB", 0x4b>;
+def : OpcodeVal<"OP_FP", 0x53>;
+def : OpcodeVal<"CUSTOM_2", 0x5b>;
+def : OpcodeVal<"BRANCH", 0x63>;
+def : OpcodeVal<"JALR", 0x67>;
+def : OpcodeVal<"JAL", 0x6f>;
+def : OpcodeVal<"SYSTEM", 0x73>;
+def : OpcodeVal<"CUSTOM_3", 0x7b>;
+
+// Note that for all directive definitions, the passed constants (e.g. funct3,
+// funct3, opcode) are all dummy values that are overridden by the .insn
+// definition.
+
+let hasSideEffects = 1, mayLoad = 1, mayStore = 1,
+    isAsmParserOnly = 1 in {
+
+def INSN_R : RVInstR<0, 0, OPC_LOAD, (outs GPR:$rd), (ins opcode_value:$opcode,
+                     uimm3:$funct3, uimm7:$funct7, GPR:$rs1, GPR:$rs2),
+                     ".insn r", "$opcode, $funct3, $funct7, $rd, $rs1, $rs2">,
+             Sched<[]> {
+  bits<7> funct7;
+  bits<3> funct3;
+  bits<7> opcode;
+
+  let Inst{31-25} = funct7;
+  let Inst{14-12} = funct3;
+  let Inst{6-0} = opcode;
+}
+
+def INSN_I : RVInstI<0, OPC_LOAD, (outs GPR:$rd), (ins opcode_value:$opcode,
+                     uimm3:$funct3, GPR:$rs1, simm12:$imm12), ".insn i",
+                     "$opcode, $funct3, $rd, $rs1, $imm12">,
+      Sched<[]> {
+  bits<3> funct3;
+  bits<7> opcode;
+
+  let Inst{14-12} = funct3;
+  let Inst{6-0} = opcode;
+}

I'm afraid the branch were I was playing with this got a bit messy so it's hard to extract a full patch, but hopefully that's enough to outline the idea (and I can spend more time pulling bits out if it's useful).

[asb]

CC @uweigand in case you have any thoughts in the more tablegen-based approach I suggested in the comment above (i.e. whether you'd be interested in using it for SystemZ if it worked out for RISC-V).

[craig.topper]

In D108602#2979398, @asb wrote:

I made a start on .insn support quite some time ago (and unfortunately got distracted with other things and didn't get it to the point it was worth sharing - apologies for that).

I actually had an idea for doing it in a slightly different way vs SystemZ (that SystemZ could hopefully be moved towards as well). Essentially, if we parse .insn like an instruction and not like a directive, we can reuse most of the existing tablegen machinery for asm parsing.

e.g. adding a new hook to AsmParser:

--- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
+++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
@@ -416,6 +416,13 @@ public:
   /// \param DirectiveID - the identifier token of the directive.
   virtual bool ParseDirective(AsmToken DirectiveID) = 0;
 
+  /// Return true if the given IDVal should be parsed as a directive. Called
+  /// whenever a "normal" directive is encountered (i.e. not conditional
+  /// assembly directives). Targets may use this to override default parsing
+  /// behaviour, for instance to allow instruction-like directives such as
+  /// .insn to be parsed as an instruction.
+  virtual bool shouldParseAsDirective(StringRef IDVal) { return true; }
+
   /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
   /// instruction as an actual MCInst and emit it to the specified MCStreamer.
   /// This returns false on success and returns true on failure to match.
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp
index c05f26cbdda5..c3fd85f4a9e0 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -1889,7 +1889,8 @@ bool AsmParser::parseStatement(ParseStatementInfo &Info,
   // Otherwise, we have a normal instruction or directive.
 
   // Directives start with "."
-  if (IDVal.startswith(".") && IDVal != ".") {
+  if (IDVal.startswith(".") && IDVal != "." &&
+      getTargetParser().shouldParseAsDirective(IDVal)) {
     // There are several entities interested in parsing directives:
     //
     // 1. The target-specific assembly parser. Some directives are target

Then implement that hook in RISCVAsmParser:

@@ -1756,6 +1808,17 @@ bool RISCVAsmParser::ParseInstruction(ParseInstructionInfo &Info,
   // First operand is token for instruction
   Operands.push_back(RISCVOperand::createToken(Name, NameLoc, isRV64()));
 
+  // If parsing a .insn directive, then create a token containing the
+  // instruction format identifier.
+  if (Name == ".insn") {
+    SMLoc Loc = getLoc();
+    if (!getLexer().is(AsmToken::Identifier))
+      return Error(Loc, ".insn should be followed by an instruction format");
+    StringRef InstFormat = getParser().getTok().getIdentifier();
+    getParser().Lex();
+    Operands.push_back(RISCVOperand::createToken(InstFormat, Loc, isRV64()));
+  }
+
   // If there are no more operands, then finish
   if (getLexer().is(AsmToken::EndOfStatement))
     return false;
@@ -1847,6 +1910,10 @@ bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) {
   return true;
 }
 
+bool RISCVAsmParser::shouldParseAsDirective(StringRef IDVal) {
+  return IDVal != ".insn";
+}
+

Then with some extra machinery for printing opcode values etc, you can make definitions in RISCVInstrInfo.td like:

+//===----------------------------------------------------------------------===//
+// .insn directive
+//===----------------------------------------------------------------------===//
+
+class OpcodeVal<string name, bits<7> enc> {
+  string Name = name;
+  bits<7> Encoding = enc;
+}
+
+def OpcodeValList : GenericTable {
+  let FilterClass = "OpcodeVal";
+  let Fields = [ "Name", "Encoding" ];
+
+  let PrimaryKey = [ "Encoding" ];
+  let PrimaryKeyName = "lookupOpcodeValByEncoding";
+}
+
+def lookupOpcodeValByName : SearchIndex {
+  let Table = OpcodeValList;
+  let Key = [ "Name" ];
+}
+
+// These names match those accepted by the GNU assembler's .insn directive.
+def : OpcodeVal<"C0", 0x0>;
+def : OpcodeVal<"C1", 0x1>;
+def : OpcodeVal<"C2", 0x2>;
+def : OpcodeVal<"LOAD", 0x03>;
+def : OpcodeVal<"LOAD_FP", 0x07>;
+def : OpcodeVal<"CUSTOM_0", 0x0b>;
+def : OpcodeVal<"MISC_MEM", 0x0f>;
+def : OpcodeVal<"OP_IMM", 0x13>;
+def : OpcodeVal<"AUIPC", 0x17>;
+def : OpcodeVal<"OP_IMM_32", 0x1b>;
+def : OpcodeVal<"STORE", 0x23>;
+def : OpcodeVal<"STORE_FP", 0x27>;
+def : OpcodeVal<"CUSTOM_1", 0x2b>;
+def : OpcodeVal<"AMO", 0x2f>;
+def : OpcodeVal<"OP", 0x33>;
+def : OpcodeVal<"LUI", 0x37>;
+def : OpcodeVal<"OP_32", 0x3b>;
+def : OpcodeVal<"MADD", 0x43>;
+def : OpcodeVal<"MSUB", 0x47>;
+def : OpcodeVal<"NMADD", 0x4f>;
+def : OpcodeVal<"NMSUB", 0x4b>;
+def : OpcodeVal<"OP_FP", 0x53>;
+def : OpcodeVal<"CUSTOM_2", 0x5b>;
+def : OpcodeVal<"BRANCH", 0x63>;
+def : OpcodeVal<"JALR", 0x67>;
+def : OpcodeVal<"JAL", 0x6f>;
+def : OpcodeVal<"SYSTEM", 0x73>;
+def : OpcodeVal<"CUSTOM_3", 0x7b>;
+
+// Note that for all directive definitions, the passed constants (e.g. funct3,
+// funct3, opcode) are all dummy values that are overridden by the .insn
+// definition.
+
+let hasSideEffects = 1, mayLoad = 1, mayStore = 1,
+    isAsmParserOnly = 1 in {
+
+def INSN_R : RVInstR<0, 0, OPC_LOAD, (outs GPR:$rd), (ins opcode_value:$opcode,
+                     uimm3:$funct3, uimm7:$funct7, GPR:$rs1, GPR:$rs2),
+                     ".insn r", "$opcode, $funct3, $funct7, $rd, $rs1, $rs2">,
+             Sched<[]> {
+  bits<7> funct7;
+  bits<3> funct3;
+  bits<7> opcode;
+
+  let Inst{31-25} = funct7;
+  let Inst{14-12} = funct3;
+  let Inst{6-0} = opcode;
+}
+
+def INSN_I : RVInstI<0, OPC_LOAD, (outs GPR:$rd), (ins opcode_value:$opcode,
+                     uimm3:$funct3, GPR:$rs1, simm12:$imm12), ".insn i",
+                     "$opcode, $funct3, $rd, $rs1, $imm12">,
+      Sched<[]> {
+  bits<3> funct3;
+  bits<7> opcode;
+
+  let Inst{14-12} = funct3;
+  let Inst{6-0} = opcode;
+}

I'm afraid the branch were I was playing with this got a bit messy so it's hard to extract a full patch, but hopefully that's enough to outline the idea (and I can spend more time pulling bits out if it's useful).

I started looking at this and found one issue immediately.

We ended up with this entry in the custom operand parser

{ 0 /* .insn */, 8 /* 3 */, MCK_SImm21Lsb0JAL, AMFBS_None },

This should be based on the format. Not just ".insn". I think this would cause the operand to fail parsing for any of the formats, but J.

[craig.topper]

Make some strides in reusing the instruction parsing and matching infrastructure.

[craig.topper]

clang-format

[craig.topper]

Ping

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

961

We don't typically indent inside let blocks

998

Will writing .insn_r in the source get picked up by this and thus expose this detail, or be regarded as an unknown directive and thus give an error?

1004

R4 ones need an extra space

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

564

XLenVT is wrong, should probably be untyped or Any or something like that. 32 is bogus too but I see we do that for GPR, presumably it's ignored when you use RegInfoByHwMode.

[craig.topper]

Address review comments.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

998

It should be hidden. I've added a test to insn_invalid.s

[jrtc27]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

568

Missed this one last time... but same comment, probably shouldn't be set

[craig.topper]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

568

Removing that caused tablegen to crash. Turns out we either need a valid VT where untyped is or we need a non-zero "let Size =".

[craig.topper]

Remove the RegInfos but set the size to 32 as a bogus value to keep tablegen from crashing.

[jrtc27]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

568

Makes sense. This is probably about as good as we can get then without adding some notion of a pseudo register class to tablegen.

[jrtc27]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2261

llvm/lib/Target/RISCV/RISCVInstrInfo.td

962

We should probably be marking rd as outs? In a way it doesn't matter (though downstream I think I'll need to inspect the register used for rd to know which relocation to use for jumps; currently I just look at the opcode in RISCVMCCodeEmitter::getImmOpValue but that'll become the ambiguous InsnJ and, eventually, InsnCJ and being able to just get the first def to see what register it is would be slightly easier than having to hard-code which operand number it is) but is technically wrong currently.

[craig.topper]

Move $rd to outs. Fix formatting

[jrtc27]

Thanks, looks fine to me now but let's see what others think

[MaskRay]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1007

Does binutils have these .insn_* aliases? I cannot find them.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1007

No. This was a hack to allow tablegen to have a mnemonic to key the lookup need for tryCustomParseOperand. Anything starting with a . is treated as a directive so will never be parsed as an instruction. There's code in the .insn handling to make this fake mnemonic.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1007

No, but see previous discussions. These are internal aliases (which, given they start with a dot, get parsed as directives and thus don't end up checking the match tables, so cannot be used in assembly; see inso-invalid.s for a test of this) to work around TableGen's asm matcher assumption that the mnemonic plus the first argument is enough to disambiguate which instruction to try matching against (there's no way to backtrack, nor to try multiple in parallel).

[MaskRay]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2254

seems that you can omit L since the opcode is always correct.

Then the argument can be deleted.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2254

L is also passed to MatchAndEmitInstruction and is used for "too few operands for instruction". I guess I could point that at the format operand instead?

[zixuan-wu]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

156

Does it forget to add UIMM2 and UIMM3 verification at verifyInstruction in RISCVInstrInfo.cpp?

[zixuan-wu]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

156

And can also make uimm2/uimm3 be instance of ImmLeaf? Which make them reusable to be used in DAG pattern.

[zixuan-wu]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

156

It's also missed in match invalid switch like Match_InvalidUImm5 does in RISCVAsmparser.cpp?

[Jim]

I have uploaded D110307 and D110308 to add missing cases for uimm2, uimm3 and uimm7.

[zixuan-wu]

In D108602#3017150, @Jim wrote:

I have uploaded D110307 and D110308 to add missing cases for uimm2, uimm3 and uimm7.

Thank you!

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

#include "RISCVGenAsmMatcher.inc"
   OperandMatchResultTy parseJALOffset(OperandVector &Operands);
   OperandMatchResultTy parseVTypeI(OperandVector &Operands);
   OperandMatchResultTy parseMaskReg(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
   bool parseDirectiveOption();
   bool parseDirectiveAttribute();
+  bool parseDirectiveInsn(SMLoc L);
 
   void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
     if (!(getSTI().getFeatureBits()[Feature])) {
       MCSubtargetInfo &STI = copySTI();
       setAvailableFeatures(
           ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
     }
   }
bool isUImmLog2XLenHalf() const {
     if (!isImm())
       return false;
     if (!evaluateConstantImm(getImm(), Imm, VK) ||
         VK != RISCVMCExpr::VK_RISCV_None)
       return false;
     return (isRV64() && isUInt<5>(Imm)) || isUInt<4>(Imm);
   }
 
+  bool isUImm2() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<2>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isUImm3() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm5() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isUImm7() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<7>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isSImm5() const {
     if (!isImm())
       return false;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     int64_t Imm;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) {
   // This returns false if this function recognizes the directive
   // regardless of whether it is successfully handles or reports an
   // error. Otherwise it returns true to give the generic parser a
   // chance at recognizing it.
   StringRef IDVal = DirectiveID.getString();
 
   if (IDVal == ".option")
     return parseDirectiveOption();
-  else if (IDVal == ".attribute")
+  if (IDVal == ".attribute")
     return parseDirectiveAttribute();
+  if (IDVal == ".insn")
+    return parseDirectiveInsn(DirectiveID.getLoc());
 
   return true;
 }
 
 bool RISCVAsmParser::parseDirectiveOption() {
   MCAsmParser &Parser = getParser();
   // Get the option token.
   AsmToken Tok = Parser.getTok();
if (Tag != RISCVAttrs::ARCH) {
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
   }
 
   return false;
 }
 
+/// parseDirectiveInsn
+/// ::= .insn [ format encoding, (operands (, operands)*) ]
+bool RISCVAsmParser::parseDirectiveInsn(SMLoc L) {
+  MCAsmParser &Parser = getParser();
+
+  // Expect instruction format as identifier.
+  StringRef Format;
+  SMLoc ErrorLoc = Parser.getTok().getLoc();
+  if (Parser.parseIdentifier(Format))
+    return Error(ErrorLoc, "expected instruction format");
+
+  if (Format != "r" && Format != "r4" && Format != "i" && Format != "b" &&
+      Format != "sb" && Format != "u" && Format != "j" && Format != "uj" &&
+      Format != "s")
+    return Error(ErrorLoc, "invalid instruction format");
+
+  std::string FormatName = (".insn_" + Format).str();
+
+  ParseInstructionInfo Info;
+  SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
+
+  if (ParseInstruction(Info, FormatName, L, Operands))
+    return true;
+
+  unsigned Opcode;
+  uint64_t ErrorInfo;
+  return MatchAndEmitInstruction(L, Opcode, Operands, Parser.getStreamer(),
+                                 ErrorInfo,
+                                 /*MatchingInlineAsm=*/false);
+}
+
 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
   MCInst CInst;
   bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
   if (Res)
     ++RISCVNumInstrsCompressed;
   S.emitInstruction((Res ? CInst : Inst), getSTI());
 }
 
 void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
                                  MCStreamer &Out) {
   RISCVMatInt::InstSeq Seq =
       RISCVMatInt::generateInstSeq(Value, getSTI().getFeatureBits());
 
   MCRegister SrcReg = RISCV::X0;
   for (RISCVMatInt::Inst &Inst : Seq) {
     if (Inst.Opc == RISCV::LUI) {
       emitToStreamer(
           Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm));
void RISCVAsmParser::emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
   const MCExpr *RefToLinkTmpLabel =
       RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx),
                           RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx);
 
   emitToStreamer(Out, MCInstBuilder(SecondOpcode)
                           .addOperand(DestReg)
                           .addOperand(TmpReg)
                           .addExpr(RefToLinkTmpLabel));
 }
 
 void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
                                           MCStreamer &Out) {
   // The load local address pseudo-instruction "lla" is used in PC-relative
   // addressing of local symbols:
   //   lla rdest, symbol
   // expands to
   //   TmpLabel: AUIPC rdest, %pcrel_hi(symbol)
   //             ADDI rdest, rdest, %pcrel_lo(TmpLabel)
   MCOperand DestReg = Inst.getOperand(0);
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
   emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_RISCV_PCREL_HI,
                     RISCV::ADDI, IDLoc, Out);
 }
 
 void RISCVAsmParser::emitLoadAddress(MCInst &Inst, SMLoc IDLoc,
                                      MCStreamer &Out) {
   // The load address pseudo-instruction "la" is used in PC-relative and
   // GOT-indirect addressing of global symbols:
   //   la rdest, symbol
   // expands to either (for non-PIC)
   //   TmpLabel: AUIPC rdest, %pcrel_hi(symbol)
   //             ADDI rdest, rdest, %pcrel_lo(TmpLabel)
   // or (for PIC)
   //   TmpLabel: AUIPC rdest, %got_pcrel_hi(symbol)
   //             Lx rdest, %pcrel_lo(TmpLabel)(rdest)
   MCOperand DestReg = Inst.getOperand(0);
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
   unsigned SecondOpcode;
   RISCVMCExpr::VariantKind VKHi;
   if (ParserOptions.IsPicEnabled) {
     SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
     VKHi = RISCVMCExpr::VK_RISCV_GOT_HI;
   } else {
     SecondOpcode = RISCV::ADDI;
     VKHi = RISCVMCExpr::VK_RISCV_PCREL_HI;
   }
   emitAuipcInstPair(DestReg, DestReg, Symbol, VKHi, SecondOpcode, IDLoc, Out);
void RISCVAsmParser::emitPseudoExtend(MCInst &Inst, bool SignExtend,
   //
   // The expansion looks like this
   //
   //    SLLI rd, rs, XLEN - Width
   //    SR[A|R]I rd, rd, XLEN - Width
   MCOperand DestReg = Inst.getOperand(0);
   MCOperand SourceReg = Inst.getOperand(1);
 
   unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI;
   int64_t ShAmt = (isRV64() ? 64 : 32) - Width;
 
   assert(ShAmt > 0 && "Shift amount must be non-zero.");
 
   emitToStreamer(Out, MCInstBuilder(RISCV::SLLI)
                           .addOperand(DestReg)
                           .addOperand(SourceReg)
                           .addImm(ShAmt));

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

enum {
   // multiple "bitmask" flags.
   MO_DIRECT_FLAG_MASK = 15
 };
 } // namespace RISCVII
 
 namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
-  OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM3,
+  OPERAND_UIMM4,
   OPERAND_UIMM5,
+  OPERAND_UIMM7,
   OPERAND_UIMM12,
   OPERAND_SIMM12,
   OPERAND_UIMM20,
   OPERAND_UIMMLOG2XLEN,
   OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN,
   // Operand is either a register or uimm5, this is used by V extension pseudo
   // instructions to represent a value that be passed as AVL to either vsetvli
   // or vsetivli.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

case RISCVMCExpr::VK_RISCV_CALL:
       break;
     case RISCVMCExpr::VK_RISCV_CALL_PLT:
       FixupKind = RISCV::fixup_riscv_call_plt;
       RelaxCandidate = true;
       break;
     }
   } else if (Kind == MCExpr::SymbolRef &&
              cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
-    if (Desc.getOpcode() == RISCV::JAL) {
+    if (MIFrm == RISCVII::InstFormatJ) {
       FixupKind = RISCV::fixup_riscv_jal;
     } else if (MIFrm == RISCVII::InstFormatB) {
       FixupKind = RISCV::fixup_riscv_branch;
     } else if (MIFrm == RISCVII::InstFormatCJ) {
       FixupKind = RISCV::fixup_riscv_rvc_jump;
     } else if (MIFrm == RISCVII::InstFormatCB) {
       FixupKind = RISCV::fixup_riscv_rvc_branch;
     }

llvm/lib/Target/RISCV/RISCVInstrFormats.td

class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
 
   let Inst{31} = imm20{19};
   let Inst{30-21} = imm20{9-0};
   let Inst{20} = imm20{10};
   let Inst{19-12} = imm20{18-11};
   let Inst{11-7} = rd;
   let Opcode = opcode.Value;
 }
+
+//===----------------------------------------------------------------------===//
+// Instruction classes for .insn directives
+//===----------------------------------------------------------------------===//
+
+class DirectiveInsnR<dag outs, dag ins, string argstr>
+  : RVInst<outs, ins, "", "", [], InstFormatR> {
+  bits<7> opcode;
+  bits<7> funct7;
+  bits<3> funct3;
+
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode;
+
+  let AsmString = ".insn r " # argstr;
+}
+
+class DirectiveInsnR4<dag outs, dag ins, string argstr>
+  : RVInst<outs, ins, "", "", [], InstFormatR4> {
+  bits<7> opcode;
+  bits<2> funct2;
+  bits<3> funct3;
+
+  bits<5> rs3;
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode;
+
+  let AsmString = ".insn r4 " # argstr;
+}
+
+class DirectiveInsnI<dag outs, dag ins, string argstr>
+  : RVInst<outs, ins, "", "", [], InstFormatI> {
+  bits<7> opcode;
+  bits<3> funct3;
+
+  bits<12> imm12;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-20} = imm12;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode;
+
+  let AsmString = ".insn i " # argstr;
+}
+
+class DirectiveInsnS<dag outs, dag ins, string argstr>
+  : RVInst<outs, ins, "", "", [], InstFormatS> {
+  bits<7> opcode;
+  bits<3> funct3;
+
+  bits<12> imm12;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31-25} = imm12{11-5};
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = imm12{4-0};
+  let Opcode = opcode;
+
+  let AsmString = ".insn s " # argstr;
+}
+
+class DirectiveInsnB<dag outs, dag ins, string argstr>
+  : RVInst<outs, ins, "", "", [], InstFormatB> {
+  bits<7> opcode;
+  bits<3> funct3;
+
+  bits<12> imm12;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{31} = imm12{11};
+  let Inst{30-25} = imm12{9-4};
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-8} = imm12{3-0};
+  let Inst{7} = imm12{10};
+  let Opcode = opcode;
+
+  let AsmString = ".insn b " # argstr;
+}
+
+class DirectiveInsnU<dag outs, dag ins, string argstr>
+  : RVInst<outs, ins, "", "", [], InstFormatU> {
+  bits<7> opcode;
+
+  bits<20> imm20;
+  bits<5> rd;
+
+  let Inst{31-12} = imm20;
+  let Inst{11-7} = rd;
+  let Opcode = opcode;
+
+  let AsmString = ".insn u " # argstr;
+}
+
+class DirectiveInsnJ<dag outs, dag ins, string argstr>
+  : RVInst<outs, ins, "", "", [], InstFormatJ> {
+  bits<7> opcode;
+
+  bits<20> imm20;
+  bits<5> rd;
+
+  let Inst{31-12} = imm20;
+  let Inst{11-7} = rd;
+  let Opcode = opcode;
+
+  let AsmString = ".insn j " # argstr;
+}

llvm/lib/Target/RISCV/RISCVInstrInfo.td

let MCOperandPredicate = [{
     if (STI.getTargetTriple().isArch64Bit())
       return isUInt<6>(Imm);
     return isUInt<5>(Imm);
   }];
   let OperandType = "OPERAND_UIMMLOG2XLEN";
   let OperandNamespace = "RISCVOp";
 }
 
+def uimm2 : Operand<XLenVT> {
+  let ParserMatchClass = UImmAsmOperand<2>;
+  let DecoderMethod = "decodeUImmOperand<2>";
+  let OperandType = "OPERAND_UIMM2";
+  let OperandNamespace = "RISCVOp";
+}
+
+def uimm3 : Operand<XLenVT> {
+  let ParserMatchClass = UImmAsmOperand<3>;
+  let DecoderMethod = "decodeUImmOperand<3>";
+  let OperandType = "OPERAND_UIMM3";
+  let OperandNamespace = "RISCVOp";
+}
+
 def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<5>;
   let DecoderMethod = "decodeUImmOperand<5>";
   let OperandType = "OPERAND_UIMM5";
   let OperandNamespace = "RISCVOp";
 }
 
+def uimm7 : Operand<XLenVT> {
+  let ParserMatchClass = UImmAsmOperand<7>;
+  let DecoderMethod = "decodeUImmOperand<7>";
+  let OperandType = "OPERAND_UIMM7";
+  let OperandNamespace = "RISCVOp";
+}
+
 def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<12>;
   let EncoderMethod = "getImmOpValue";
   let DecoderMethod = "decodeSImmOperand<12>";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isInt<12>(Imm);

 def : MnemonicAlias<"sbreak", "ebreak">;
 
 // This alias was added to the spec in December 2020. Don't print it by default
 // to allow assembly we print to be compatible with versions of GNU assembler
 // that don't support this alias.
 def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>;
 
 //===----------------------------------------------------------------------===//
+// .insn directive instructions
+//===----------------------------------------------------------------------===//
+
+// isCodeGenOnly = 1 to hide them from the tablegened assembly parser.
+let isCodeGenOnly = 1, hasSideEffects = 1, mayLoad = 1, mayStore = 1,
+    hasNoSchedulingInfo = 1 in {
+def InsnR : DirectiveInsnR<(outs AnyReg:$rd), (ins uimm7:$opcode, uimm3:$funct3,
+                                                   uimm7:$funct7, AnyReg:$rs1,
+                                                   AnyReg:$rs2),
+                           "$opcode, $funct3, $funct7, $rd, $rs1, $rs2">;
+def InsnR4 : DirectiveInsnR4<(outs AnyReg:$rd), (ins uimm7:$opcode,
+                                                     uimm3:$funct3,
+                                                     uimm2:$funct2,
+                                                     AnyReg:$rs1, AnyReg:$rs2,
+                                                     AnyReg:$rs3),
+                            "$opcode, $funct3, $funct2, $rd, $rs1, $rs2, $rs3">;
+def InsnI : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7:$opcode, uimm3:$funct3,
+                                                   AnyReg:$rs1, simm12:$imm12),
+                           "$opcode, $funct3, $rd, $rs1, $imm12">;
+def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7:$opcode,
+                                                       uimm3:$funct3,
+                                                       AnyReg:$rs1,
+                                                       simm12:$imm12),
+                               "$opcode, $funct3, $rd, ${imm12}(${rs1})">;
+def InsnB : DirectiveInsnB<(outs), (ins uimm7:$opcode, uimm3:$funct3,
+                                        AnyReg:$rs1, AnyReg:$rs2,
+                                        simm13_lsb0:$imm12),
+                           "$opcode, $funct3, $rs1, $rs2, $imm12">;
+def InsnU : DirectiveInsnU<(outs AnyReg:$rd), (ins uimm7:$opcode,
+                                                   uimm20_lui:$imm20),
+                           "$opcode, $rd, $imm20">;
+def InsnJ : DirectiveInsnJ<(outs AnyReg:$rd), (ins uimm7:$opcode,
+                                                   simm21_lsb0_jal:$imm20),
+                           "$opcode, $rd, $imm20">;
+def InsnS : DirectiveInsnS<(outs), (ins uimm7:$opcode, uimm3:$funct3,
+                                        AnyReg:$rs2, AnyReg:$rs1,
+                                        simm12:$imm12),
+                           "$opcode, $funct3, $rs2, ${imm12}(${rs1})">;
+}
+
+// Use InstAliases to match these so that we can combine the insn and format
+// into a mnemonic to use as the key for the tablegened asm matcher table. The
+// parser will take care of creating these fake mnemonics and will only do it
+// for known formats.
+let EmitPriority = 0 in {
+def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2",
+                (InsnR AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7,
+                       AnyReg:$rs1, AnyReg:$rs2)>;
+// Accept 4 register form of ".insn r" as alias for ".insn r4".
+def : InstAlias<".insn_r $opcode, $funct3, $funct7, $rd, $rs1, $rs2, $rs3",
+                (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7,
+                        AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>;
+def : InstAlias<".insn_r4 $opcode, $funct3, $funct7, $rd, $rs1, $rs2, $rs3",
+                (InsnR4 AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, uimm7:$funct7,
+                        AnyReg:$rs1, AnyReg:$rs2, AnyReg:$rs3)>;
+def : InstAlias<".insn_i $opcode, $funct3, $rd, $rs1, $imm12",
+                (InsnI AnyReg:$rd, uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1,
+                       simm12:$imm12)>;
+def : InstAlias<".insn_i $opcode, $funct3, $rd, ${imm12}(${rs1})",
+                (InsnI_Mem AnyReg:$rd, uimm7:$opcode, uimm3:$funct3,
+                           AnyReg:$rs1, simm12:$imm12)>;
+def : InstAlias<".insn_b $opcode, $funct3, $rs1, $rs2, $imm12",
+                (InsnB uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1,
+                       AnyReg:$rs2, simm13_lsb0:$imm12)>;
+// Accept sb as an alias for b.
+def : InstAlias<".insn_sb $opcode, $funct3, $rs1, $rs2, $imm12",
+                (InsnB uimm7:$opcode, uimm3:$funct3, AnyReg:$rs1,
+                       AnyReg:$rs2, simm13_lsb0:$imm12)>;
+def : InstAlias<".insn_u $opcode, $rd, $imm20",
+                (InsnU AnyReg:$rd, uimm7:$opcode, uimm20_lui:$imm20)>;
+def : InstAlias<".insn_j $opcode, $rd, $imm20",
+                (InsnJ AnyReg:$rd, uimm7:$opcode, simm21_lsb0_jal:$imm20)>;
+// Accept uj as an alias for j.
+def : InstAlias<".insn_uj $opcode, $rd, $imm20",
+                (InsnJ AnyReg:$rd, uimm7:$opcode, simm21_lsb0_jal:$imm20)>;
+def : InstAlias<".insn_s $opcode, $funct3, $rs2, ${imm12}(${rs1})",
+                (InsnS uimm7:$opcode, uimm3:$funct3, AnyReg:$rs2,
+                       AnyReg:$rs1, simm12:$imm12)>;
+}
+
+//===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //
 // Naming convention: For 'generic' pattern classes, we use the naming
 // convention PatTy1Ty2. For pattern classes which offer a more complex
 // expansion, prefix the class name, e.g. BccPat.
 //===----------------------------------------------------------------------===//
 
 /// Generic pattern classes
 
 class PatGpr<SDPatternOperator OpNode, RVInst Inst>
     : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
 class PatGprGpr<SDPatternOperator OpNode, RVInst Inst>
     : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
 
 class PatGprImm<SDPatternOperator OpNode, RVInst Inst, ImmLeaf ImmType>
     : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), ImmType:$imm)),

 
 def add_oneuse : PatFrag<(ops node:$A, node:$B), (add node:$A, node:$B), [{
   return N->hasOneUse();
 }]>;
 
 def mul_oneuse : PatFrag<(ops node:$A, node:$B), (mul node:$A, node:$B), [{
   return N->hasOneUse();
 }]>;
 
 def mul_const_oneuse : PatFrag<(ops node:$A, node:$B),
                                (mul node:$A, node:$B), [{
   if (auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
     if (N1C->hasOneUse())
       return true;
   return false;
 }]>;
 
 /// Simple arithmetic operations
 
 def : PatGprGpr<add, ADD>;
 def : PatGprSimm12<add, ADDI>;
 def : PatGprGpr<sub, SUB>;
 def : PatGprGpr<or, OR>;
 def : PatGprSimm12<or, ORI>;
 def : PatGprGpr<and, AND>;
 def : PatGprSimm12<and, ANDI>;

 let Predicates = [IsRV64] in {
 // Select W instructions if only the lower 32-bits of the result are used.
 def : Pat<(overflowingbinopw<add> GPR:$rs1, (AddiPair:$rs2)),
           (ADDIW (ADDIW GPR:$rs1, (AddiPairImmB AddiPair:$rs2)),
                  (AddiPairImmA AddiPair:$rs2))>;
 }
 
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoB.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
                                     !mul(nf, m)>;
   }
 }
 
 // Special registers
 def FFLAGS : RISCVReg<0, "fflags">;
 def FRM    : RISCVReg<0, "frm">;
 def FCSR   : RISCVReg<0, "fcsr">;
+
+// Any type register. Used for .insn directives when we don't know what the
+// register types could be.
+// NOTE: The alignment and size are bogus values. The Size needs to be non-zero
+// or tablegen will use "untyped" to determine the size which will assert.
+let isAllocatable = 0 in
+def AnyReg : RegisterClass<"RISCV", [untyped], 32,
+                           (add (sequence "X%u", 0, 31),
+                                (sequence "F%u_D", 0, 31),
+                                (sequence "V%u", 0, 31))> {
+  let Size = 32;
+}

llvm/test/MC/RISCV/insn-invalid.s

+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+
+# Too many operands
+.insn i  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:33: error: invalid operand for instruction
+.insn r  0x43,  0,  0, fa0, fa1, fa2, fa3, fa4 # CHECK: :[[@LINE]]:44: error: invalid operand for instruction
+
+# Too few operands
+.insn r  0x33,  0,  0, a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+.insn i  0x13,  0,  a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+
+.insn r  0x33,  0,  0, a0, 13 # CHECK: :[[@LINE]]:28: error: invalid operand for instruction
+.insn i  0x13,  0, a0, a1, a2 # CHECK: :[[@LINE]]:28: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+.insn q  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:7: error: invalid instruction format
+
+# Make fake mnemonics we use to match these in the tablegened asm match table isn't exposed.
+.insn_i  0x13,  0,  a0, a1, 13, 14 # CHECK: :[[@LINE]]:1: error: unknown directive

llvm/test/MC/RISCV/insn.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc %s -triple riscv64 -mattr=+f -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+f < %s \
+# RUN:     | llvm-objdump --mattr=+f -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+f < %s \
+# RUN:     | llvm-objdump --mattr=+f -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ %s
+
+target:
+
+# CHECK-ASM: .insn r 51, 0, 0, a0, a1, a2
+# CHECK-ASM: encoding: [0x33,0x85,0xc5,0x00]
+# CHECK-OBJ: add a0, a1, a2
+.insn r  0x33,  0,  0, a0, a1, a2
+
+# CHECK-ASM: .insn i 19, 0, a0, a1, 13
+# CHECK-ASM: encoding: [0x13,0x85,0xd5,0x00]
+# CHECK-OBJ: addi a0, a1, 13
+.insn i  0x13,  0, a0, a1, 13
+
+# CHECK-ASM: .insn i 103, 0, a0, 10(a1)
+# CHECK-ASM: encoding: [0x67,0x85,0xa5,0x00]
+# CHECK-OBJ: jalr a0, 10(a1)
+.insn i  0x67,  0, a0, 10(a1)
+
+# CHECK-ASM: .insn i 3, 0, a0, 4(a1)
+# CHECK-ASM: encoding: [0x03,0x85,0x45,0x00]
+# CHECK-OBJ: lb a0, 4(a1)
+.insn i   0x3,  0, a0, 4(a1)
+
+# CHECK-ASM: .insn b 99, 0, a0, a1, target
+# CHECK-ASM: [0x63'A',A,0xb5'A',A]
+# CHECK-OBJ: beq a0, a1, 0x0 <target>
+.insn sb 0x63,  0, a0, a1, target
+
+# CHECK-ASM: .insn b 99, 0, a0, a1, target
+# CHECK-ASM: [0x63'A',A,0xb5'A',A]
+# CHECK-OBJ: beq a0, a1, 0x0 <target>
+.insn b  0x63,  0, a0, a1, target
+
+# CHECK-ASM: .insn s 35, 0, a0, 4(a1)
+# CHECK-ASM: encoding: [0x23,0x82,0xa5,0x00]
+# CHECK-OBJ: sb a0, 4(a1)
+.insn s  0x23,  0, a0, 4(a1)
+
+# CHECK-ASM: .insn u 55, a0, 4095
+# CHECK-ASM: encoding: [0x37,0xf5,0xff,0x00]
+# CHECK-OBJ: lui a0, 4095
+.insn u  0x37, a0, 0xfff
+
+# CHECK-ASM: .insn j 111, a0, target
+# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A]
+# CHECK-OBJ: jal a0, 0x0 <target>
+.insn uj 0x6f, a0, target
+
+# CHECK-ASM: .insn j 111, a0, target
+# CHECK-ASM: encoding: [0x6f,0bAAAA0101,A,A]
+# CHECK-OBJ: jal a0, 0x0 <target>
+.insn j  0x6f, a0, target
+
+# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3
+# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68]
+# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne
+.insn r  0x43,  0,  0, fa0, fa1, fa2, fa3
+
+# CHECK-ASM: .insn r4 67, 0, 0, fa0, fa1, fa2, fa3
+# CHECK-ASM: encoding: [0x43,0x85,0xc5,0x68]
+# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne
+.insn r4 0x43,  0,  0, fa0, fa1, fa2, fa3
+
+# CHECK-ASM: .insn i 3, 5, t1, -2048(t2)
+# CHECK-ASM: encoding: [0x03,0xd3,0x03,0x80]
+# CHECK-OBJ: lhu t1, -2048(t2)
+.insn i 0x3, 0x5, x6, %lo(2048)(x7)