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Differential D110307

[RISCV] Add missing op type OPERAND_UIMM2, OPERAND_UIMM3 and OPERAND_UIMM7 for verifyInstruction
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Authored by Jim on Sep 22 2021, 11:19 PM.

Details

Reviewers
craig.topper
Commits
rGfbacf5ad385c: [RISCV] Add missing op type OPERAND_UIMM2, OPERAND_UIMM3 and OPERAND_UIMM7 for…

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Event Timeline

Jim created this revision.Sep 22 2021, 11:19 PM
Herald added subscribers: vkmr, frasercrmck, evandro and 24 others. · View Herald TranscriptSep 22 2021, 11:19 PM
Jim requested review of this revision.Sep 22 2021, 11:19 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 22 2021, 11:19 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Jim added a reviewer: craig.topper.Sep 22 2021, 11:20 PM
craig.topper accepted this revision.Sep 22 2021, 11:23 PM

LGTM

This revision is now accepted and ready to land.Sep 22 2021, 11:23 PM
Jim mentioned this in D108602: [RISCV] Initial support .insn directive for the assembler..Sep 22 2021, 11:23 PM
Harbormaster completed remote builds in B125281: Diff 374446.Sep 22 2021, 11:41 PM
This revision was landed with ongoing or failed builds.Sep 23 2021, 4:40 AM
Closed by commit rGfbacf5ad385c: [RISCV] Add missing op type OPERAND_UIMM2, OPERAND_UIMM3 and OPERAND_UIMM7 for… (authored by Jim). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jim added a commit: rGfbacf5ad385c: [RISCV] Add missing op type OPERAND_UIMM2, OPERAND_UIMM3 and OPERAND_UIMM7 for….
Herald added a subscriber: achieveartificialintelligence. · View Herald TranscriptSep 23 2021, 4:40 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
9 lines

Diff 374506

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Show First 20 Lines • Show All 913 Lines • ▼ Show 20 Lines if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) { OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
const MachineOperand &MO = MI.getOperand(OI.index()); const MachineOperand &MO = MI.getOperand(OI.index());
if (MO.isImm()) { if (MO.isImm()) {
int64_t Imm = MO.getImm(); int64_t Imm = MO.getImm();
bool Ok; bool Ok;
switch (OpType) { switch (OpType) {
default: default:
llvm_unreachable("Unexpected operand type"); llvm_unreachable("Unexpected operand type");
case RISCVOp::OPERAND_UIMM2:
Ok = isUInt<2>(Imm);
break;
case RISCVOp::OPERAND_UIMM3:
Ok = isUInt<3>(Imm);
break;
case RISCVOp::OPERAND_UIMM4: case RISCVOp::OPERAND_UIMM4:
Ok = isUInt<4>(Imm); Ok = isUInt<4>(Imm);
break; break;
case RISCVOp::OPERAND_UIMM5: case RISCVOp::OPERAND_UIMM5:
Ok = isUInt<5>(Imm); Ok = isUInt<5>(Imm);
break; break;
case RISCVOp::OPERAND_UIMM7:
Ok = isUInt<7>(Imm);
break;
case RISCVOp::OPERAND_UIMM12: case RISCVOp::OPERAND_UIMM12:
Ok = isUInt<12>(Imm); Ok = isUInt<12>(Imm);
break; break;
case RISCVOp::OPERAND_SIMM12: case RISCVOp::OPERAND_SIMM12:
Ok = isInt<12>(Imm); Ok = isInt<12>(Imm);
break; break;
case RISCVOp::OPERAND_UIMM20: case RISCVOp::OPERAND_UIMM20:
Ok = isUInt<20>(Imm); Ok = isUInt<20>(Imm);
▲ Show 20 Lines • Show All 746 Lines • Show Last 20 Lines