[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.

[HsiangKai]

Remove redundant argument.

[HsiangKai]

Fix build errors.

[rogfer01]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

528

I think this might still add unflagged instructions.

Not sure what is the best way to flag them (I imagine we could traverse MBBI to the end of the MBB and invoke setFlag).

[rogfer01]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

528

(I imagine we could traverse MBBI to the end of the MBB and invoke setFlag).

Oh no, that wouldn't work. Please ignore me.

[HsiangKai]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

528

Yeah, there is no way to distinguish the caller of copyPhysReg() comes from prologue/epilogue or not.

[craig.topper]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

528

Can we just use BuildMI? We're not getting much from copyPhysReg here are we? It's just an ADDI with 0, I think.

[jrtc27]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

320

This should be an explicit argument rather than inferred

528

Downstream we'd have to add an if to use a capability move instruction for CHERI-RISC-V rather than getting to reuse the implementation in copyPhysReg, but that's hardly a huge burden. Ideally copyPhysReg would take an MIFlag but that's annoying to go and propagate everywhere just to avoid that.

[HsiangKai]

Address comments.

[asb]

This looks good to me, though it would be good to get a quick LGTM from someone who works more actively with the RVV code (e.g. Craig, Roger, or Fraser).

I think this one shouldn't be labeled as '[NFC]' as it will impact e.g. debug info generation.

[frasercrmck]

LGTM

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
   int64_t SlotSize = STI.getXLen() / 8;
   // Store return address to shadow call stack
   // s[w|d]  ra, 0(s2)
   // addi    s2, s2, [4|8]
   BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
       .addReg(RAReg)
       .addReg(SCSPReg)
-      .addImm(0);
+      .addImm(0)
+      .setMIFlag(MachineInstr::FrameSetup);
   BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
       .addReg(SCSPReg, RegState::Define)
       .addReg(SCSPReg)
-      .addImm(SlotSize);
+      .addImm(SlotSize)
+      .setMIFlag(MachineInstr::FrameSetup);
 }
 
 static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             const DebugLoc &DL) {
   if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
     return;
 
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
   int64_t SlotSize = STI.getXLen() / 8;
   // Load return address from shadow call stack
   // l[w|d]  ra, -[4|8](s2)
   // addi    s2, s2, -[4|8]
   BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
       .addReg(RAReg, RegState::Define)
       .addReg(SCSPReg)
-      .addImm(-SlotSize);
+      .addImm(-SlotSize)
+      .setMIFlag(MachineInstr::FrameDestroy);
   BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
       .addReg(SCSPReg, RegState::Define)
       .addReg(SCSPReg)
-      .addImm(-SlotSize);
+      .addImm(-SlotSize)
+      .setMIFlag(MachineInstr::FrameDestroy);
 }
 
 // Get the ID of the libcall used for spilling and restoring callee saved
 // registers. The ID is representative of the number of registers saved or
 // restored by the libcall, except it is zero-indexed - ID 0 corresponds to a
 // single register.
 static int getLibCallID(const MachineFunction &MF,
                         const std::vector<CalleeSavedInfo> &CSI) {
void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
                                            MachineBasicBlock::iterator MBBI,
                                            const DebugLoc &DL,
                                            int64_t Amount) const {
   assert(Amount != 0 && "Did not need to adjust stack pointer for RVV.");
 
   const RISCVInstrInfo *TII = STI.getInstrInfo();
   Register SPReg = getSPReg(STI);
   unsigned Opc = RISCV::ADD;
+  MachineInstr::MIFlag FrameFlag = MachineInstr::FrameDestroy;
   if (Amount < 0) {
     Amount = -Amount;
     Opc = RISCV::SUB;
+    FrameFlag = MachineInstr::FrameSetup;
   }
 
   // 1. Multiply the number of v-slots to the length of registers
-  Register FactorRegister =
-      TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, Amount);
+  Register FactorRegister = TII->getVLENFactoredAmount(
+      MF, MBB, MBBI, DL, Amount, /*IsPrologue=*/true, FrameFlag);
   // 2. SP = SP - RVV stack size
   BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
       .addReg(SPReg)
-      .addReg(FactorRegister, RegState::Kill);
+      .addReg(FactorRegister, RegState::Kill)
+      .setMIFlag(FrameFlag);
 }
 
 void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {
   MachineFrameInfo &MFI = MF.getFrameInfo();
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   const RISCVInstrInfo *TII = STI.getInstrInfo();
void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
 
   // Allocate space on the stack if necessary.
   adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
 
   // Emit ".cfi_def_cfa_offset RealStackSize"
   unsigned CFIIndex = MF.addFrameInst(
       MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize));
   BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-      .addCFIIndex(CFIIndex);
+      .addCFIIndex(CFIIndex)
+      .setMIFlag(MachineInstr::FrameSetup);
 
   const auto &CSI = MFI.getCalleeSavedInfo();
 
   // The frame pointer is callee-saved, and code has been generated for us to
   // save it to the stack. We need to skip over the storing of callee-saved
   // registers as the frame pointer must be modified after it has been saved
   // to the stack, not before.
   // FIXME: assumes exactly one instruction is used to save each callee-saved
if (FrameIdx < 0)
       Offset = FrameIdx * (int64_t) STI.getXLen() / 8;
     else
       Offset = MFI.getObjectOffset(Entry.getFrameIdx()) -
                RVFI->getLibCallStackSize();
     Register Reg = Entry.getReg();
     unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
         nullptr, RI->getDwarfRegNum(Reg, true), Offset));
     BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-        .addCFIIndex(CFIIndex);
+        .addCFIIndex(CFIIndex)
+        .setMIFlag(MachineInstr::FrameSetup);
   }
 
   // Generate new FP.
   if (hasFP(MF)) {
     if (STI.isRegisterReservedByUser(FPReg))
       MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
           MF.getFunction(), "Frame pointer required, but has been reserved."});
 
     adjustReg(MBB, MBBI, DL, FPReg, SPReg,
               RealStackSize - RVFI->getVarArgsSaveSize(),
               MachineInstr::FrameSetup);
 
     // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()"
     unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
         nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize()));
     BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-        .addCFIIndex(CFIIndex);
+        .addCFIIndex(CFIIndex)
+        .setMIFlag(MachineInstr::FrameSetup);
   }
 
   // Emit the second SP adjustment after saving callee saved registers.
   if (FirstSPAdjustAmount) {
     uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
     assert(SecondSPAdjustAmount > 0 &&
            "SecondSPAdjustAmount should be greater than zero");
     adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount,
               MachineInstr::FrameSetup);
 
     // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0",
     // don't emit an sp-based .cfi_def_cfa_offset
     if (!hasFP(MF)) {
       // Emit ".cfi_def_cfa_offset StackSize"
       unsigned CFIIndex = MF.addFrameInst(
           MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize()));
       BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-          .addCFIIndex(CFIIndex);
+          .addCFIIndex(CFIIndex)
+          .setMIFlag(MachineInstr::FrameSetup);
     }
   }
 
   if (RVVStackSize)
     adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize);
 
   if (hasFP(MF)) {
     // Realign Stack
     const RISCVRegisterInfo *RI = STI.getRegisterInfo();
     if (RI->hasStackRealignment(MF)) {
       Align MaxAlignment = MFI.getMaxAlign();
 
       const RISCVInstrInfo *TII = STI.getInstrInfo();
       if (isInt<12>(-(int)MaxAlignment.value())) {
         BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
             .addReg(SPReg)
-            .addImm(-(int)MaxAlignment.value());
+            .addImm(-(int)MaxAlignment.value())
+            .setMIFlag(MachineInstr::FrameSetup);
       } else {
         unsigned ShiftAmount = Log2(MaxAlignment);
         Register VR =
             MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
         BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
             .addReg(SPReg)
-            .addImm(ShiftAmount);
+            .addImm(ShiftAmount)
+            .setMIFlag(MachineInstr::FrameSetup);
         BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
             .addReg(VR)
-            .addImm(ShiftAmount);
+            .addImm(ShiftAmount)
+            .setMIFlag(MachineInstr::FrameSetup);
       }
       // FP will be used to restore the frame in the epilogue, so we need
       // another base register BP to record SP after re-alignment. SP will
       // track the current stack after allocating variable sized objects.
       if (hasBP(MF)) {
         // move BP, SP
         TII->copyPhysReg(MBB, MBBI, DL, BPReg, SPReg, false);
       }
     }
   }
 }
 
 void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();

llvm/lib/Target/RISCV/RISCVInstrInfo.h

public:
   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
                                        unsigned OpIdx1,
                                        unsigned OpIdx2) const override;
 
   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
                                       MachineInstr &MI,
                                       LiveVariables *LV) const override;
 
-  Register getVLENFactoredAmount(MachineFunction &MF, MachineBasicBlock &MBB,
-                                 MachineBasicBlock::iterator II,
-                                 const DebugLoc &DL, int64_t Amount) const;
+  Register getVLENFactoredAmount(
+      MachineFunction &MF, MachineBasicBlock &MBB,
+      MachineBasicBlock::iterator II, const DebugLoc &DL, int64_t Amount,
+      MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const;
 
   // Returns true if the given MI is an RVV instruction opcode for which we may
   // expect to see a FrameIndex operand. When CheckFIs is true, the instruction
   // must contain at least one FrameIndex operand.
   bool isRVVSpill(const MachineInstr &MI, bool CheckFIs) const;
 
   Optional<std::pair<unsigned, unsigned>>
   isRVVSpillForZvlsseg(unsigned Opcode) const;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 #undef CASE_WIDEOP_CHANGE_OPCODE_COMMON
 #undef CASE_WIDEOP_OPCODE_LMULS
 #undef CASE_WIDEOP_OPCODE_COMMON
 
 Register RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
                                                MachineBasicBlock &MBB,
                                                MachineBasicBlock::iterator II,
                                                const DebugLoc &DL,
-                                               int64_t Amount) const {
+                                               int64_t Amount,
+                                               MachineInstr::MIFlag Flag) const {
   assert(Amount > 0 && "There is no need to get VLEN scaled value.");
   assert(Amount % 8 == 0 &&
          "Reserve the stack by the multiple of one vector size.");
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
   int64_t NumOfVReg = Amount / 8;
 
   Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-  BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
+  BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL)
+    .setMIFlag(Flag);
   assert(isInt<32>(NumOfVReg) &&
          "Expect the number of vector registers within 32-bits.");
   if (isPowerOf2_32(NumOfVReg)) {
     uint32_t ShiftAmount = Log2_32(NumOfVReg);
     if (ShiftAmount == 0)
       return VL;
     BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
         .addReg(VL, RegState::Kill)
-        .addImm(ShiftAmount);
+        .addImm(ShiftAmount)
+        .setMIFlag(Flag);
   } else if (isPowerOf2_32(NumOfVReg - 1)) {
     Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     uint32_t ShiftAmount = Log2_32(NumOfVReg - 1);
     BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), ScaledRegister)
         .addReg(VL)
-        .addImm(ShiftAmount);
+        .addImm(ShiftAmount)
+        .setMIFlag(Flag);
     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), VL)
         .addReg(ScaledRegister, RegState::Kill)
-        .addReg(VL, RegState::Kill);
+        .addReg(VL, RegState::Kill)
+        .setMIFlag(Flag);
   } else if (isPowerOf2_32(NumOfVReg + 1)) {
     Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     uint32_t ShiftAmount = Log2_32(NumOfVReg + 1);
     BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), ScaledRegister)
         .addReg(VL)
-        .addImm(ShiftAmount);
+        .addImm(ShiftAmount)
+        .setMIFlag(Flag);
     BuildMI(MBB, II, DL, TII->get(RISCV::SUB), VL)
         .addReg(ScaledRegister, RegState::Kill)
-        .addReg(VL, RegState::Kill);
+        .addReg(VL, RegState::Kill)
+        .setMIFlag(Flag);
   } else {
     Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     if (!isInt<12>(NumOfVReg))
       movImm(MBB, II, DL, N, NumOfVReg);
-    else
+    else {
       BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), N)
           .addReg(RISCV::X0)
-          .addImm(NumOfVReg);
+          .addImm(NumOfVReg)
+          .setMIFlag(Flag);
+    }
     if (!MF.getSubtarget<RISCVSubtarget>().hasStdExtM())
       MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
           MF.getFunction(),
           "M-extension must be enabled to calculate the vscaled size/offset."});
     BuildMI(MBB, II, DL, TII->get(RISCV::MUL), VL)
         .addReg(VL, RegState::Kill)
-        .addReg(N, RegState::Kill);
+        .addReg(N, RegState::Kill)
+        .setMIFlag(Flag);
   }
 
   return VL;
 }
 
 static bool isRVVWholeLoadStore(unsigned Opcode) {
   switch (Opcode) {
   default:

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

stack:
   - { id: 2, offset: 0, size: 8, alignment: 8, stack-id: scalable-vector }
 body: |
   bb.0:
     liveins: $x10, $x11
 
     ; CHECK-LABEL: name: add_scalable_offset
     ; CHECK: liveins: $x10, $x11, $x1
     ; CHECK: $x2 = frame-setup ADDI $x2, -2032
-    ; CHECK: CFI_INSTRUCTION def_cfa_offset 2032
+    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 2032
     ; CHECK: SD killed $x1, $x2, 2024 :: (store 8 into %stack.3)
     ; CHECK: SD killed $x8, $x2, 2016 :: (store 8 into %stack.4)
-    ; CHECK: CFI_INSTRUCTION offset $x1, -8
-    ; CHECK: CFI_INSTRUCTION offset $x8, -16
+    ; CHECK: frame-setup CFI_INSTRUCTION offset $x1, -8
+    ; CHECK: frame-setup CFI_INSTRUCTION offset $x8, -16
     ; CHECK: $x8 = frame-setup ADDI $x2, 2032
-    ; CHECK: CFI_INSTRUCTION def_cfa $x8, 0
+    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $x8, 0
     ; CHECK: $x2 = frame-setup ADDI $x2, -240
-    ; CHECK: $x12 = PseudoReadVLENB
-    ; CHECK: $x2 = SUB $x2, killed $x12
+    ; CHECK: $x12 = frame-setup PseudoReadVLENB
+    ; CHECK: $x2 = frame-setup SUB $x2, killed $x12
     ; CHECK: dead $x0 = PseudoVSETVLI killed renamable $x11, 88, implicit-def $vl, implicit-def $vtype
     ; CHECK: renamable $v25 = PseudoVLE64_V_M1 killed renamable $x10, $noreg, 6, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
     ; CHECK: $x11 = PseudoReadVLENB
     ; CHECK: $x10 = LUI 1048575
     ; CHECK: $x10 = ADDIW killed $x10, 1824
     ; CHECK: $x10 = ADD $x8, killed $x10
     ; CHECK: $x10 = SUB killed $x10, killed $x11
     ; CHECK: VS1R_V killed renamable $v25, killed renamable $x10
-    ; CHECK: $x10 = PseudoReadVLENB
-    ; CHECK: $x2 = ADD $x2, killed $x10
+    ; CHECK: $x10 = frame-destroy PseudoReadVLENB
+    ; CHECK: $x2 = frame-destroy ADD $x2, killed $x10
     ; CHECK: $x2 = frame-destroy ADDI $x2, 240
     ; CHECK: $x8 = LD $x2, 2016 :: (load 8 from %stack.4)
     ; CHECK: $x1 = LD $x2, 2024 :: (load 8 from %stack.3)
     ; CHECK: $x2 = frame-destroy ADDI $x2, 2032
     ; CHECK: PseudoRET
     %1:gpr = COPY $x11
     %0:gpr = COPY $x10
     %2:vr = PseudoVLE64_V_M1 %0, %1, 6 :: (load unknown-size from %ir.pa, align 8)
     %3:gpr = ADDI %stack.2, 0
     VS1R_V killed %2:vr, %3:gpr
     PseudoRET
 
 ...

llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir

- { id: 2, name: '', type: spill-slot, offset: 0, size: 400, alignment: 8,
       stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 body:             |
   ; CHECK-LABEL: name: spillslot
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK:   liveins: $x12, $x1, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27
   ; CHECK:   $x2 = frame-setup ADDI $x2, -2032
-  ; CHECK:   CFI_INSTRUCTION def_cfa_offset 2032
+  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 2032
   ; CHECK:   SD killed $x1, $x2, 2024 :: (store 8 into %stack.3)
   ; CHECK:   SD killed $x8, $x2, 2016 :: (store 8 into %stack.4)
   ; CHECK:   SD killed $x9, $x2, 2008 :: (store 8 into %stack.5)
   ; CHECK:   SD killed $x18, $x2, 2000 :: (store 8 into %stack.6)
   ; CHECK:   SD killed $x19, $x2, 1992 :: (store 8 into %stack.7)
   ; CHECK:   SD killed $x20, $x2, 1984 :: (store 8 into %stack.8)
   ; CHECK:   SD killed $x21, $x2, 1976 :: (store 8 into %stack.9)
   ; CHECK:   SD killed $x22, $x2, 1968 :: (store 8 into %stack.10)
   ; CHECK:   SD killed $x23, $x2, 1960 :: (store 8 into %stack.11)
   ; CHECK:   SD killed $x24, $x2, 1952 :: (store 8 into %stack.12)
   ; CHECK:   SD killed $x25, $x2, 1944 :: (store 8 into %stack.13)
   ; CHECK:   SD killed $x26, $x2, 1936 :: (store 8 into %stack.14)
   ; CHECK:   SD killed $x27, $x2, 1928 :: (store 8 into %stack.15)
-  ; CHECK:   CFI_INSTRUCTION offset $x1, -8
-  ; CHECK:   CFI_INSTRUCTION offset $x8, -16
-  ; CHECK:   CFI_INSTRUCTION offset $x9, -24
-  ; CHECK:   CFI_INSTRUCTION offset $x18, -32
-  ; CHECK:   CFI_INSTRUCTION offset $x19, -40
-  ; CHECK:   CFI_INSTRUCTION offset $x20, -48
-  ; CHECK:   CFI_INSTRUCTION offset $x21, -56
-  ; CHECK:   CFI_INSTRUCTION offset $x22, -64
-  ; CHECK:   CFI_INSTRUCTION offset $x23, -72
-  ; CHECK:   CFI_INSTRUCTION offset $x24, -80
-  ; CHECK:   CFI_INSTRUCTION offset $x25, -88
-  ; CHECK:   CFI_INSTRUCTION offset $x26, -96
-  ; CHECK:   CFI_INSTRUCTION offset $x27, -104
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x1, -8
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x8, -16
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x9, -24
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x18, -32
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x19, -40
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x20, -48
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x21, -56
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x22, -64
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x23, -72
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x24, -80
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x25, -88
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x26, -96
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $x27, -104
   ; CHECK:   $x8 = frame-setup ADDI $x2, 2032
-  ; CHECK:   CFI_INSTRUCTION def_cfa $x8, 0
+  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa $x8, 0
   ; CHECK:   $x2 = frame-setup ADDI $x2, -272
-  ; CHECK:   $x10 = PseudoReadVLENB
-  ; CHECK:   $x11 = ADDI $x0, 51
-  ; CHECK:   $x10 = MUL killed $x10, killed $x11
-  ; CHECK:   $x2 = SUB $x2, killed $x10
-  ; CHECK:   $x2 = ANDI $x2, -128
+  ; CHECK:   $x10 = frame-setup PseudoReadVLENB
+  ; CHECK:   $x11 = frame-setup ADDI $x0, 51
+  ; CHECK:   $x10 = frame-setup MUL killed $x10, killed $x11
+  ; CHECK:   $x2 = frame-setup SUB $x2, killed $x10
+  ; CHECK:   $x2 = frame-setup ANDI $x2, -128
   ; CHECK:   dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype
   ; CHECK:   renamable $v25 = PseudoVMV_V_X_M1 killed renamable $x12, $noreg, 16, implicit $vl, implicit $vtype
   ; CHECK:   $x11 = PseudoReadVLENB
   ; CHECK:   $x10 = ADDI $x0, 50
   ; CHECK:   $x11 = MUL killed $x11, killed $x10
   ; CHECK:   $x10 = LUI 1
   ; CHECK:   $x10 = ADDIW killed $x10, -1896
   ; CHECK:   $x10 = ADD $x2, killed $x10

llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir

 name: foo
 tracksRegLiveness: true
 stack:
   - { id: 0, stack-id: scalable-vector, offset: 0, size: 8, alignment: 8 }
 body: |
   ; CHECK-LABEL: name: foo
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   CFI_INSTRUCTION def_cfa_offset 0
-  ; CHECK:   $x10 = PseudoReadVLENB
-  ; CHECK:   $x10 = SLLI killed $x10, 1
-  ; CHECK:   $x2 = SUB $x2, killed $x10
+  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 0
+  ; CHECK:   $x10 = frame-setup PseudoReadVLENB
+  ; CHECK:   $x10 = frame-setup SLLI killed $x10, 1
+  ; CHECK:   $x2 = frame-setup SUB $x2, killed $x10
   ; CHECK: bb.1:
-  ; CHECK:   $x10 = PseudoReadVLENB
-  ; CHECK:   $x10 = SLLI killed $x10, 1
-  ; CHECK:   $x2 = ADD $x2, killed $x10
+  ; CHECK:   $x10 = frame-destroy PseudoReadVLENB
+  ; CHECK:   $x10 = frame-destroy SLLI killed $x10, 1
+  ; CHECK:   $x2 = frame-destroy ADD $x2, killed $x10
   ; CHECK:   PseudoRET
   bb.0:
   bb.1:
     PseudoRET

llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

stack:
   - { id: 0, offset: 0, size: 64, alignment: 8, stack-id: scalable-vector }
 body: |
   bb.0:
     liveins: $x10, $x11
 
     ; CHECK-LABEL: name: zvlsseg_spill
     ; CHECK: liveins: $x10, $x11
     ; CHECK: $x2 = frame-setup ADDI $x2, -16
-    ; CHECK: CFI_INSTRUCTION def_cfa_offset 16
-    ; CHECK: $x12 = PseudoReadVLENB
-    ; CHECK: $x12 = SLLI killed $x12, 3
-    ; CHECK: $x2 = SUB $x2, killed $x12
+    ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    ; CHECK: $x12 = frame-setup PseudoReadVLENB
+    ; CHECK: $x12 = frame-setup SLLI killed $x12, 3
+    ; CHECK: $x2 = frame-setup SUB $x2, killed $x12
     ; CHECK: dead $x0 = PseudoVSETVLI killed renamable $x11, 88, implicit-def $vl, implicit-def $vtype
     ; CHECK: $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 renamable $x10, $noreg, 6, implicit $vl, implicit $vtype
     ; CHECK: $x11 = ADDI $x2, 16
     ; CHECK: $x12 = PseudoReadVLENB
     ; CHECK: PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, killed $x11, killed $x12
     ; CHECK: $x11 = ADDI $x2, 16
     ; CHECK: $x12 = PseudoReadVLENB
     ; CHECK: dead renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 killed $x11, killed $x12, implicit-def $v8
     ; CHECK: VS1R_V killed $v8, killed renamable $x10
-    ; CHECK: $x10 = PseudoReadVLENB
-    ; CHECK: $x10 = SLLI killed $x10, 3
-    ; CHECK: $x2 = ADD $x2, killed $x10
+    ; CHECK: $x10 = frame-destroy PseudoReadVLENB
+    ; CHECK: $x10 = frame-destroy SLLI killed $x10, 3
+    ; CHECK: $x2 = frame-destroy ADD $x2, killed $x10
     ; CHECK: $x2 = frame-destroy ADDI $x2, 16
     ; CHECK: PseudoRET
     %0:gpr = COPY $x10
     %1:gpr = COPY $x11
     $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 %0, %1, 6
     PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, %stack.0, $x0
     renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 %stack.0, $x0
     VS1R_V killed $v8, %0:gpr
     PseudoRET
 ...