[DAGCombine] reassoc flag shouldn't enable contract

[jsji]

Summary

According to IR LangRef, the FMF flag:

contract
Allow floating-point contraction (e.g. fusing a multiply followed by an
addition into a fused multiply-and-add).

reassoc
Allow reassociation transformations for floating-point instructions.
This may dramatically change results in floating-point.

My understanding is that these two flags shouldn't imply each other,
as we might have a SDNode that can be reassociated with others, but
not contractble.

eg: We may want following fmul/fad/fsub to freely reassoc, but don't
want fma being generated here.

%F = fmul reassoc double %A, %B         ; <double> [#uses=1]
%G = fmul reassoc double %C, %D         ; <double> [#uses=1]
%H = fadd reassoc double %F, %G         ; <double> [#uses=1]
%I = fsub reassoc double %H, %E         ; <double> [#uses=1]

Before https://reviews.llvm.org/D45710, reassoc flag actually
did not imply isContratable either.

static bool isContractable(SDNode *N) {

SDNodeFlags F = N->getFlags();
return F.hasAllowContract() || F.hasUnsafeAlgebra();

}

The current implementation also only check the flag in fadd node,
ignoring fmul node, this patch update that as well.

[dmgreen]

llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll

3

I can fix this.

[jsji]

llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll

3

Thanks!

[dfukalov]

Changes in AMDGPU tests LGTM, thanks!

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12875

Nit: it seems this function is too trivial now and we can remove it?

13110

Nit: move CanFuse definition two hundreds lines down to its uses?

[jsji]

Address review comments.

[qiucf]

Thanks for the patch. It looks reasonable since we've split effect of contract from reassoc (like D89527), and this one does the missing reverse.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13131

SDValue overloaded '->' operator.

llvm/test/CodeGen/PowerPC/fma-aggr-FMF.ll

26

extra space

[jsji]

Address review comments.

[jsji]

Rebase to pick up Dave's D104255.

[qiucf]

LGTM if no further comments from others @spatel

[spatel]

In code that I've looked at (mostly C compiled with -ffast-math), we always have contract when we have reassoc, so I don't see much practical difference.
Can you explain more how we could benefit from this change - in the example in the description, we would have 4 instructions rather than 3 if we use FMA - is that better?
We should duplicate (instead of edit) at least a few of the tests, so we can verify that the existing tests do not form FMA now. That could also be used to show an advantage from not forming FMA.

llvm/test/CodeGen/PowerPC/fmf-propagation.ll

107

This comment was not valid even before this patch.

[jsji]

In D104247#2827089, @spatel wrote:

In code that I've looked at (mostly C compiled with -ffast-math), we always have contract when we have reassoc, so I don't see much practical difference.
Can you explain more how we could benefit from this change - in the example in the description, we would have 4 instructions rather than 3 if we use FMA - is that better?

Yes, you are right, the performance of having FMA should be better. However, we have quite some scenarios that users care about precision more than performance, they want to precise control of when FMA can be generated. So The major motivation of this is to ensure that we respect the IR semantics. For users that care about performance, we still can get them through default global option or emitting respect flag in IR.

We should duplicate (instead of edit) at least a few of the tests, so we can verify that the existing tests do not form FMA now. That could also be used to show an advantage from not forming FMA.

Sure, I can do that . Thanks!

[pengfei]

In D104247#2827116, @jsji wrote:

In D104247#2827089, @spatel wrote:

In code that I've looked at (mostly C compiled with -ffast-math), we always have contract when we have reassoc, so I don't see much practical difference.
Can you explain more how we could benefit from this change - in the example in the description, we would have 4 instructions rather than 3 if we use FMA - is that better?

Yes, you are right, the performance of having FMA should be better. However, we have quite some scenarios that users care about precision more than performance, they want to precise control of when FMA can be generated. So The major motivation of this is to ensure that we respect the IR semantics. For users that care about performance, we still can get them through default global option or emitting respect flag in IR.

AFAIU, the use of FMA doesn't decline the precision (but may improve a bit, which is also unexpected in some circumstance). But reassoc flag does affect precision much. We had some discussion on D99675, contract is acceptable even we want to disable reassoc for the sake of precision. That said, contract has much less influence on precision than reassoc. So I don't see any necessity to use reassoc without contract.

[jsji]

In D104247#2828581, @pengfei wrote:

In D104247#2827116, @jsji wrote:

In D104247#2827089, @spatel wrote:

In code that I've looked at (mostly C compiled with -ffast-math), we always have contract when we have reassoc, so I don't see much practical difference.
Can you explain more how we could benefit from this change - in the example in the description, we would have 4 instructions rather than 3 if we use FMA - is that better?

Yes, you are right, the performance of having FMA should be better. However, we have quite some scenarios that users care about precision more than performance, they want to precise control of when FMA can be generated. So The major motivation of this is to ensure that we respect the IR semantics. For users that care about performance, we still can get them through default global option or emitting respect flag in IR.

AFAIU, the use of FMA doesn't decline the precision (but may improve a bit, which is also unexpected in some circumstance).

Yes, you are right. FMA on PowerPC improves precision, which is sometime unexpected to math library writers.

We had some discussion on D99675, contract is acceptable even we want to disable reassoc for the sake of precision.
That said, contract has much less influence on precision than reassoc. So I don't see any necessity to use reassoc without contract.

I agree in general.
However, there are some specific cases that IR producer might generate reassoc flag for general reassociation, not intending for contract,
and current implementation is causing confusions and failures.

As reassoc and contract are defined as two independent flags,
I think we should distinguish them in implementation, regardless of whether it is really meaningful to use reassoc without contract?

Or another choice is we can update the definition of these two flags, saying that reassoc always imply contract,
but this doesn't looks a clear definition to me.

[jsji]

Address comments -- updated testcases.

[spatel]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13263

If we still allow the global/deprecated UnsafeFPMath option to enable FMA formation, we are keeping a side-channel way to override the FMF. That is, the global setting is effectively a replacement for "reassoc" in (many?) regression tests.

I think this is not changing the logic before this patch, so that's fine, but do you plan to fix that too?

llvm/test/CodeGen/PowerPC/fma-assoc.ll

323

Ideally, we would remove the RUN lines that have that setting and rely on IR-level FMF instead. This may require duplicating some tests and updating the FMF.

We are trying to rely on the IR and node-level alone if possible - see D99080 for discussion.

llvm/test/CodeGen/PowerPC/fma-precision.ll

2

Similar to the earlier inline comment (see D99080 for details). Can we avoid using the global flag by updating FMF instead?

[jsji]

Address comments.

[jsji]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13263

Yes, I planned to fix this -- by allowing it for global flag as well , not only UnsafeFPMath.

13263

Oh, just to double confirm, we will still allow global options to override FMF (UnSafeFPMath, -ffast-math, etc), right? FMF is great, but sometimes global options will be more handy for front-end or IR producers. It may take time for IR producers to transit to FMF only?

llvm/test/CodeGen/PowerPC/fma-assoc.ll

323

Can we do this in another follow up patch? As you mentioned in D99080, I believe there are quite some tests needs updates.

[spatel]

LGTM.
Since we are opting for a definition of reassoc that is not a superset of the other flags, it might be worth seeing if transforms related to arcp and afn are similarly affected.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13263

The goal of IR- and node-level FMF is to obsolete/deprecate the global options. But this has been the case for many years now, so I have no guess for how much longer it will take. :)

llvm/test/CodeGen/PowerPC/fma-assoc.ll

323

Sure - this is going to require manual inspection, adding tests, etc. I just wanted to point out that fixing the global option might not be worth the effort (if the code is behaving as expected using FMF).

[jsji]

In D104247#2831159, @spatel wrote:

LGTM.
Since we are opting for a definition of reassoc that is not a superset of the other flags, it might be worth seeing if transforms related to arcp and afn are similarly affected.

Thanks, sure, will check.

[mcberg2017]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13263

Some of these patterns below have operands/operations which change order, they should be audited and checked reassoc FMF to enable. Perhaps a follow on change?

[jsji]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13263

Good point, sure, will follow up.

[spatel]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13263

Sorry, I missed this difference. The patch as-is is allowing miscompiles IIUC. For example, this test of the pattern:

; x*y + u*v - z
define float @f(float %x, float %y, float %z, float %u, float %v) {
  %xy = fmul contract float %x, %y
  %uv = fmul contract float %u, %v
  %xyuv = fadd contract float %xy, %uv
  %xyuvz = fsub contract float %xyuv, %z
  ret float %xyuvz
}

We are not allowed to fuse the trailing fsub into fma based on what we decided in D89527, but that's what happens now with:

$ llc -o - fma.ll -mtriple=powerpc64le -ppc-asm-full-reg-names
	xsmsubasp f3, f4, f5 ; u*v - z
	xsmaddasp f3, f1, f2 ; x*y + (u*v - z)
	fmr f1, f3
	blr

[jsji]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13263

Yes, working on it.

[jsji]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13263

The specific case ; x*y + u*v - z , the behavior is not changed by D104247. It has been like this for a long time. But yeah, I am looking into these patterns now.

[jsji]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13263

https://reviews.llvm.org/D104723 posted for this.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

for (const SDValue &Op : BV->op_values()) {
     // For big endian targets, swap the order of the pieces of each element.
     if (DAG.getDataLayout().isBigEndian())
       std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
   }
 
   return DAG.getBuildVector(VT, DL, Ops);
 }
 
 static bool isContractable(SDNode *N) {
   SDNodeFlags F = N->getFlags();
-  return F.hasAllowContract() || F.hasAllowReassociation();
+  return F.hasAllowContract();
 }
 
 /// Try to perform FMA combining on a given FADD node.
 SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N->getValueType(0);
   SDLoc SL(N);
 
   const TargetOptions &Options = DAG.getTarget().Options;
 
   // Floating-point multiply-add with intermediate rounding.
   bool HasFMAD = (LegalOperations && TLI.isFMADLegal(DAG, N));
 
   // Floating-point multiply-add without intermediate rounding.
   bool HasFMA =
       TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT) &&
       (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
 
   // No valid opcode, do not combine.
   if (!HasFMAD && !HasFMA)
     return SDValue();
 
-  bool CanFuse = Options.UnsafeFPMath || isContractable(N);
   bool CanReassociate =
       Options.UnsafeFPMath || N->getFlags().hasAllowReassociation();
   bool AllowFusionGlobally = (Options.AllowFPOpFusion == FPOpFusion::Fast ||
-                              CanFuse || HasFMAD);
+                              Options.UnsafeFPMath || HasFMAD);
   // If the addition is not contractable, do not combine.
   if (!AllowFusionGlobally && !isContractable(N))
     return SDValue();
 
   if (TLI.generateFMAsInMachineCombiner(VT, OptLevel))
     return SDValue();
 
   // Always prefer FMAD to FMA for precision.
bool HasFMA =
       TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT) &&
       (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT));
 
   // No valid opcode, do not combine.
   if (!HasFMAD && !HasFMA)
     return SDValue();
 
   const SDNodeFlags Flags = N->getFlags();
   bool CanFuse = Options.UnsafeFPMath || isContractable(N);
   bool AllowFusionGlobally = (Options.AllowFPOpFusion == FPOpFusion::Fast ||
-                              CanFuse || HasFMAD);
+                              Options.UnsafeFPMath || HasFMAD);
 
   // If the subtraction is not contractable, do not combine.
   if (!AllowFusionGlobally && !isContractable(N))
     return SDValue();
 
   if (TLI.generateFMAsInMachineCombiner(VT, OptLevel))
     return SDValue();
 
   // Always prefer FMAD to FMA for precision.
   unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
   bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
   bool NoSignedZero = Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros();
 
   // Is the node an FMUL and contractable either due to global flags or
   // SDNodeFlags.
   auto isContractableFMUL = [AllowFusionGlobally](SDValue N) {
     if (N.getOpcode() != ISD::FMUL)
       return false;
     return AllowFusionGlobally || isContractable(N.getNode());
   };
 
   // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
   auto tryToFoldXYSubZ = [&](SDValue XY, SDValue Z) {
     if (isContractableFMUL(XY) && (Aggressive || XY->hasOneUse())) {
       return DAG.getNode(PreferredFusedOpcode, SL, VT, XY.getOperand(0),
                          XY.getOperand(1), DAG.getNode(ISD::FNEG, SL, VT, Z));
     }
if (N00.getOpcode() == ISD::FP_EXTEND) {
                         DAG.getNode(ISD::FP_EXTEND, SL, VT, N000.getOperand(1)),
                         N1));
       }
     }
   }
 
   // More folding opportunities when target permits.
   if (Aggressive) {
     // fold (fsub (fma x, y, (fmul u, v)), z)
     //   -> (fma x, y (fma u, v, (fneg z)))
     if (CanFuse && N0.getOpcode() == PreferredFusedOpcode &&
         isContractableFMUL(N0.getOperand(2)) && N0->hasOneUse() &&
         N0.getOperand(2)->hasOneUse()) {
       return DAG.getNode(PreferredFusedOpcode, SL, VT, N0.getOperand(0),
                          N0.getOperand(1),
                          DAG.getNode(PreferredFusedOpcode, SL, VT,
                                      N0.getOperand(2).getOperand(0),

llvm/test/CodeGen/AArch64/fadd-combines.ll

 ; requires reassociation to fuse with c*d.
 
 define float @fadd_fma_fmul_fmf(float %a, float %b, float %c, float %d, float %n0) nounwind {
 ; CHECK-LABEL: fadd_fma_fmul_fmf:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fmadd s2, s2, s3, s4
 ; CHECK-NEXT:    fmadd s0, s0, s1, s2
 ; CHECK-NEXT:    ret
-  %m1 = fmul float %a, %b
-  %m2 = fmul float %c, %d
+  %m1 = fmul contract float %a, %b
+  %m2 = fmul contract float %c, %d
   %a1 = fadd contract float %m1, %m2
-  %a2 = fadd reassoc float %n0, %a1
+  %a2 = fadd contract reassoc float %n0, %a1
   ret float %a2
 }
 
 ; Not minimum FMF.
 
 define float @fadd_fma_fmul_2(float %a, float %b, float %c, float %d, float %n0) nounwind {
 ; CHECK-LABEL: fadd_fma_fmul_2:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/vldn_shuffle.ll

 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    add x9, x0, x8
 ; CHECK-NEXT:    add x10, x1, x8
 ; CHECK-NEXT:    ld2 { v0.4s, v1.4s }, [x9]
 ; CHECK-NEXT:    ld2 { v2.4s, v3.4s }, [x10]
 ; CHECK-NEXT:    add x8, x8, #32 // =32
 ; CHECK-NEXT:    cmp x8, #2, lsl #12 // =8192
 ; CHECK-NEXT:    fmul v4.4s, v2.4s, v0.4s
-; CHECK-NEXT:    fmla v4.4s, v1.4s, v3.4s
+; CHECK-NEXT:    fmla v4.4s, v3.4s, v1.4s
 ; CHECK-NEXT:    str q4, [x2], #16
 ; CHECK-NEXT:    b.ne .LBB3_1
 ; CHECK-NEXT:  // %bb.2: // %while.end
 ; CHECK-NEXT:    ret
 entry:
   br label %vector.body
 
 vector.body:                                      ; preds = %vector.body, %entry

llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll

 ; GFX10-FLUSH:  v_add_f16_e32
 ; GFX10-DENORM: v_fmac_f16_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
 
 define amdgpu_kernel void @fmul_fadd_contract_f16(half addrspace(1)* %out, half addrspace(1)* %in1,
                          half addrspace(1)* %in2, half addrspace(1)* %in3) #0 {
   %r0 = load half, half addrspace(1)* %in1
   %r1 = load half, half addrspace(1)* %in2
   %r2 = load half, half addrspace(1)* %in3
-  %mul = fmul half %r0, %r1
+  %mul = fmul contract half %r0, %r1
   %add = fadd contract half %mul, %r2
   store half %add, half addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}fmuladd_2.0_a_b_f16
 ; GCN: {{buffer|flat|global}}_load_ushort [[R1:v[0-9]+]],
 ; GCN: {{buffer|flat|global}}_load_ushort [[R2:v[0-9]+]],

llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll

 ; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32
 
 ; GCN-DENORM-FASTFMA: v_fma_f32
 define amdgpu_kernel void @fmul_fadd_contract_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
                            float addrspace(1)* %in2, float addrspace(1)* %in3) #0 {
   %r0 = load volatile float, float addrspace(1)* %in1
   %r1 = load volatile float, float addrspace(1)* %in2
   %r2 = load volatile float, float addrspace(1)* %in3
-  %mul = fmul float %r0, %r1
+  %mul = fmul contract float %r0, %r1
   %add = fadd contract float %mul, %r2
   store float %add, float addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}fmuladd_2.0_a_b_f32
 ; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]],
 ; GCN: {{buffer|flat|global}}_load_dword [[R2:v[0-9]+]],

llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll

 ; GCN-LABEL: {{^}}fmul_fadd_contract_f64:
 ; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
 
 define amdgpu_kernel void @fmul_fadd_contract_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
                            double addrspace(1)* %in2, double addrspace(1)* %in3) #0 {
   %r0 = load double, double addrspace(1)* %in1
   %r1 = load double, double addrspace(1)* %in2
   %r2 = load double, double addrspace(1)* %in3
-  %tmp = fmul double %r0, %r1
+  %tmp = fmul contract double %r0, %r1
   %r3 = fadd contract double %tmp, %r2
   store double %r3, double addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}fadd_a_a_b_f64:
 ; GCN: {{buffer|flat}}_load_dwordx2 [[R1:v\[[0-9]+:[0-9]+\]]],
 ; GCN: {{buffer|flat}}_load_dwordx2 [[R2:v\[[0-9]+:[0-9]+\]]],

llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll

 ; GFX9-FLUSH: v_pk_add_f16 {{v[0-9]+, v[0-9]+, v[0-9]+}}
 
 ; GFX9-DENORM: v_pk_fma_f16 {{v[0-9]+, v[0-9]+, v[0-9]+}}
 define amdgpu_kernel void @fmul_fadd_contract_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in1,
                          <2 x half> addrspace(1)* %in2, <2 x half> addrspace(1)* %in3) #0 {
   %r0 = load <2 x half>, <2 x half> addrspace(1)* %in1
   %r1 = load <2 x half>, <2 x half> addrspace(1)* %in2
   %r2 = load <2 x half>, <2 x half> addrspace(1)* %in3
-  %r3 = fmul <2 x half> %r0, %r1
+  %r3 = fmul contract <2 x half> %r0, %r1
   %r4 = fadd contract <2 x half> %r3, %r2
   store <2 x half> %r4, <2 x half> addrspace(1)* %out
   ret void
 }
 
 
 ; GCN-LABEL: {{^}}fmuladd_2.0_a_b_v2f16:
 ; GCN: {{buffer|flat|global}}_load_dword [[R1:v[0-9]+]],

llvm/test/CodeGen/PowerPC/combine-fneg.ll

 ; CHECK-NEXT:    xvnmsubadp 1, 0, 2
 ; CHECK-NEXT:    xvnmaddadp 2, 2, 1
 ; CHECK-NEXT:    xvmuldp 34, 34, 2
 ; CHECK-NEXT:    xvmuldp 35, 35, 2
 ; CHECK-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0
   %splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer
-  %div = fdiv reassoc nsz arcp ninf <4 x double> %a1, %splat.splat
-  %sub = fsub reassoc nsz <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
+  %div = fdiv contract reassoc nsz arcp ninf <4 x double> %a1, %splat.splat
+  %sub = fsub contract reassoc nsz <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
   ret <4 x double> %sub
 }

llvm/test/CodeGen/PowerPC/fdiv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 -vec-extabi | FileCheck %s
 
 define dso_local float @foo_nosw(float %0, float %1) local_unnamed_addr {
 ; CHECK-LABEL: foo_nosw:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsdivsp 1, 1, 2
 ; CHECK-NEXT:    blr
-  %3 = fdiv reassoc arcp nsz float %0, %1
+  %3 = fdiv contract reassoc arcp nsz float %0, %1
   ret float %3
 }
 
 define dso_local float @foo(float %0, float %1) local_unnamed_addr {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsresp 3, 2
 ; CHECK-NEXT:    xsmulsp 0, 1, 3
 ; CHECK-NEXT:    xsnmsubasp 1, 2, 0
 ; CHECK-NEXT:    xsmaddasp 0, 3, 1
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    blr
-  %3 = fdiv reassoc arcp nsz ninf float %0, %1
+  %3 = fdiv contract reassoc arcp nsz ninf float %0, %1
   ret float %3
 }

llvm/test/CodeGen/PowerPC/fma-aggr-FMF.ll

 }
 
 ; There is no contract on the mul with no extra use so we can't fuse that.
 ; Since we are fusing with the mul with an extra use, the fmul needs to stick
 ; around beside the fma.
 define float @no_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) {
 ; CHECK-LABEL: no_fma_with_fewer_uses:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xsmulsp 0, 1, 2
-; CHECK-NEXT:    fmr 1, 0
-; CHECK-NEXT:    xsmaddasp 1, 3, 4
-; CHECK-NEXT:    xsdivsp 1, 0, 1
+; CHECK-NEXT:    xsmulsp 0, 3, 4
+; CHECK-NEXT:    xsmulsp 3, 1, 2 
+; CHECK-NEXT:    xsmaddasp 0, 1, 2
+; CHECK-NEXT:    xsdivsp 1, 3, 0
 ; CHECK-NEXT:    blr
   %mul1 = fmul contract float %f1, %f2
   %mul2 = fmul float %f3, %f4
   %add = fadd contract float %mul1, %mul2
   %second_use_of_mul1 = fdiv float %mul1, %add
   ret float %second_use_of_mul1
 }

llvm/test/CodeGen/PowerPC/fma-assoc.ll

; CHECK-VSX-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
   %I = fadd reassoc double %E, %H         ; <double> [#uses=1]
   ret double %I
 }
 
 define double @test_reassoc_FMSUB_ASSOC1(double %A, double %B, double %C,
 ; CHECK-LABEL: test_reassoc_FMSUB_ASSOC1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmsub 0, 3, 4, 5
 ; CHECK-NEXT:    fmadd 1, 1, 2, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC1:
 ; CHECK-VSX:       # %bb.0:
 ; CHECK-VSX-NEXT:    xsmsubmdp 3, 4, 5
 ; CHECK-VSX-NEXT:    xsmaddadp 3, 1, 2
 ; CHECK-VSX-NEXT:    fmr 1, 3
 ; CHECK-VSX-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
-  %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
-  %I = fsub reassoc double %H, %E         ; <double> [#uses=1]
+  %H = fadd contract reassoc double %F, %G         ; <double> [#uses=1]
+  %I = fsub contract reassoc double %H, %E         ; <double> [#uses=1]
   ret double %I
 }
 
 define double @test_reassoc_FMSUB_ASSOC2(double %A, double %B, double %C,
 ; CHECK-LABEL: test_reassoc_FMSUB_ASSOC2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmul 0, 3, 4
 ; CHECK-NEXT:    fmadd 0, 1, 2, 0

 ; CHECK-VSX:       # %bb.0:
 ; CHECK-VSX-NEXT:    xsnmsubmdp 3, 4, 5
 ; CHECK-VSX-NEXT:    xsnmsubadp 3, 1, 2
 ; CHECK-VSX-NEXT:    fmr 1, 3
 ; CHECK-VSX-NEXT:    blr
                                  double %D, double %E) {
   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
-  %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
-  %I = fsub reassoc nsz double %E, %H         ; <double> [#uses=1]
+  %H = fadd contract reassoc double %F, %G         ; <double> [#uses=1]
+  %I = fsub contract reassoc nsz double %E, %H         ; <double> [#uses=1]
   ret double %I
 }
 
 define double @test_reassoc_FMADD_ASSOC_EXT1(float %A, float %B, double %C,
 ; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmadd 0, 1, 2, 5
 ; CHECK-NEXT:    fmadd 1, 3, 4, 0

llvm/test/CodeGen/PowerPC/fma-combine.ll

 ; CHECK-NEXT:    fmr 4, 3
 ; CHECK-NEXT:    xsmaddasp 3, 2, 0
 ; CHECK-NEXT:    xsnmaddasp 4, 2, 0
 ; CHECK-NEXT:    xsmaddasp 1, 2, 3
 ; CHECK-NEXT:    xsmaddasp 1, 4, 2
 ; CHECK-NEXT:    blr
   %tmp = load float, float* undef, align 4
   %tmp2 = load float, float* undef, align 4
-  %tmp3 = fmul reassoc float %tmp, 0x3FE372D780000000
-  %tmp4 = fadd reassoc float %tmp3, 1.000000e+00
-  %tmp5 = fmul reassoc float %tmp2, %tmp4
+  %tmp3 = fmul contract reassoc float %tmp, 0x3FE372D780000000
+  %tmp4 = fadd contract reassoc float %tmp3, 1.000000e+00
+  %tmp5 = fmul contract reassoc float %tmp2, %tmp4
   %tmp6 = load float, float* undef, align 4
   %tmp7 = load float, float* undef, align 4
-  %tmp8 = fmul reassoc float %tmp7, 0x3FE372D780000000
-  %tmp9 = fsub reassoc nsz float -1.000000e+00, %tmp8
-  %tmp10 = fmul reassoc float %tmp9, %tmp6
-  %tmp11 = fadd reassoc float %tmp5, 5.000000e-01
-  %tmp12 = fadd reassoc float %tmp11, %tmp10
+  %tmp8 = fmul contract reassoc float %tmp7, 0x3FE372D780000000
+  %tmp9 = fsub contract reassoc nsz float -1.000000e+00, %tmp8
+  %tmp10 = fmul contract reassoc float %tmp9, %tmp6
+  %tmp11 = fadd contract reassoc float %tmp5, 5.000000e-01
+  %tmp12 = fadd contract reassoc float %tmp11, %tmp10
   ret float %tmp12
 }
 
 ; This would crash while trying getNegatedExpression().
 define dso_local double @getNegatedExpression_crash(double %x, double %y) {
 ; CHECK-FAST-LABEL: getNegatedExpression_crash:
 ; CHECK-FAST:       # %bb.0:
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI5_1@toc@ha

llvm/test/CodeGen/PowerPC/fma-mutate.ll

 ; CHECK-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-NEXT:    xsmuldp 0, 1, 4
 ; CHECK-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    xssqrtdp 1, 1
 ; CHECK-NEXT:    blr
-  %r = call reassoc afn ninf double @llvm.sqrt.f64(double %a)
+  %r = call contract reassoc afn ninf double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 
 define double @foo3_safe(double %a) nounwind {
 ; CHECK-LABEL: foo3_safe:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xssqrtdp 1, 1
 ; CHECK-NEXT:    blr
   %r = call double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 

llvm/test/CodeGen/PowerPC/fma-negate.ll

 ; VSX-NEXT:    xsnmsubadp 1, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_mul_sub_f64:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fnmsub 1, 2, 3, 1
 ; NO-VSX-NEXT:    blr
 entry:
-  %0 = fmul reassoc nsz double %b, %c
-  %1 = fsub reassoc nsz double %a, %0
+  %0 = fmul contract reassoc nsz double %b, %c
+  %1 = fsub contract reassoc nsz double %a, %0
   ret double %1
 }
 
 define double @test_fast_2mul_sub_f64(double %a, double %b, double %c,
 ; VSX-LABEL: test_fast_2mul_sub_f64:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xsmuldp 0, 3, 4
 ; VSX-NEXT:    xsmsubadp 0, 1, 2
 ; VSX-NEXT:    fmr 1, 0
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_2mul_sub_f64:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fmul 0, 3, 4
 ; NO-VSX-NEXT:    fmsub 1, 1, 2, 0
 ; NO-VSX-NEXT:    blr
                                       double %d) {
 entry:
-  %0 = fmul reassoc double %a, %b
-  %1 = fmul reassoc double %c, %d
-  %2 = fsub reassoc double %0, %1
+  %0 = fmul contract reassoc double %a, %b
+  %1 = fmul contract reassoc double %c, %d
+  %2 = fsub contract reassoc double %0, %1
   ret double %2
 }
 
 define double @test_fast_neg_fma_f64(double %a, double %b, double %c) {
 ; VSX-LABEL: test_fast_neg_fma_f64:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xsnmsubadp 3, 1, 2
 ; VSX-NEXT:    fmr 1, 3

 ; VSX-NEXT:    xsnmsubasp 1, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_mul_sub_f32:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fnmsubs 1, 2, 3, 1
 ; NO-VSX-NEXT:    blr
 entry:
-  %0 = fmul reassoc float %b, %c
-  %1 = fsub reassoc nsz float %a, %0
+  %0 = fmul contract reassoc float %b, %c
+  %1 = fsub contract reassoc nsz float %a, %0
   ret float %1
 }
 
 define float @test_fast_2mul_sub_f32(float %a, float %b, float %c, float %d) {
 ; VSX-LABEL: test_fast_2mul_sub_f32:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xsmulsp 0, 3, 4
 ; VSX-NEXT:    xsmsubasp 0, 1, 2
 ; VSX-NEXT:    fmr 1, 0
 ; VSX-NEXT:    blr
 ;
 ; NO-VSX-LABEL: test_fast_2mul_sub_f32:
 ; NO-VSX:       # %bb.0: # %entry
 ; NO-VSX-NEXT:    fmuls 0, 3, 4
 ; NO-VSX-NEXT:    fmsubs 1, 1, 2, 0
 ; NO-VSX-NEXT:    blr
 entry:
-  %0 = fmul reassoc float %a, %b
-  %1 = fmul reassoc float %c, %d
-  %2 = fsub reassoc nsz float %0, %1
+  %0 = fmul contract reassoc float %a, %b
+  %1 = fmul contract reassoc float %c, %d
+  %2 = fsub contract reassoc nsz float %0, %1
   ret float %2
 }
 
 define float @test_fast_neg_fma_f32(float %a, float %b, float %c) {
 ; VSX-LABEL: test_fast_neg_fma_f32:
 ; VSX:       # %bb.0: # %entry
 ; VSX-NEXT:    xsnmsubasp 3, 1, 2
 ; VSX-NEXT:    fmr 1, 3

llvm/test/CodeGen/PowerPC/fma-precision.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-linux-gnu | FileCheck %s
+; RUN: llc < %s -fp-contract=fast -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-linux-gnu | FileCheck %s
 
 ; Verify that the fold of a*b-c*d respect the uses of a*b
 define double @fsub1(double %a, double %b, double %c, double %d)  {
 ; CHECK-LABEL: fsub1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xsmuldp 0, 2, 1
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    xsnmsubadp 1, 4, 3

llvm/test/CodeGen/PowerPC/fmf-propagation.ll

 ; FMF-NEXT:    fmr 1, 3
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fadd_contract1:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xsmaddasp 3, 1, 2
 ; GLOBAL-NEXT:    fmr 1, 3
 ; GLOBAL-NEXT:    blr
-  %mul = fmul float %x, %y
+  %mul = fmul contract float %x, %y
   %add = fadd contract float %mul, %z
   ret float %add
 }
 
 ; This shouldn't change anything - the intermediate fmul result is now also flagged.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_contract2:'
 ; FMFDEBUG:         fma contract {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}

 ; GLOBAL-NEXT:    xsmaddasp 3, 1, 2
 ; GLOBAL-NEXT:    fmr 1, 3
 ; GLOBAL-NEXT:    blr
   %mul = fmul contract float %x, %y
   %add = fadd contract float %mul, %z
   ret float %add
 }
 
-; Reassociation implies that FMA contraction is allowed.
+; Reassociation does NOT imply that FMA contraction is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_reassoc1:'
-; FMFDEBUG:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
+; FMFDEBUG-NOT:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fadd_reassoc1:'
 
 define float @fmul_fadd_reassoc1(float %x, float %y, float %z) {
 ; FMF-LABEL: fmul_fadd_reassoc1:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    xsmaddasp 3, 1, 2
-; FMF-NEXT:    fmr 1, 3
+; FMF-NEXT:    xsmulsp 0, 1, 2
+; FMF-NEXT:    xsaddsp 1, 0, 3
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fadd_reassoc1:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xsmaddasp 3, 1, 2
 ; GLOBAL-NEXT:    fmr 1, 3
 ; GLOBAL-NEXT:    blr
   %mul = fmul float %x, %y
   %add = fadd reassoc float %mul, %z
   ret float %add
 }
 
 ; This shouldn't change anything - the intermediate fmul result is now also flagged.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_reassoc2:'
-; FMFDEBUG:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}
+; FMFDEBUG-NOT:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fadd_reassoc2:'
 
 define float @fmul_fadd_reassoc2(float %x, float %y, float %z) {
 ; FMF-LABEL: fmul_fadd_reassoc2:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    xsmaddasp 3, 1, 2
-; FMF-NEXT:    fmr 1, 3
+; FMF-NEXT:    xsmulsp 0, 1, 2
+; FMF-NEXT:    xsaddsp 1, 0, 3
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fadd_reassoc2:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xsmaddasp 3, 1, 2
 ; GLOBAL-NEXT:    fmr 1, 3
 ; GLOBAL-NEXT:    blr
   %mul = fmul reassoc float %x, %y
   %add = fadd reassoc float %mul, %z
   ret float %add
 }
 
 ; The fadd is now fully 'fast'. This implies that contraction is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_fast1:'
-; FMFDEBUG:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
+; FMFDEBUG-NOT:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fadd_fast1:'
 
 define float @fmul_fadd_fast1(float %x, float %y, float %z) {
 ; FMF-LABEL: fmul_fadd_fast1:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    xsmaddasp 3, 1, 2
-; FMF-NEXT:    fmr 1, 3
+; FMF-NEXT:    xsmulsp 0, 1, 2
+; FMF-NEXT:    xsaddsp 1, 0, 3
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fadd_fast1:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xsmaddasp 3, 1, 2
 ; GLOBAL-NEXT:    fmr 1, 3
 ; GLOBAL-NEXT:    blr
   %mul = fmul reassoc float %x, %y
   %add = fadd reassoc float %mul, %z
   ret float %add
 }
 
 ; This shouldn't change anything - the intermediate fmul result is now also flagged.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fadd_fast2:'
-; FMFDEBUG:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
+; FMFDEBUG-NOT:         fma reassoc {{t[0-9]+}}, {{t[0-9]+}}, {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fmul_fadd_fast2:'
 
 define float @fmul_fadd_fast2(float %x, float %y, float %z) {
 ; FMF-LABEL: fmul_fadd_fast2:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    xsmaddasp 3, 1, 2
-; FMF-NEXT:    fmr 1, 3
+; FMF-NEXT:    xsmulsp 0, 1, 2
+; FMF-NEXT:    xsaddsp 1, 0, 3
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: fmul_fadd_fast2:
 ; GLOBAL:       # %bb.0:
 ; GLOBAL-NEXT:    xsmaddasp 3, 1, 2
 ; GLOBAL-NEXT:    fmr 1, 3
 ; GLOBAL-NEXT:    blr
   %mul = fmul reassoc float %x, %y

 ; GLOBAL-NEXT:    blr
   %rt = call afn float @llvm.sqrt.f32(float %x)
   ret float %rt
 }
 
 ; The call is now fully 'fast'. This implies that approximation is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_ieee:'
-; FMFDEBUG:         fmul ninf afn reassoc {{t[0-9]+}}
+; FMFDEBUG:         fmul ninf contract afn reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_ieee:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_ieee:'
-; GLOBALDEBUG:         fmul ninf afn reassoc {{t[0-9]+}}
+; GLOBALDEBUG:         fmul ninf contract afn reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_ieee:'
 
 define float @sqrt_fast_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_fast_ieee:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xsabsdp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI14_2@toc@ha
 ; FMF-NEXT:    lfs 2, .LCPI14_2@toc@l(3)

 ; GLOBAL-NEXT:    lfs 3, .LCPI14_1@toc@l(4)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB14_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
-  %rt = call reassoc afn ninf float @llvm.sqrt.f32(float %x)
+  %rt = call contract reassoc afn ninf float @llvm.sqrt.f32(float %x)
   ret float %rt
 }
 
 ; The call is now fully 'fast'. This implies that approximation is allowed.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
-; FMFDEBUG:         fmul ninf afn reassoc {{t[0-9]+}}
+; FMFDEBUG:         fmul ninf contract afn reassoc {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
 
 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
-; GLOBALDEBUG:         fmul ninf afn reassoc {{t[0-9]+}}
+; GLOBALDEBUG:         fmul ninf contract afn reassoc {{t[0-9]+}}
 ; GLOBALDEBUG:       Type-legalized selection DAG: %bb.0 'sqrt_fast_preserve_sign:'
 
 define float @sqrt_fast_preserve_sign(float %x) #1 {
 ; FMF-LABEL: sqrt_fast_preserve_sign:
 ; FMF:       # %bb.0:
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    fcmpu 0, 1, 0
 ; FMF-NEXT:    beq 0, .LBB15_2

 ; GLOBAL-NEXT:    lfs 3, .LCPI15_1@toc@l(4)
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 1, 3
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB15_2:
 ; GLOBAL-NEXT:    fmr 1, 0
 ; GLOBAL-NEXT:    blr
-  %rt = call reassoc ninf afn float @llvm.sqrt.f32(float %x)
+  %rt = call contract reassoc ninf afn float @llvm.sqrt.f32(float %x)
   ret float %rt
 }
 
 ; fcmp can have fast-math-flags.
 
 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fcmp_nnan:'
 ; FMFDEBUG:         select_cc nnan {{t[0-9]+}}
 ; FMFDEBUG:       Type-legalized selection DAG: %bb.0 'fcmp_nnan:'

llvm/test/CodeGen/PowerPC/machine-combiner.ll

 
 define double @reassociate_mamaa_double(double %0, double %1, double %2, double %3, double %4, double %5) {
 ; CHECK-LABEL: reassociate_mamaa_double:
 ; CHECK:       # %bb.0:
 ; CHECK-PWR-DAG:   xsmaddadp 1, 6, 5
 ; CHECK-PWR-DAG:   xsmaddadp 2, 4, 3
 ; CHECK-PWR:       xsadddp 1, 2, 1
 ; CHECK-NEXT:  blr
-  %7 = fmul reassoc nsz double %3, %2
-  %8 = fmul reassoc nsz double %5, %4
-  %9 = fadd reassoc nsz double %1, %0
-  %10 = fadd reassoc nsz double %9, %7
-  %11 = fadd reassoc nsz double %10, %8
+  %7 = fmul contract reassoc nsz double %3, %2
+  %8 = fmul contract reassoc nsz double %5, %4
+  %9 = fadd contract reassoc nsz double %1, %0
+  %10 = fadd contract reassoc nsz double %9, %7
+  %11 = fadd contract reassoc nsz double %10, %8
   ret double %11
 }
 
 define float @reassociate_mamaa_float(float %0, float %1, float %2, float %3, float %4, float %5) {
 ; CHECK-LABEL: reassociate_mamaa_float:
 ; CHECK:       # %bb.0:
 ; CHECK-DAG:   fmadds [[REG0:[0-9]+]], 4, 3, 2
 ; CHECK-DAG:   fmadds [[REG1:[0-9]+]], 6, 5, 1
 ; CHECK:       fadds 1, [[REG0]], [[REG1]]
 ; CHECK-NEXT:  blr
-  %7 = fmul reassoc nsz float %3, %2
-  %8 = fmul reassoc nsz float %5, %4
-  %9 = fadd reassoc nsz float %1, %0
-  %10 = fadd reassoc nsz float %9, %7
-  %11 = fadd reassoc nsz float %10, %8
+  %7 = fmul contract reassoc nsz float %3, %2
+  %8 = fmul contract reassoc nsz float %5, %4
+  %9 = fadd contract reassoc nsz float %1, %0
+  %10 = fadd contract reassoc nsz float %9, %7
+  %11 = fadd contract reassoc nsz float %10, %8
   ret float %11
 }
 
 define <4 x float> @reassociate_mamaa_vec(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3, <4 x float> %4, <4 x float> %5) {
 ; CHECK-LABEL: reassociate_mamaa_vec:
 ; CHECK:       # %bb.0:
 ; CHECK-PWR-DAG:   xvmaddasp [[REG0:[0-9]+]], 39, 38
 ; CHECK-PWR-DAG:   xvmaddasp [[REG1:[0-9]+]], 37, 36
 ; CHECK-PWR:       xvaddsp 34, [[REG1]], [[REG0]]
 ; CHECK-NEXT:  blr
-  %7 = fmul reassoc nsz <4 x float> %3, %2
-  %8 = fmul reassoc nsz <4 x float> %5, %4
-  %9 = fadd reassoc nsz <4 x float> %1, %0
-  %10 = fadd reassoc nsz <4 x float> %9, %7
-  %11 = fadd reassoc nsz <4 x float> %10, %8
+  %7 = fmul contract reassoc nsz <4 x float> %3, %2
+  %8 = fmul contract reassoc nsz <4 x float> %5, %4
+  %9 = fadd contract reassoc nsz <4 x float> %1, %0
+  %10 = fadd contract reassoc nsz <4 x float> %9, %7
+  %11 = fadd contract reassoc nsz <4 x float> %10, %8
   ret <4 x float> %11
 }
 
 define double @reassociate_mamama_double(double %0, double %1, double %2, double %3, double %4, double %5, double %6, double %7, double %8) {
 ; CHECK-LABEL: reassociate_mamama_double:
 ; CHECK:       # %bb.0:
 ; CHECK-PWR:       xsmaddadp 7, 2, 1
 ; CHECK-PWR-DAG:   xsmuldp [[REG0:[0-9]+]], 4, 3
 ; CHECK-PWR-DAG:   xsmaddadp 7, 6, 5
 ; CHECK-PWR-DAG:   xsmaddadp [[REG0]], 9, 8
 ; CHECK-PWR:       xsadddp 1, 7, [[REG0]]
 ; CHECK-NEXT:  blr
-  %10 = fmul reassoc nsz double %1, %0
-  %11 = fmul reassoc nsz double %3, %2
-  %12 = fmul reassoc nsz double %5, %4
-  %13 = fmul reassoc nsz double %8, %7
-  %14 = fadd reassoc nsz double %11, %10
-  %15 = fadd reassoc nsz double %14, %6
-  %16 = fadd reassoc nsz double %15, %12
-  %17 = fadd reassoc nsz double %16, %13
+  %10 = fmul contract reassoc nsz double %1, %0
+  %11 = fmul contract reassoc nsz double %3, %2
+  %12 = fmul contract reassoc nsz double %5, %4
+  %13 = fmul contract reassoc nsz double %8, %7
+  %14 = fadd contract reassoc nsz double %11, %10
+  %15 = fadd contract reassoc nsz double %14, %6
+  %16 = fadd contract reassoc nsz double %15, %12
+  %17 = fadd contract reassoc nsz double %16, %13
   ret double %17
 }
 
 define dso_local float @reassociate_mamama_8(float %0, float %1, float %2, float %3, float %4, float %5, float %6, float %7, float %8,
                                              float %9, float %10, float %11, float %12, float %13, float %14, float %15, float %16) {
 ; CHECK-LABEL: reassociate_mamama_8:
 ; CHECK:       # %bb.0:
 ; CHECK-DAG:    fmadds [[REG0:[0-9]+]], 3, 2, 1
 ; CHECK-DAG:    fmuls  [[REG1:[0-9]+]], 5, 4
 ; CHECK-DAG:    fmadds [[REG2:[0-9]+]], 7, 6, [[REG0]]
 ; CHECK-DAG:    fmadds [[REG3:[0-9]+]], 9, 8, [[REG1]]
 ;
 ; CHECK-DAG:    fmadds [[REG4:[0-9]+]], 13, 12, [[REG3]]
 ; CHECK-DAG:    fmadds [[REG5:[0-9]+]], 11, 10, [[REG2]]
 ;
 ; CHECK-DAG:    fmadds [[REG6:[0-9]+]], 3, 2, [[REG4]]
 ; CHECK-DAG:    fmadds [[REG7:[0-9]+]], 5, 4, [[REG5]]
 ; CHECK:        fadds 1, [[REG7]], [[REG6]]
 ; CHECK-NEXT:   blr
-  %18 = fmul reassoc nsz float %2, %1
-  %19 = fadd reassoc nsz float %18, %0
-  %20 = fmul reassoc nsz float %4, %3
-  %21 = fadd reassoc nsz float %19, %20
-  %22 = fmul reassoc nsz float %6, %5
-  %23 = fadd reassoc nsz float %21, %22
-  %24 = fmul reassoc nsz float %8, %7
-  %25 = fadd reassoc nsz float %23, %24
-  %26 = fmul reassoc nsz float %10, %9
-  %27 = fadd reassoc nsz float %25, %26
-  %28 = fmul reassoc nsz float %12, %11
-  %29 = fadd reassoc nsz float %27, %28
-  %30 = fmul reassoc nsz float %14, %13
-  %31 = fadd reassoc nsz float %29, %30
-  %32 = fmul reassoc nsz float %16, %15
-  %33 = fadd reassoc nsz float %31, %32
+  %18 = fmul contract reassoc nsz float %2, %1
+  %19 = fadd contract reassoc nsz float %18, %0
+  %20 = fmul contract reassoc nsz float %4, %3
+  %21 = fadd contract reassoc nsz float %19, %20
+  %22 = fmul contract reassoc nsz float %6, %5
+  %23 = fadd contract reassoc nsz float %21, %22
+  %24 = fmul contract reassoc nsz float %8, %7
+  %25 = fadd contract reassoc nsz float %23, %24
+  %26 = fmul contract reassoc nsz float %10, %9
+  %27 = fadd contract reassoc nsz float %25, %26
+  %28 = fmul contract reassoc nsz float %12, %11
+  %29 = fadd contract reassoc nsz float %27, %28
+  %30 = fmul contract reassoc nsz float %14, %13
+  %31 = fadd contract reassoc nsz float %29, %30
+  %32 = fmul contract reassoc nsz float %16, %15
+  %33 = fadd contract reassoc nsz float %31, %32
   ret float %33
 }
 

llvm/test/CodeGen/PowerPC/recipest.ll

 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P9-NEXT:    xsmuldp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    blr
-  %x = call arcp reassoc double @llvm.sqrt.f64(double %b)
-  %r = fdiv arcp reassoc double %a, %x
+  %x = call arcp contract reassoc double @llvm.sqrt.f64(double %b)
+  %r = fdiv arcp contract reassoc double %a, %x
   ret double %r
 }
 
 define double @foo_safe(double %a, double %b) nounwind {
 ; CHECK-P7-LABEL: foo_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fsqrt 0, 2
 ; CHECK-P7-NEXT:    fdiv 1, 1, 0

 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
 ; CHECK-P9-NEXT:    xsmulsp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddasp 3, 2, 0
 ; CHECK-P9-NEXT:    lfs 2, .LCPI3_1@toc@l(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    blr
-  %x = call reassoc arcp float @llvm.sqrt.f32(float %b)
+  %x = call contract reassoc arcp float @llvm.sqrt.f32(float %b)
   %y = fpext float %x to double
-  %r = fdiv reassoc arcp double %a, %y
+  %r = fdiv contract reassoc arcp double %a, %y
   ret double %r
 }
 
 define double @foof_safe(double %a, float %b) nounwind {
 ; CHECK-P7-LABEL: foof_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fsqrts 0, 2
 ; CHECK-P7-NEXT:    fdiv 1, 1, 0

 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 5
 ; CHECK-P9-NEXT:    xsmuldp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 4, 2, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmuldp 0, 0, 4
 ; CHECK-P9-NEXT:    xsrsp 0, 0
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P9-NEXT:    blr
-  %x = call reassoc arcp double @llvm.sqrt.f64(double %b)
+  %x = call contract reassoc arcp double @llvm.sqrt.f64(double %b)
   %y = fptrunc double %x to float
-  %r = fdiv reassoc arcp float %a, %y
+  %r = fdiv contract reassoc arcp float %a, %y
   ret float %r
 }
 
 define float @food_safe(float %a, double %b) nounwind {
 ; CHECK-P7-LABEL: food_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fsqrt 0, 2
 ; CHECK-P7-NEXT:    frsp 0, 0

 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI7_1@toc@ha
 ; CHECK-P9-NEXT:    xsmulsp 2, 2, 0
 ; CHECK-P9-NEXT:    xsmaddasp 3, 2, 0
 ; CHECK-P9-NEXT:    lfs 2, .LCPI7_1@toc@l(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 3
 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P9-NEXT:    blr
-  %x = call reassoc arcp float @llvm.sqrt.f32(float %b)
-  %r = fdiv reassoc arcp float %a, %x
+  %x = call contract reassoc arcp float @llvm.sqrt.f32(float %b)
+  %r = fdiv contract reassoc arcp float %a, %x
   ret float %r
 }
 
 define float @goo_safe(float %a, float %b) nounwind {
 ; CHECK-P7-LABEL: goo_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fsqrts 0, 2
 ; CHECK-P7-NEXT:    fdivs 1, 1, 0

 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 1
 ; CHECK-P9-NEXT:    xsresp 1, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 4
 ; CHECK-P9-NEXT:    xsmulsp 4, 0, 1
 ; CHECK-P9-NEXT:    xsnmsubasp 0, 2, 4
 ; CHECK-P9-NEXT:    xsmaddasp 4, 1, 0
 ; CHECK-P9-NEXT:    xsmulsp 1, 3, 4
 ; CHECK-P9-NEXT:    blr
-  %x = call reassoc arcp nsz float @llvm.sqrt.f32(float %a)
-  %y = fmul reassoc nsz float %x, %b
-  %z = fdiv reassoc arcp nsz ninf float %c, %y
+  %x = call contract reassoc arcp nsz float @llvm.sqrt.f32(float %a)
+  %y = fmul contract reassoc nsz float %x, %b
+  %z = fdiv contract reassoc arcp nsz ninf float %c, %y
   ret float %z
 }
 
 define float @rsqrt_fmul_safe(float %a, float %b, float %c) {
 ; CHECK-P7-LABEL: rsqrt_fmul_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fsqrts 0, 1
 ; CHECK-P7-NEXT:    fmuls 0, 0, 2

 ; CHECK-P9-NEXT:    addi 3, 3, .LCPI12_1@toc@l
 ; CHECK-P9-NEXT:    xvmulsp 1, 35, 0
 ; CHECK-P9-NEXT:    xvmaddasp 2, 1, 0
 ; CHECK-P9-NEXT:    lxvx 1, 0, 3
 ; CHECK-P9-NEXT:    xvmulsp 0, 0, 1
 ; CHECK-P9-NEXT:    xvmulsp 0, 0, 2
 ; CHECK-P9-NEXT:    xvmulsp 34, 34, 0
 ; CHECK-P9-NEXT:    blr
-  %x = call reassoc arcp <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
-  %r = fdiv reassoc arcp <4 x float> %a, %x
+  %x = call contract reassoc arcp <4 x float> @llvm.sqrt.v4f32(<4 x float> %b)
+  %r = fdiv contract reassoc arcp <4 x float> %a, %x
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-P7-LABEL: hoo_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    addi 3, 1, -32
 ; CHECK-P7-NEXT:    stvx 3, 0, 3

 ; CHECK-P9-NEXT:    lfs 0, .LCPI14_0@toc@l(3)
 ; CHECK-P9-NEXT:    xsmaddadp 0, 2, 3
 ; CHECK-P9-NEXT:    xsnmsubadp 3, 3, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 3
 ; CHECK-P9-NEXT:    xsnmsubadp 1, 2, 0
 ; CHECK-P9-NEXT:    xsmaddadp 0, 3, 1
 ; CHECK-P9-NEXT:    fmr 1, 0
 ; CHECK-P9-NEXT:    blr
-  %r = fdiv reassoc arcp nsz ninf double %a, %b
+  %r = fdiv contract reassoc arcp nsz ninf double %a, %b
   ret double %r
 }
 
 define double @foo2_safe(double %a, double %b) nounwind {
 ; CHECK-P7-LABEL: foo2_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fdiv 1, 1, 2
 ; CHECK-P7-NEXT:    blr

 ; CHECK-P9-LABEL: goo2_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xsresp 3, 2
 ; CHECK-P9-NEXT:    xsmulsp 0, 1, 3
 ; CHECK-P9-NEXT:    xsnmsubasp 1, 2, 0
 ; CHECK-P9-NEXT:    xsmaddasp 0, 3, 1
 ; CHECK-P9-NEXT:    fmr 1, 0
 ; CHECK-P9-NEXT:    blr
-  %r = fdiv reassoc arcp nsz ninf float %a, %b
+  %r = fdiv contract reassoc arcp nsz ninf float %a, %b
   ret float %r
 }
 
 define float @goo2_safe(float %a, float %b) nounwind {
 ; CHECK-P7-LABEL: goo2_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fdivs 1, 1, 2
 ; CHECK-P7-NEXT:    blr

 ; CHECK-P9-LABEL: hoo2_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xvresp 1, 35
 ; CHECK-P9-NEXT:    xvmulsp 0, 34, 1
 ; CHECK-P9-NEXT:    xvnmsubasp 34, 35, 0
 ; CHECK-P9-NEXT:    xvmaddasp 0, 1, 34
 ; CHECK-P9-NEXT:    xxlor 34, 0, 0
 ; CHECK-P9-NEXT:    blr
-  %r = fdiv reassoc arcp nsz ninf <4 x float> %a, %b
+  %r = fdiv contract reassoc arcp nsz ninf <4 x float> %a, %b
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo2_safe(<4 x float> %a, <4 x float> %b) nounwind {
 ; CHECK-P7-LABEL: hoo2_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    addi 3, 1, -32
 ; CHECK-P7-NEXT:    addi 4, 1, -48

 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 2
 ; CHECK-P9-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB20_2:
 ; CHECK-P9-NEXT:    xssqrtdp 1, 1
 ; CHECK-P9-NEXT:    blr
-  %r = call reassoc ninf afn double @llvm.sqrt.f64(double %a)
+  %r = call contract reassoc ninf afn double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 
 define double @foo3_fmf_crbits_off(double %a) #2 {
 ; CHECK-P7-LABEL: foo3_fmf_crbits_off:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fabs 0, 1
 ; CHECK-P7-NEXT:    addis 3, 2, .LCPI21_2@toc@ha

 ; CHECK-P9-NEXT:    xsmuldp 1, 1, 0
 ; CHECK-P9-NEXT:    xsmaddadp 3, 1, 0
 ; CHECK-P9-NEXT:    xsmuldp 0, 1, 2
 ; CHECK-P9-NEXT:    xsmuldp 1, 0, 3
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB21_2:
 ; CHECK-P9-NEXT:    xssqrtdp 1, 1
 ; CHECK-P9-NEXT:    blr
-  %r = call reassoc ninf afn double @llvm.sqrt.f64(double %a)
+  %r = call contract reassoc ninf afn double @llvm.sqrt.f64(double %a)
   ret double %r
 }
 
 define double @foo3_safe(double %a) nounwind {
 ; CHECK-P7-LABEL: foo3_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fsqrt 1, 1
 ; CHECK-P7-NEXT:    blr

 ; CHECK-P9-NEXT:    xsmulsp 1, 1, 0
 ; CHECK-P9-NEXT:    xsmaddasp 2, 1, 0
 ; CHECK-P9-NEXT:    lfs 0, .LCPI23_1@toc@l(3)
 ; CHECK-P9-NEXT:    xsmulsp 0, 1, 0
 ; CHECK-P9-NEXT:    xsmulsp 0, 0, 2
 ; CHECK-P9-NEXT:  .LBB23_2:
 ; CHECK-P9-NEXT:    fmr 1, 0
 ; CHECK-P9-NEXT:    blr
-  %r = call reassoc ninf afn float @llvm.sqrt.f32(float %a)
+  %r = call contract reassoc ninf afn float @llvm.sqrt.f32(float %a)
   ret float %r
 }
 
 define float @goo3_safe(float %a) nounwind {
 ; CHECK-P7-LABEL: goo3_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fsqrts 1, 1
 ; CHECK-P7-NEXT:    blr

 ; CHECK-P9-NEXT:    xvmaddasp 2, 1, 0
 ; CHECK-P9-NEXT:    lxvx 0, 0, 3
 ; CHECK-P9-NEXT:    xvmulsp 0, 1, 0
 ; CHECK-P9-NEXT:    xvmulsp 34, 0, 2
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB25_2:
 ; CHECK-P9-NEXT:    xvsqrtsp 34, 34
 ; CHECK-P9-NEXT:    blr
-  %r = call reassoc ninf afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
+  %r = call contract reassoc ninf afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo3_safe(<4 x float> %a) nounwind {
 ; CHECK-P7-LABEL: hoo3_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    addi 3, 1, -32
 ; CHECK-P7-NEXT:    stvx 2, 0, 3

 ; CHECK-P9-NEXT:    xvmuldp 3, 34, 0
 ; CHECK-P9-NEXT:    xvmaddadp 2, 3, 0
 ; CHECK-P9-NEXT:    xvmuldp 0, 3, 1
 ; CHECK-P9-NEXT:    xvmuldp 34, 0, 2
 ; CHECK-P9-NEXT:    blr
 ; CHECK-P9-NEXT:  .LBB27_2:
 ; CHECK-P9-NEXT:    xvsqrtdp 34, 34
 ; CHECK-P9-NEXT:    blr
-  %r = call reassoc ninf afn <2 x double> @llvm.sqrt.v2f64(<2 x double> %a)
+  %r = call contract reassoc ninf afn <2 x double> @llvm.sqrt.v2f64(<2 x double> %a)
   ret <2 x double> %r
 }
 
 define <2 x double> @hoo4_safe(<2 x double> %a) #1 {
 ; CHECK-P7-LABEL: hoo4_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    fsqrt 1, 1
 ; CHECK-P7-NEXT:    fsqrt 2, 2

 ; CHECK-P8-NEXT:    ld 0, 16(1)
 ; CHECK-P8-NEXT:    mtlr 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo5_fmf:
 ; CHECK-P9:       # %bb.0:
 ; CHECK-P9-NEXT:    xssqrtqp 2, 2
 ; CHECK-P9-NEXT:    blr
-  %r = call reassoc ninf afn fp128 @llvm.sqrt.f128(fp128 %a)
+  %r = call contract reassoc ninf afn fp128 @llvm.sqrt.f128(fp128 %a)
   ret fp128 %r
 }
 
 define fp128 @hoo5_safe(fp128 %a) #1 {
 ; CHECK-P7-LABEL: hoo5_safe:
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    mflr 0
 ; CHECK-P7-NEXT:    std 0, 16(1)

llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll

 ; CHECK-FMA-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-FMA-NEXT:    xsmulsp f1, f2, f1
 ; CHECK-FMA-NEXT:    lfs f0, .LCPI0_0@toc@l(r3)
 ; CHECK-FMA-NEXT:    addis r3, r2, .LCPI0_1@toc@ha
 ; CHECK-FMA-NEXT:    lfs f2, .LCPI0_1@toc@l(r3)
 ; CHECK-FMA-NEXT:    xsmaddasp f1, f4, f2
 ; CHECK-FMA-NEXT:    xsmaddasp f1, f3, f0
 ; CHECK-FMA-NEXT:    blr
-  %5 = fmul reassoc nsz float %1, %0
-  %6 = fsub reassoc nsz float %2, %3
-  %7 = fmul reassoc nsz float %6, 0x3DB2533FE0000000
-  %8 = fadd reassoc nsz float %7, %5
+  %5 = fmul contract reassoc nsz float %1, %0
+  %6 = fsub contract reassoc nsz float %2, %3
+  %7 = fmul contract reassoc nsz float %6, 0x3DB2533FE0000000
+  %8 = fadd contract reassoc nsz float %7, %5
   ret float %8
 }
 
 define double @foo_double(double %0, double %1, double %2, double %3) {
 ; CHECK-LABEL: foo_double:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xsmuldp f1, f2, f1
 ; CHECK-NEXT:    xssubdp f0, f3, f4

 ; CHECK-FMA-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-FMA-NEXT:    xsmuldp f1, f2, f1
 ; CHECK-FMA-NEXT:    lfd f0, .LCPI1_0@toc@l(r3)
 ; CHECK-FMA-NEXT:    addis r3, r2, .LCPI1_1@toc@ha
 ; CHECK-FMA-NEXT:    lfd f2, .LCPI1_1@toc@l(r3)
 ; CHECK-FMA-NEXT:    xsmaddadp f1, f4, f2
 ; CHECK-FMA-NEXT:    xsmaddadp f1, f3, f0
 ; CHECK-FMA-NEXT:    blr
-  %5 = fmul reassoc nsz double %1, %0
-  %6 = fsub reassoc nsz double %2, %3
-  %7 = fmul reassoc nsz double %6, 0x3DB2533FE68CADDE
-  %8 = fadd reassoc nsz double %7, %5
+  %5 = fmul contract reassoc nsz double %1, %0
+  %6 = fsub contract reassoc nsz double %2, %3
+  %7 = fmul contract reassoc nsz double %6, 0x3DB2533FE68CADDE
+  %8 = fadd contract reassoc nsz double %7, %5
   ret double %8
 }
 
 define float @foo_float_reuse_const(float %0, float %1, float %2, float %3) {
 ; CHECK-LABEL: foo_float_reuse_const:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-NEXT:    xsmulsp f1, f2, f1

 ; CHECK-FMA-NEXT:    lfs f5, .LCPI2_1@toc@l(r3)
 ; CHECK-FMA-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-FMA-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-FMA-NEXT:    xsmaddasp f1, f4, f5
 ; CHECK-FMA-NEXT:    xsmaddasp f1, f3, f0
 ; CHECK-FMA-NEXT:    xsmulsp f0, f2, f5
 ; CHECK-FMA-NEXT:    stfs f0, 0(r3)
 ; CHECK-FMA-NEXT:    blr
-  %5 = fmul reassoc nsz float %1, %0
-  %6 = fsub reassoc nsz float %2, %3
-  %7 = fmul reassoc nsz float %6, 0x3DB2533FE0000000
-  %8 = fadd reassoc nsz float %7, %5
-  %9 = fmul reassoc nsz float %1, 0xBDB2533FE0000000
+  %5 = fmul contract reassoc nsz float %1, %0
+  %6 = fsub contract reassoc nsz float %2, %3
+  %7 = fmul contract reassoc nsz float %6, 0x3DB2533FE0000000
+  %8 = fadd contract reassoc nsz float %7, %5
+  %9 = fmul contract reassoc nsz float %1, 0xBDB2533FE0000000
   store float %9, float* @global_val, align 4
   ret float %8
 }

llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll

 ; CHECK-NEXT:    xvresp 1, 0
 ; CHECK-NEXT:    xvnmsubasp 35, 0, 1
 ; CHECK-NEXT:    xvmulsp 0, 34, 36
 ; CHECK-NEXT:    xvmaddasp 1, 1, 35
 ; CHECK-NEXT:    xvmulsp 34, 0, 1
 ; CHECK-NEXT:    blr
   %ins = insertelement <4 x float> undef, float %a, i32 0
   %splat = shufflevector <4 x float> %ins, <4 x float> undef, <4 x i32> zeroinitializer
-  %t1 = fmul reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
-  %mul = fdiv reassoc arcp nsz ninf <4 x float> %t1, %splat
+  %t1 = fmul contract reassoc <4 x float> %b, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 0x3FF028F5C0000000>
+  %mul = fdiv contract reassoc arcp nsz ninf <4 x float> %t1, %splat
   ret <4 x float> %mul
 }
 

llvm/test/CodeGen/Thumb2/mve-vldshuffle.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs -fp-contract=fast %s -o - | FileCheck %s
+; FIXME: The fmul <8 x half> %5, %6 generated in %vector.body does NOT have contract bits on by default.
 
 define void @arm_cmplx_mag_squared_f16(half* nocapture readonly %pSrc, half* nocapture %pDst, i32 %numSamples) {
 ; CHECK-LABEL: arm_cmplx_mag_squared_f16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r7, lr}
 ; CHECK-NEXT:    push {r4, r5, r7, lr}
 ; CHECK-NEXT:    cmp r2, #0
 ; CHECK-NEXT:    beq .LBB0_8

llvm/test/CodeGen/X86/machine-combiner.ll

 ; AVX1-NEXT:    vaddps %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v4f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
 ; AVX512-NEXT:    vaddps %xmm0, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
-  %t0 = fmul reassoc nsz <4 x float> %x0, %x1
-  %t1 = fadd reassoc nsz <4 x float> %x2, %t0
+  %t0 = fmul contract reassoc nsz <4 x float> %x0, %x1
+  %t1 = fadd contract reassoc nsz <4 x float> %x2, %t0
   %t2 = fadd reassoc nsz <4 x float> %x3, %t1
   ret <4 x float> %t2
 }
 
 ; Verify that SSE and AVX 128-bit vector double-precision adds are reassociated.
 
 define <2 x double> @reassociate_adds_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {
 ; SSE-LABEL: reassociate_adds_v2f64:

 ; AVX1-NEXT:    vaddpd %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v2f64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
 ; AVX512-NEXT:    vaddpd %xmm0, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
-  %t0 = fmul reassoc nsz <2 x double> %x0, %x1
-  %t1 = fadd reassoc nsz <2 x double> %x2, %t0
+  %t0 = fmul contract reassoc nsz <2 x double> %x0, %x1
+  %t1 = fadd contract reassoc nsz <2 x double> %x2, %t0
   %t2 = fadd reassoc nsz <2 x double> %x3, %t1
   ret <2 x double> %t2
 }
 
 ; Verify that SSE and AVX 128-bit vector single-precision multiplies are reassociated.
 
 define <4 x float> @reassociate_muls_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; SSE-LABEL: reassociate_muls_v4f32:

 ; AVX1-NEXT:    vaddps %ymm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v8f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
 ; AVX512-NEXT:    vaddps %ymm0, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
-  %t0 = fmul reassoc nsz <8 x float> %x0, %x1
-  %t1 = fadd reassoc nsz <8 x float> %x2, %t0
+  %t0 = fmul contract reassoc nsz <8 x float> %x0, %x1
+  %t1 = fadd contract reassoc nsz <8 x float> %x2, %t0
   %t2 = fadd reassoc nsz <8 x float> %x3, %t1
   ret <8 x float> %t2
 }
 
 ; Verify that AVX 256-bit vector double-precision adds are reassociated.
 
 define <4 x double> @reassociate_adds_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {
 ; SSE-LABEL: reassociate_adds_v4f64:

 ; AVX1-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v4f64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
 ; AVX512-NEXT:    vaddpd %ymm0, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
-  %t0 = fmul reassoc nsz <4 x double> %x0, %x1
-  %t1 = fadd reassoc nsz <4 x double> %x2, %t0
+  %t0 = fmul contract reassoc nsz <4 x double> %x0, %x1
+  %t1 = fadd contract reassoc nsz <4 x double> %x2, %t0
   %t2 = fadd reassoc nsz <4 x double> %x3, %t1
   ret <4 x double> %t2
 }
 
 ; Verify that AVX 256-bit vector single-precision multiplies are reassociated.
 
 define <8 x float> @reassociate_muls_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {
 ; SSE-LABEL: reassociate_muls_v8f32:

 ; AVX1-NEXT:    vaddps %ymm2, %ymm1, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v16f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
 ; AVX512-NEXT:    vaddps %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
-  %t0 = fmul reassoc nsz <16 x float> %x0, %x1
-  %t1 = fadd reassoc nsz <16 x float> %x2, %t0
+  %t0 = fmul contract reassoc nsz <16 x float> %x0, %x1
+  %t1 = fadd contract reassoc nsz <16 x float> %x2, %t0
   %t2 = fadd reassoc nsz <16 x float> %x3, %t1
   ret <16 x float> %t2
 }
 
 ; Verify that AVX512 512-bit vector double-precision adds are reassociated.
 
 define <8 x double> @reassociate_adds_v8f64(<8 x double> %x0, <8 x double> %x1, <8 x double> %x2, <8 x double> %x3) {
 ; SSE-LABEL: reassociate_adds_v8f64:

 ; AVX1-NEXT:    vaddpd %ymm2, %ymm1, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v8f64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
 ; AVX512-NEXT:    vaddpd %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
-  %t0 = fmul reassoc nsz <8 x double> %x0, %x1
-  %t1 = fadd reassoc nsz <8 x double> %x2, %t0
+  %t0 = fmul contract reassoc nsz <8 x double> %x0, %x1
+  %t1 = fadd contract reassoc nsz <8 x double> %x2, %t0
   %t2 = fadd reassoc nsz <8 x double> %x3, %t1
   ret <8 x double> %t2
 }
 
 ; Verify that AVX512 512-bit vector single-precision multiplies are reassociated.
 
 define <16 x float> @reassociate_muls_v16f32(<16 x float> %x0, <16 x float> %x1, <16 x float> %x2, <16 x float> %x3) {
 ; SSE-LABEL: reassociate_muls_v16f32:

llvm/test/CodeGen/X86/sqrt-fastmath.ll

 ; AVX512-NEXT:    vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3
 ; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
 ; AVX512-NEXT:    vmulps %xmm1, %xmm2, %xmm1
 ; AVX512-NEXT:    vmulps %xmm3, %xmm1, %xmm1
 ; AVX512-NEXT:    vmulps %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    retq
   %s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %z)
   %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
-  %m = fmul reassoc <4 x float> %a, %s
-  %d = fdiv reassoc arcp <4 x float> %x, %m
+  %m = fmul contract reassoc <4 x float> %a, %s
+  %d = fdiv contract reassoc arcp <4 x float> %x, %m
   ret <4 x float> %d
 }
 
 ; This has 'arcp' but does not have 'reassoc' FMF.
 ; We allow converting the sqrt to an estimate, but
 ; do not pull the divisor into the estimate.
 ; x / (fabs(y) * sqrt(z)) --> x * rsqrt(z) / fabs(y)
 

 ; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
 ; AVX512-NEXT:    vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3
 ; AVX512-NEXT:    vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
 ; AVX512-NEXT:    vmulps %xmm1, %xmm2, %xmm1
 ; AVX512-NEXT:    vmulps %xmm3, %xmm1, %xmm1
 ; AVX512-NEXT:    vmulps %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    retq
   %s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %y)
-  %m = fmul reassoc <4 x float> %y, %s
-  %d = fdiv reassoc arcp <4 x float> %x, %m
+  %m = fmul contract reassoc <4 x float> %y, %s
+  %d = fdiv contract reassoc arcp <4 x float> %x, %m
   ret <4 x float> %d
 }
 
 define double @sqrt_fdiv_common_operand(double %x) nounwind {
 ; SSE-LABEL: sqrt_fdiv_common_operand:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    sqrtsd %xmm0, %xmm0
 ; SSE-NEXT:    retq