[DAGCombiner] Tighten reasscociation of visitFMA

[qiucf]

Summary

From LangRef:

contract: Allow floating-point contraction (e.g. fusing a multiply followed by an addition into a fused multiply-and-add). This does not enable reassociating to form arbitrary contractions. For example, `(a*b) + (c*d) + e can not be transformed into (a*b) + ((c*d) + e)` to create two fma operations.

reassoc: Allow reassociation transformations for floating-point instructions. This may dramatically change results in floating-point.

So contract should only help in fusing several operations into one (FMA), not rearrange nodes like (fma (fmul x, c1), c2, y) into (fma x, c1*c2, y).

[spatel]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13257

Can you add a test for this transform too?

[qiucf]

Add another test about preventing combined into (fmul x, c1+c2). (test was not pre-committed, diff is for review)

[spatel]

LGTM

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13214

This comment line seems to be misplaced now - it can be moved above the FlagInserter declaration or deleted.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitFMUL(SDNode *N) {
   }
 
   return SDValue();
 }
 
 SDValue DAGCombiner::visitFMA(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   SDValue N2 = N->getOperand(2);
   ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
   ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
   const TargetOptions &Options = DAG.getTarget().Options;
+  // FMA nodes have flags that propagate to the created nodes.
   SelectionDAG::FlagInserter FlagsInserter(DAG, N);
 
-  // FMA nodes have flags that propagate to the created nodes.
-  bool UnsafeFPMath = Options.UnsafeFPMath || isContractable(N);
+  bool UnsafeFPMath =
+      Options.UnsafeFPMath || N->getFlags().hasAllowReassociation();
 
   // Constant fold FMA.
   if (isa<ConstantFPSDNode>(N0) &&
       isa<ConstantFPSDNode>(N1) &&
       isa<ConstantFPSDNode>(N2)) {
     return DAG.getNode(ISD::FMA, DL, VT, N0, N1, N2);
   }
 
if (N0CFP && N0CFP->isZero())
       return N2;
     if (N1CFP && N1CFP->isZero())
       return N2;
   }
 
   if (N0CFP && N0CFP->isExactlyValue(1.0))
     return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
   if (N1CFP && N1CFP->isExactlyValue(1.0))
     return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
 
   // Canonicalize (fma c, x, y) -> (fma x, c, y)
   if (isConstantFPBuildVectorOrConstantFP(N0) &&
      !isConstantFPBuildVectorOrConstantFP(N1))
     return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
 
   if (UnsafeFPMath) {
     // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)

llvm/test/CodeGen/PowerPC/fma-combine.ll

 ; CHECK-NEXT:    xxswapd 0, 0
 ; CHECK-NEXT:    xvmaddadp 34, 34, 0
 ; CHECK-NEXT:    blr
 entry:
   %0 = call reassoc nnan <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> <double -1.0, double -1.0>, <2 x double> %a)
   ret <2 x double> %0
 }
 
+define double @fma_combine_const(double %a, double %b) {
+; CHECK-FAST-LABEL: fma_combine_const:
+; CHECK-FAST:       # %bb.0: # %entry
+; CHECK-FAST-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
+; CHECK-FAST-NEXT:    lfd 0, .LCPI9_0@toc@l(3)
+; CHECK-FAST-NEXT:    xsmaddadp 2, 1, 0
+; CHECK-FAST-NEXT:    fmr 1, 2
+; CHECK-FAST-NEXT:    blr
+;
+; CHECK-FAST-NOVSX-LABEL: fma_combine_const:
+; CHECK-FAST-NOVSX:       # %bb.0: # %entry
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
+; CHECK-FAST-NOVSX-NEXT:    lfd 0, .LCPI9_0@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    fmadd 1, 1, 0, 2
+; CHECK-FAST-NOVSX-NEXT:    blr
+;
+; CHECK-LABEL: fma_combine_const:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
+; CHECK-NEXT:    lfd 0, .LCPI9_0@toc@l(3)
+; CHECK-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
+; CHECK-NEXT:    lfd 3, .LCPI9_1@toc@l(3)
+; CHECK-NEXT:    xsmuldp 0, 1, 0
+; CHECK-NEXT:    fmr 1, 2
+; CHECK-NEXT:    xsmaddadp 1, 0, 3
+; CHECK-NEXT:    blr
+entry:
+  %0 = fmul double %a, 1.1
+  %1 = call contract double @llvm.fma.f64(double %0, double 2.1, double %b)
+  ret double %1
+}
+
 declare double @llvm.fma.f64(double, double, double) nounwind readnone
 declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone

llvm/test/CodeGen/X86/fma-scalar-combine.ll

entry:
   %3 = fmul fast double %1, %0
   %4 = fsub fast double %sub, %3
   %5 = bitcast i8 %k to <8 x i1>
   %6 = extractelement <8 x i1> %5, i64 0
   %7 = select i1 %6, double %4, double %2
   %8 = insertelement <2 x double> %c, double %7, i64 0
   ret <2 x double> %8
 }
+
+; Don't fold into (fmul x, c1+c2) if reassoc not set
+define float @fma_const_fmul(float %x) {
+; CHECK-LABEL: fma_const_fmul:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmulss {{.*}}(%rip), %xmm0, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x59,0x0d,A,A,A,A]
+; CHECK-NEXT:    # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte
+; CHECK-NEXT:    vfmadd132ss {{.*}}(%rip), %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x99,0x05,A,A,A,A]
+; CHECK-NEXT:    # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte
+; CHECK-NEXT:    # xmm0 = (xmm0 * mem) + xmm1
+; CHECK-NEXT:    retq # encoding: [0xc3]
+  %mul1 = fmul contract float %x, 10.0
+  %mul2 = fmul contract float %x, 11.0
+  %add1 = fadd contract float %mul1, %mul2
+  ret float %add1
+}