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[VP][SelectionDAG] Add a target-configurable EVL operand type
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Authored by frasercrmck on May 24 2021, 7:37 AM.

Details

Summary

This patch adds a way for the target to configure the type it uses for
the explicit vector length operands of VP SDNodes. The type must be a
legal integer type (there is still no target-independent legalization of
this operand) and must currently be at least as big as i32, the type
used by the IR intrinsics. An implicit zero-extension takes place on
targets which choose a larger type. All VP nodes should be created with
this type used for the EVL operand.

This allows 64-bit RISC-V to avoid custom legalization of all VP nodes,
keeping them in their target-independent form for that bit longer.

Diff Detail

Event Timeline

frasercrmck created this revision.May 24 2021, 7:37 AM
frasercrmck requested review of this revision.May 24 2021, 7:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 24 2021, 7:37 AM

Apart from the nit, this looks good to me. @rogfer01 ?

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
7307

Hoist this up? The assertion does not (actually) depend on the loop.

frasercrmck marked an inline comment as done.
  • rebase
  • hoist assertion
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
7307

Ah yes, leftover from some refactoring. Thanks!

simoll accepted this revision.May 27 2021, 5:00 AM
This revision is now accepted and ready to land.May 27 2021, 5:00 AM
This revision was landed with ongoing or failed builds.May 27 2021, 7:35 AM
This revision was automatically updated to reflect the committed changes.