Page MenuHomePhabricator

[AArch64][SVE] Improve SVE codegen for fixed length BITCAST

Authored by bsmith on May 6 2021, 5:58 AM.



Expanding a fixed length operation involves wrapping the operation in an
insert/extract subvector pair, as such, when this is done to bitcast we
end up with an extract_subvector of a bitcast. DAGCombine tries to
convert this into a bitcast of an extract_subvector which restores the
initial fixed length bitcast, causing an infinite loop of legalization.

As part of this patch, we must make sure the above DAGCombine does not
trigger after legalization if the created bitcast would not be legal.

Diff Detail

Event Timeline

bsmith created this revision.May 6 2021, 5:58 AM
bsmith requested review of this revision.May 6 2021, 5:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 6 2021, 5:58 AM



nit: Not sure what others think, but I personally found this a little confusing. I realise you're reusing Op here, but I'd kind of expected something like this:

SrcOp = convertToScalableVector(DAG, ContainerSrcVT, SrcOp);
Op = DAG.getNode(ISD::BITCAST, DL, ContainerDstVT, SrcOp);
david-arm accepted this revision.May 6 2021, 7:20 AM
This revision is now accepted and ready to land.May 6 2021, 7:20 AM
Matt added a subscriber: Matt.May 7 2021, 8:22 AM
This revision was landed with ongoing or failed builds.May 10 2021, 6:52 AM
This revision was automatically updated to reflect the committed changes.