[RISCV] Teach normaliseSetCC to canonicalize X > -1 to X >= 0 and X < 1 to 0 >= X.

[craig.topper]

Summary

This allows the use of BGE with X0 instead of puting -1/1 in a
register.

[jrtc27]

Hm, this seems like a bit of an abuse of what the function is intended to do, at least with its current name and comment, as it's now not just doing normalisation for mapping to the set of supported instructions but also optimising at the same time.

[craig.topper]

Improve comment and try to improve function name to encapsulate new behavior.

[jrtc27]

In D98542#2623036, @craig.topper wrote:

Improve comment and try to improve function name to encapsulate new behavior.

Thanks, looks better now to me (and I was struggling to come up with a good name myself otherwise I would have suggested one).

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 
 bool RISCVTargetLowering::hasBitPreservingFPLogic(EVT VT) const {
   return (VT == MVT::f16 && Subtarget.hasStdExtZfh()) ||
          (VT == MVT::f32 && Subtarget.hasStdExtF()) ||
          (VT == MVT::f64 && Subtarget.hasStdExtD());
 }
 
 // Changes the condition code and swaps operands if necessary, so the SetCC
-// operation matches one of the comparisons supported directly in the RISC-V
-// ISA.
-static void normaliseSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
+// operation matches one of the comparisons supported directly by branches
+// in the RISC-V ISA. May adjust compares to favor compare with 0 over compare
+// with 1/-1.
+static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
+                                    ISD::CondCode &CC, SelectionDAG &DAG) {
+  // Convert X > -1 to X >= 0.
+  if (CC == ISD::SETGT && isAllOnesConstant(RHS)) {
+    RHS = DAG.getConstant(0, DL, RHS.getValueType());
+    CC = ISD::SETGE;
+    return;
+  }
+  // Convert X < 1 to 0 >= X.
+  if (CC == ISD::SETLT && isOneConstant(RHS)) {
+    RHS = LHS;
+    LHS = DAG.getConstant(0, DL, RHS.getValueType());
+    CC = ISD::SETGE;
+    return;
+  }
+
   switch (CC) {
   default:
     break;
   case ISD::SETGT:
   case ISD::SETLE:
   case ISD::SETUGT:
   case ISD::SETULE:
     CC = ISD::getSetCCSwappedOperands(CC);
     std::swap(LHS, RHS);
     break;
   }
 }
 
 // Return the RISC-V branch opcode that matches the given DAG integer
 // condition code. The CondCode must be one of those supported by the RISC-V
-// ISA (see normaliseSetCC).
+// ISA (see translateSetCCForBranch).
 static unsigned getBranchOpcodeForIntCondCode(ISD::CondCode CC) {
   switch (CC) {
   default:
     llvm_unreachable("Unsupported CondCode");
   case ISD::SETEQ:
     return RISCV::BEQ;
   case ISD::SETNE:
     return RISCV::BNE;
SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
   if (Op.getSimpleValueType() == XLenVT && CondV.getOpcode() == ISD::SETCC &&
       CondV.getOperand(0).getSimpleValueType() == XLenVT) {
     SDValue LHS = CondV.getOperand(0);
     SDValue RHS = CondV.getOperand(1);
     auto CC = cast<CondCodeSDNode>(CondV.getOperand(2));
     ISD::CondCode CCVal = CC->get();
 
-    normaliseSetCC(LHS, RHS, CCVal);
+    translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
 
     SDValue TargetCC = DAG.getConstant(CCVal, DL, XLenVT);
     SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
     return DAG.getNode(RISCVISD::SELECT_CC, DL, Op.getValueType(), Ops);
   }
 
   // Otherwise:
   // (select condv, truev, falsev)
if (LHS.getOpcode() == ISD::SETCC && isNullConstant(RHS) &&
         LHS.getOperand(0).getValueType() == Subtarget.getXLenVT()) {
       // If we're looking for eq 0 instead of ne 0, we need to invert the
       // condition.
       bool Invert = CCVal == ISD::SETEQ;
       CCVal = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
       if (Invert)
         CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType());
 
+      SDLoc DL(N);
       RHS = LHS.getOperand(1);
       LHS = LHS.getOperand(0);
-      normaliseSetCC(LHS, RHS, CCVal);
+      translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
 
-      SDLoc DL(N);
       SDValue TargetCC = DAG.getConstant(CCVal, DL, Subtarget.getXLenVT());
       return DAG.getNode(
           RISCVISD::SELECT_CC, DL, N->getValueType(0),
           {LHS, RHS, TargetCC, N->getOperand(3), N->getOperand(4)});
     }
 
     // Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) ->
     //      (select_cc X, Y, eq/ne, trueV, falseV)

llvm/test/CodeGen/RISCV/select-cc.ll

 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB0_18:
 ; RV32I-NEXT:    lw a2, 0(a1)
 ; RV32I-NEXT:    bge a2, a0, .LBB0_20
 ; RV32I-NEXT:  # %bb.19:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB0_20:
 ; RV32I-NEXT:    lw a2, 0(a1)
-; RV32I-NEXT:    addi a3, zero, 1
-; RV32I-NEXT:    blt a2, a3, .LBB0_22
+; RV32I-NEXT:    blez a2, .LBB0_22
 ; RV32I-NEXT:  # %bb.21:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB0_22:
 ; RV32I-NEXT:    lw a1, 0(a1)
-; RV32I-NEXT:    addi a3, zero, -1
-; RV32I-NEXT:    blt a3, a2, .LBB0_24
+; RV32I-NEXT:    bgez a2, .LBB0_24
 ; RV32I-NEXT:  # %bb.23:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_24:
 ; RV32I-NEXT:    ret
 ;
 ; RV32IBT-LABEL: foo:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    lw a2, 0(a1)