Added the situation of Mask == 0.

Patch D92089 can cover this.

The patch D92089 can cover this.

@steven.zhang I still have some doubts about the properties setting. According to the behavior described by ISA, it also includes the write operation?

According to ISA,

DCBF (Data Cache Block Flush) is treated as a Load, except that reference and change recording need not be done.

it is appropriate to set IntrReadMem, IntrArgMemOnly for these dcbf_ instructions.

Added test cases.

Updated as Zheng's suggestions.

In D89855#2398960, @shchenz wrote:

I saw some testcases are removed compared with your committed version. Is there any reason?

Added a BE line in the test.

In post-RA, if SrcMI also defines the register to be forwarded, we can only do the folding if SrcMI is going to be erased.
For example, SrcMI and MI can't not be folded in the scenario:

$r3 = RLWINM_rec $r3, 27, 5, 10, implicit-def $cr0
dead renamable $r3 = RLWINM_rec killed renamable $r3, 8, 5, 10, implicit-def $cr0
BLR8 implicit $lr8, implicit $rm, implicit killed $cr0

I've run the bootstrap-test as well as SEPC.

ping

Thanks for your reviews, and I apologize for not responding in time. I will commit this patch after all tests done.

Updated as Steven's comments.

@RKSimon Thanks. Updated.

In D88278#2306618, @amyk wrote:

Overall I think this LGTM.

Please correct me if I am wrong but I think the description of the functions need to be updated to:

int vec_test_swdiv(vector double v1, vector double v2);
int vec_test_swdivs(vector float v1, vector float v2);
int vec_test_swsqrt(vector double v1);
int vec_test_swsqrts(vector float v1);

Looking forward to your further comments :) @jsji @nemanjai

In D88274#2305121, @shchenz wrote:

LGTM too. Thanks for sharing the background. Before committing this, it's better to update the description for later reference like @nemanjai pointed out?

In D88274#2300438, @nemanjai wrote:

LGTM. The code here is correct, but I do have a couple of questions:

1. Do these copies come up in real code? And if so, under which circumstances. We don't have copies in the other direction implemented, so that makes me wonder when these ever come up.
2. Does this solve a problem seen in real code? If so, is there a bugzilla report? At the very least, the conditions under which this causes a problem should be added to the description.
3. Is there any follow up required/planned for this?

Skip rotation if CR7.

Format.

Thank you so much for your comments. :D @jsji @nemanjai
I have post another patch D88201 to handle scenario 2 and 3 in DAGCombiner.

Update comments.

Hi @jsji An infinite loop will occur if we handle the scenario 1 (mul X, c2 << c1) -> (shl (mul X, c2), c1) in DAGCombiner, because there exists a reverse conversion (shl (mul x, c1), c2) -> (mul x, c1 << c2).

Keep the scenario 1 implemented in ISEL.
For scenario 2 and 3, I will post another patch to implement them in DAGCombiner.

Thank you for your comments! @jsji @nemanjai

Update predictions for test cases.