[RISCV} Fold (select_cc (setlt X, Y), 0, ne, trueV, falseV) -> (select_cc X, Y, lt, trueV, falseV)

[craig.topper]

Summary

A setcc can be created during LegalizeDAG after select_cc has been
created. This combine will enable us to fold these late setccs.

[luismarques]

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3803

Nit: "We're" capitalization.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
case ISD::OR:
     break;
   case RISCVISD::SELECT_CC: {
     // Transform
     SDValue LHS = N->getOperand(0);
     SDValue RHS = N->getOperand(1);
     auto CCVal = static_cast<ISD::CondCode>(N->getConstantOperandVal(2));
     if (!ISD::isIntEqualitySetCC(CCVal))
       break;
+
+    // Fold (select_cc (setlt X, Y), 0, ne, trueV, falseV) ->
+    //      (select_cc X, Y, lt, trueV, falseV)
+    // Sometimes the setcc is introduced after select_cc has been formed.
+    if (LHS.getOpcode() == ISD::SETCC && isNullConstant(RHS) &&
+        LHS.getOperand(0).getValueType() == Subtarget.getXLenVT()) {
+      // If We're looking for eq 0 instead of ne 0, we need to invert the
+      // condition.
+      bool Invert = CCVal == ISD::SETEQ;
+      CCVal = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
+      if (Invert)
+        CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType());
+
+      RHS = LHS.getOperand(1);
+      LHS = LHS.getOperand(0);
+      normaliseSetCC(LHS, RHS, CCVal);
+
+      SDLoc DL(N);
+      SDValue TargetCC = DAG.getConstant(CCVal, DL, Subtarget.getXLenVT());
+      return DAG.getNode(
+          RISCVISD::SELECT_CC, DL, N->getValueType(0),
+          {LHS, RHS, TargetCC, N->getOperand(3), N->getOperand(4)});
+    }
+
     // Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) ->
     //      (select_cc X, Y, eq/ne, trueV, falseV)
     if (LHS.getOpcode() == ISD::XOR && isNullConstant(RHS))
       return DAG.getNode(RISCVISD::SELECT_CC, SDLoc(N), N->getValueType(0),
                          {LHS.getOperand(0), LHS.getOperand(1),
                           N->getOperand(2), N->getOperand(3),
                           N->getOperand(4)});
     // (select_cc X, 1, setne, trueV, falseV) ->

llvm/test/CodeGen/RISCV/uadd_sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
 
 declare i4 @llvm.uadd.sat.i4(i4, i4)
 declare i8 @llvm.uadd.sat.i8(i8, i8)
 declare i16 @llvm.uadd.sat.i16(i16, i16)
 declare i32 @llvm.uadd.sat.i32(i32, i32)
 declare i64 @llvm.uadd.sat.i64(i64, i64)
 
 define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV32I-LABEL: func:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    add a1, a0, a1
-; RV32I-NEXT:    sltu a2, a1, a0
 ; RV32I-NEXT:    addi a0, zero, -1
-; RV32I-NEXT:    bnez a2, .LBB0_2
+; RV32I-NEXT:    bltu a1, a2, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 32

 ; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:  .LBB1_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    add a1, a0, a1
-; RV64I-NEXT:    sltu a2, a1, a0
 ; RV64I-NEXT:    addi a0, zero, -1
-; RV64I-NEXT:    bnez a2, .LBB1_2
+; RV64I-NEXT:    bltu a1, a2, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB1_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    add a3, a1, a3

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
 
 declare i4 @llvm.uadd.sat.i4(i4, i4)
 declare i8 @llvm.uadd.sat.i8(i8, i8)
 declare i16 @llvm.uadd.sat.i16(i16, i16)
 declare i32 @llvm.uadd.sat.i32(i32, i32)
 declare i64 @llvm.uadd.sat.i64(i64, i64)
 
 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV32I-LABEL: func32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mul a1, a1, a2
-; RV32I-NEXT:    add a1, a0, a1
-; RV32I-NEXT:    sltu a2, a1, a0
+; RV32I-NEXT:    mv a3, a0
+; RV32I-NEXT:    mul a0, a1, a2
+; RV32I-NEXT:    add a1, a3, a0
 ; RV32I-NEXT:    addi a0, zero, -1
-; RV32I-NEXT:    bnez a2, .LBB0_2
+; RV32I-NEXT:    bltu a1, a3, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 32

 ; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:  .LBB1_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    add a1, a0, a2
-; RV64I-NEXT:    sltu a2, a1, a0
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    add a2, a0, a2
 ; RV64I-NEXT:    addi a0, zero, -1
-; RV64I-NEXT:    bnez a2, .LBB1_2
+; RV64I-NEXT:    bltu a2, a1, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB1_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    add a3, a1, a5
 ; RV32IZbb-NEXT:    add a2, a0, a4
 ; RV32IZbb-NEXT:    sltu a4, a2, a0

llvm/test/CodeGen/RISCV/usub_sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
 
 declare i4 @llvm.usub.sat.i4(i4, i4)
 declare i8 @llvm.usub.sat.i8(i8, i8)
 declare i16 @llvm.usub.sat.i16(i16, i16)
 declare i32 @llvm.usub.sat.i32(i32, i32)
 declare i64 @llvm.usub.sat.i64(i64, i64)
 
 define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV32I-LABEL: func:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    sltu a2, a0, a1
 ; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    bnez a2, .LBB0_2
+; RV32I-NEXT:    bltu a2, a1, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a2, a0, 32
 ; RV64I-NEXT:    sub a0, a2, a1
-; RV64I-NEXT:    sltu a2, a2, a0
 ; RV64I-NEXT:    mv a1, zero
-; RV64I-NEXT:    bnez a2, .LBB0_2
+; RV64I-NEXT:    bltu a2, a0, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:  .LBB0_2:
 ; RV64I-NEXT:    sext.w a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func:
 ; RV32IZbb:       # %bb.0:

 ; RV32I-NEXT:  # %bb.4:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:  .LBB1_5:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    sub a1, a0, a1
-; RV64I-NEXT:    sltu a2, a0, a1
 ; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bnez a2, .LBB1_2
+; RV64I-NEXT:    bltu a2, a1, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB1_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    sltu a4, a0, a2

 ; RV64IZbb-NEXT:    ret
   %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }
 
 define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
 ; RV32I-LABEL: func16:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    sltu a2, a0, a1
-; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    bnez a2, .LBB2_2
+; RV32I-NEXT:    sub a2, a0, a1
+; RV32I-NEXT:    mv a1, zero
+; RV32I-NEXT:    bltu a0, a2, .LBB2_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:  .LBB2_2:
-; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi a1, a1, -1
-; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    lui a0, 16
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func16:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    sub a1, a0, a1
-; RV64I-NEXT:    sltu a2, a0, a1
-; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bnez a2, .LBB2_2
+; RV64I-NEXT:    sub a2, a0, a1
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:    bltu a0, a2, .LBB2_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    mv a1, a2
 ; RV64I-NEXT:  .LBB2_2:
-; RV64I-NEXT:    lui a1, 16
-; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    lui a0, 16
+; RV64I-NEXT:    addiw a0, a0, -1
+; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func16:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    maxu a0, a0, a1
 ; RV32IZbb-NEXT:    sub a0, a0, a1
 ; RV32IZbb-NEXT:    zext.h a0, a0
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func16:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    maxu a0, a0, a1
 ; RV64IZbb-NEXT:    sub a0, a0, a1
 ; RV64IZbb-NEXT:    zext.h a0, a0
 ; RV64IZbb-NEXT:    ret
   %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y);
   ret i16 %tmp;
 }
 
 define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
 ; RV32I-LABEL: func8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    sltu a2, a0, a1
-; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    bnez a2, .LBB3_2
+; RV32I-NEXT:    mv a2, zero
+; RV32I-NEXT:    bltu a0, a1, .LBB3_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    mv a2, a1
 ; RV32I-NEXT:  .LBB3_2:
-; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    andi a0, a2, 255
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func8:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sub a1, a0, a1
-; RV64I-NEXT:    sltu a2, a0, a1
-; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bnez a2, .LBB3_2
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    bltu a0, a1, .LBB3_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    mv a2, a1
 ; RV64I-NEXT:  .LBB3_2:
-; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    andi a0, a2, 255
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func8:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    maxu a0, a0, a1
 ; RV32IZbb-NEXT:    sub a0, a0, a1
 ; RV32IZbb-NEXT:    andi a0, a0, 255
 ; RV32IZbb-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func8:
 ; RV64IZbb:       # %bb.0:
 ; RV64IZbb-NEXT:    maxu a0, a0, a1
 ; RV64IZbb-NEXT:    sub a0, a0, a1
 ; RV64IZbb-NEXT:    andi a0, a0, 255
 ; RV64IZbb-NEXT:    ret
   %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y);
   ret i8 %tmp;
 }
 
 define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
 ; RV32I-LABEL: func3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    sltu a2, a0, a1
-; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    bnez a2, .LBB4_2
+; RV32I-NEXT:    mv a2, zero
+; RV32I-NEXT:    bltu a0, a1, .LBB4_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    mv a2, a1
 ; RV32I-NEXT:  .LBB4_2:
-; RV32I-NEXT:    andi a0, a0, 15
+; RV32I-NEXT:    andi a0, a2, 15
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func3:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sub a1, a0, a1
-; RV64I-NEXT:    sltu a2, a0, a1
-; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bnez a2, .LBB4_2
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    bltu a0, a1, .LBB4_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    mv a2, a1
 ; RV64I-NEXT:  .LBB4_2:
-; RV64I-NEXT:    andi a0, a0, 15
+; RV64I-NEXT:    andi a0, a2, 15
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func3:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    maxu a0, a0, a1
 ; RV32IZbb-NEXT:    sub a0, a0, a1
 ; RV32IZbb-NEXT:    andi a0, a0, 15
 ; RV32IZbb-NEXT:    ret

llvm/test/CodeGen/RISCV/usub_sat_plus.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
 
 declare i4 @llvm.usub.sat.i4(i4, i4)
 declare i8 @llvm.usub.sat.i8(i8, i8)
 declare i16 @llvm.usub.sat.i16(i16, i16)
 declare i32 @llvm.usub.sat.i32(i32, i32)
 declare i64 @llvm.usub.sat.i64(i64, i64)
 
 define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV32I-LABEL: func32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    mul a1, a1, a2
-; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    sltu a2, a0, a1
+; RV32I-NEXT:    mv a3, a0
+; RV32I-NEXT:    mul a0, a1, a2
+; RV32I-NEXT:    sub a1, a3, a0
 ; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    bnez a2, .LBB0_2
+; RV32I-NEXT:    bltu a3, a1, .LBB0_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a3, a0, 32
+; RV64I-NEXT:    mul a0, a1, a2
+; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    mul a1, a1, a2
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    sub a1, a0, a1
-; RV64I-NEXT:    sltu a2, a0, a1
+; RV64I-NEXT:    sub a1, a3, a0
 ; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bnez a2, .LBB0_2
+; RV64I-NEXT:    bltu a3, a1, .LBB0_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB0_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func32:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mul a1, a1, a2

 ; RV32I-NEXT:  # %bb.4:
 ; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:  .LBB1_5:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    sub a1, a0, a2
-; RV64I-NEXT:    sltu a2, a0, a1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    sub a2, a0, a2
 ; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bnez a2, .LBB1_2
+; RV64I-NEXT:    bltu a1, a2, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB1_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    sltu a2, a0, a4
 ; RV32IZbb-NEXT:    sub a3, a1, a5
 ; RV32IZbb-NEXT:    sub a2, a3, a2
; RV64IZbb-NEXT:    ret
   ret i64 %tmp
 }
 
 define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
 ; RV32I-LABEL: func16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a3, 16
 ; RV32I-NEXT:    addi a3, a3, -1
+; RV32I-NEXT:    and a4, a0, a3
+; RV32I-NEXT:    mul a0, a1, a2
 ; RV32I-NEXT:    and a0, a0, a3
-; RV32I-NEXT:    mul a1, a1, a2
-; RV32I-NEXT:    and a1, a1, a3
-; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    sltu a2, a0, a1
+; RV32I-NEXT:    sub a1, a4, a0
 ; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    bnez a2, .LBB2_2
+; RV32I-NEXT:    bltu a4, a1, .LBB2_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB2_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 16
 ; RV64I-NEXT:    addiw a3, a3, -1
+; RV64I-NEXT:    and a4, a0, a3
+; RV64I-NEXT:    mul a0, a1, a2
 ; RV64I-NEXT:    and a0, a0, a3
-; RV64I-NEXT:    mul a1, a1, a2
-; RV64I-NEXT:    and a1, a1, a3
-; RV64I-NEXT:    sub a1, a0, a1
-; RV64I-NEXT:    sltu a2, a0, a1
+; RV64I-NEXT:    sub a1, a4, a0
 ; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bnez a2, .LBB2_2
+; RV64I-NEXT:    bltu a4, a1, .LBB2_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB2_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func16:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    zext.h a0, a0
; RV64IZbb-NEXT:    ret
   %a = mul i16 %y, %z
   %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)
   ret i16 %tmp
 }
 
 define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
 ; RV32I-LABEL: func8:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a3, a0, 255
+; RV32I-NEXT:    mul a0, a1, a2
 ; RV32I-NEXT:    andi a0, a0, 255
-; RV32I-NEXT:    mul a1, a1, a2
-; RV32I-NEXT:    andi a1, a1, 255
-; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    sltu a2, a0, a1
+; RV32I-NEXT:    sub a1, a3, a0
 ; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    bnez a2, .LBB3_2
+; RV32I-NEXT:    bltu a3, a1, .LBB3_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB3_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func8:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a3, a0, 255
+; RV64I-NEXT:    mul a0, a1, a2
 ; RV64I-NEXT:    andi a0, a0, 255
-; RV64I-NEXT:    mul a1, a1, a2
-; RV64I-NEXT:    andi a1, a1, 255
-; RV64I-NEXT:    sub a1, a0, a1
-; RV64I-NEXT:    sltu a2, a0, a1
+; RV64I-NEXT:    sub a1, a3, a0
 ; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bnez a2, .LBB3_2
+; RV64I-NEXT:    bltu a3, a1, .LBB3_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB3_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func8:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    andi a0, a0, 255
; RV64IZbb-NEXT:    ret
   %a = mul i8 %y, %z
   %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)
   ret i8 %tmp
 }
 
 define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
 ; RV32I-LABEL: func4:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a3, a0, 15
+; RV32I-NEXT:    mul a0, a1, a2
 ; RV32I-NEXT:    andi a0, a0, 15
-; RV32I-NEXT:    mul a1, a1, a2
-; RV32I-NEXT:    andi a1, a1, 15
-; RV32I-NEXT:    sub a1, a0, a1
-; RV32I-NEXT:    sltu a2, a0, a1
+; RV32I-NEXT:    sub a1, a3, a0
 ; RV32I-NEXT:    mv a0, zero
-; RV32I-NEXT:    bnez a2, .LBB4_2
+; RV32I-NEXT:    bltu a3, a1, .LBB4_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:  .LBB4_2:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func4:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a3, a0, 15
+; RV64I-NEXT:    mul a0, a1, a2
 ; RV64I-NEXT:    andi a0, a0, 15
-; RV64I-NEXT:    mul a1, a1, a2
-; RV64I-NEXT:    andi a1, a1, 15
-; RV64I-NEXT:    sub a1, a0, a1
-; RV64I-NEXT:    sltu a2, a0, a1
+; RV64I-NEXT:    sub a1, a3, a0
 ; RV64I-NEXT:    mv a0, zero
-; RV64I-NEXT:    bnez a2, .LBB4_2
+; RV64I-NEXT:    bltu a3, a1, .LBB4_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:  .LBB4_2:
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func4:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    andi a0, a0, 15

llvm/test/CodeGen/RISCV/xaluo.ll

entry:
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: uaddo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a2, a0, a1
-; RV32-NEXT:    sltu a2, a2, a0
-; RV32-NEXT:    bnez a2, .LBB26_2
+; RV32-NEXT:    bltu a2, a0, .LBB26_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:  .LBB26_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    slli a2, a1, 32

 ; RV32-NEXT:  .LBB28_4: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
-; RV64-NEXT:    sltu a2, a2, a0
-; RV64-NEXT:    bnez a2, .LBB28_2
+; RV64-NEXT:    bltu a2, a0, .LBB28_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB28_2: # %entry
 ; RV64-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
entry:
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: usubo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sub a2, a0, a1
-; RV32-NEXT:    sltu a2, a0, a2
-; RV32-NEXT:    bnez a2, .LBB34_2
+; RV32-NEXT:    bltu a0, a2, .LBB34_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:  .LBB34_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    slli a2, a1, 32

 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:  .LBB36_4: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sub a2, a0, a1
-; RV64-NEXT:    sltu a2, a0, a2
-; RV64-NEXT:    bnez a2, .LBB36_2
+; RV64-NEXT:    bltu a0, a2, .LBB36_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB36_2: # %entry
 ; RV64-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2

 }
 
 define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: smulo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mulh a2, a0, a1
 ; RV32-NEXT:    mul a3, a0, a1
 ; RV32-NEXT:    srai a3, a3, 31
-; RV32-NEXT:    xor a2, a2, a3
-; RV32-NEXT:    snez a2, a2
-; RV32-NEXT:    bnez a2, .LBB38_2
+; RV32-NEXT:    bne a2, a3, .LBB38_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:  .LBB38_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.select.i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sext.w a2, a1

 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: smulo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulh a2, a0, a1
 ; RV64-NEXT:    mul a3, a0, a1
 ; RV64-NEXT:    srai a3, a3, 63
-; RV64-NEXT:    xor a2, a2, a3
-; RV64-NEXT:    snez a2, a2
-; RV64-NEXT:    bnez a2, .LBB40_2
+; RV64-NEXT:    bne a2, a3, .LBB40_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB40_2: # %entry
 ; RV64-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
entry:
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
 ; RV32-LABEL: umulo.select.i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mulhu a2, a0, a1
-; RV32-NEXT:    snez a2, a2
 ; RV32-NEXT:    bnez a2, .LBB42_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:  .LBB42_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.select.i32:
 ; RV64:       # %bb.0: # %entry

 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:  .LBB44_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulhu a2, a0, a1
-; RV64-NEXT:    snez a2, a2
 ; RV64-NEXT:    bnez a2, .LBB44_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB44_2: # %entry
 ; RV64-NEXT:    ret
 entry:
   %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
   %obit = extractvalue {i64, i1} %t, 1