The types in Zvlsseg occupy multiple vector registers. We use Record type in clang to represent Zvlsseg types. It will not increase the number of builtin types in clang. It just adds multiple implicit defined Record types for Zvlsseg.
I was under the impression we didn't want to use class-member access syntax for vector tuples (see https://github.com/riscv/rvv-intrinsic-doc/issues/17#issuecomment-628998077 ) so we don't need a record type, do we?
Perhaps it is possible to model them like opaque entities similar to what we do with RVV vectors where they are expanded in CodegenTypes.cpp?
Access to fields would have to be through intrinsics, though I think this didn't scale very well, did it?
I'm confused by this lookup.
If you add RvvInt8mf8Ty in the macros above will you be able to use it for types such as RvvInt8mf8x2Ty, RvvInt8mf8x3Ty, etc. without having to search it in all the types?
AFAICT ElemId seems only used in this case so perhaps we can use the "name of the field of ASTContext" (a CanQualType) directly.