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[RISCV] Use whole register load/store for generic load/store.
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Authored by HsiangKai on Feb 2 2021, 12:16 AM.

Details

Summary

In vector v0.10, there are whole vector register load/store instructions. I suggest to use the whole register load/store instructions for generic load/store for scalable vector types. It could save up vset{i}vl{i} for these load/store.

For fractional LMUL, I keep to use vle{eew}.v/vse{eew}.v instructions to load/store partial vector registers.

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Event Timeline

HsiangKai created this revision.Feb 2 2021, 12:16 AM
HsiangKai requested review of this revision.Feb 2 2021, 12:16 AM
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HsiangKai updated this revision to Diff 320747.Feb 2 2021, 4:18 AM

On the whole this seems like a good idea to me. Are there any downsides?

craig.topper added inline comments.Feb 8 2021, 3:34 PM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
901

Can we use MCRegisterInfo::getMatchingSuperReg to get do this conversion?

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
183

Can we get the VR register name with RISCV::V0 + RegNo and then convert with getMatchingSuperReg?

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
179–180

indent these lines?

213–214

indent these lines

craig.topper added inline comments.Feb 8 2021, 3:35 PM
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
183

Though we might not be able to get to MRI from here?

HsiangKai updated this revision to Diff 322244.Feb 8 2021, 5:05 PM

Address @craig.topper's comments.

HsiangKai marked 3 inline comments as done.Feb 8 2021, 5:07 PM
HsiangKai updated this revision to Diff 322245.Feb 8 2021, 5:10 PM

Formatting.

HsiangKai marked 2 inline comments as done.Feb 8 2021, 5:10 PM
This revision is now accepted and ready to land.Feb 8 2021, 8:01 PM
This revision was landed with ongoing or failed builds.Feb 8 2021, 11:53 PM
This revision was automatically updated to reflect the committed changes.