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Differential D95853

[RISCV] Use whole register load/store for generic load/store.
ClosedPublic

Authored by HsiangKai on Feb 2 2021, 12:16 AM.

Details

Reviewers
craig.topper
frasercrmck
rogfer01
evandro
Commits
rGa2d19bad0745: [RISCV] Use whole register load/store for generic load/store.
Summary

In vector v0.10, there are whole vector register load/store instructions. I suggest to use the whole register load/store instructions for generic load/store for scalable vector types. It could save up vset{i}vl{i} for these load/store.

For fractional LMUL, I keep to use vle{eew}.v/vse{eew}.v instructions to load/store partial vector registers.

Diff Detail

Event Timeline

HsiangKai created this revision.Feb 2 2021, 12:16 AM
Herald added subscribers: StephenFan, vkmr, NickHung and 25 others. · View Herald TranscriptFeb 2 2021, 12:16 AM
HsiangKai requested review of this revision.Feb 2 2021, 12:16 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 2 2021, 12:16 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B87484: Diff 320696.Feb 2 2021, 12:17 AM
HsiangKai updated this revision to Diff 320713.Feb 2 2021, 1:38 AM

Rebase.

Harbormaster completed remote builds in B87492: Diff 320713.Feb 2 2021, 1:39 AM
HsiangKai updated this revision to Diff 320747.Feb 2 2021, 4:18 AM
Harbormaster completed remote builds in B87511: Diff 320747.Feb 2 2021, 4:25 AM
HsiangKai updated this revision to Diff 321002.Feb 2 2021, 10:04 PM

Rebase.

Harbormaster completed remote builds in B87644: Diff 321002.Feb 2 2021, 10:57 PM
frasercrmck added a comment.Feb 4 2021, 1:48 AM

On the whole this seems like a good idea to me. Are there any downsides?

craig.topper added inline comments.Feb 8 2021, 3:34 PM
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
901

Can we use MCRegisterInfo::getMatchingSuperReg to get do this conversion?

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
183

Can we get the VR register name with RISCV::V0 + RegNo and then convert with getMatchingSuperReg?

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
179–180

indent these lines?

213–214

indent these lines

craig.topper added inline comments.Feb 8 2021, 3:35 PM
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
183

Though we might not be able to get to MRI from here?

HsiangKai updated this revision to Diff 322244.Feb 8 2021, 5:05 PM

Address @craig.topper's comments.

Harbormaster completed remote builds in B88372: Diff 322244.Feb 8 2021, 5:05 PM
HsiangKai marked 3 inline comments as done.Feb 8 2021, 5:07 PM
HsiangKai updated this revision to Diff 322245.Feb 8 2021, 5:10 PM

Formatting.

Harbormaster completed remote builds in B88373: Diff 322245.Feb 8 2021, 5:10 PM
HsiangKai marked 2 inline comments as done.Feb 8 2021, 5:10 PM
craig.topper accepted this revision.Feb 8 2021, 8:01 PM

LGTM

This revision is now accepted and ready to land.Feb 8 2021, 8:01 PM
This revision was landed with ongoing or failed builds.Feb 8 2021, 11:53 PM
Closed by commit rGa2d19bad0745: [RISCV] Use whole register load/store for generic load/store. (authored by HsiangKai). · Explain Why
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rGa2d19bad0745: [RISCV] Use whole register load/store for generic load/store..

Revision Contents

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RISCV/
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RISCV/
rvv/
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Diff 322245

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Show First 20 Lines • Show All 888 Lines • ▼ Show 20 Linesstatic MCRegister convertFPR64ToFPR16(MCRegister Reg) {
return Reg - RISCV::F0_D + RISCV::F0_H; return Reg - RISCV::F0_D + RISCV::F0_H;
} }
static MCRegister convertFPR64ToFPR32(MCRegister Reg) { static MCRegister convertFPR64ToFPR32(MCRegister Reg) {
assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register"); assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
return Reg - RISCV::F0_D + RISCV::F0_F; return Reg - RISCV::F0_D + RISCV::F0_F;
} }
static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
unsigned Kind) {
unsigned RegClassID;
if (Kind == MCK_VRM2)
RegClassID = RISCV::VRM2RegClassID;
craig.topperUnsubmitted
Done
ReplyInline Actions

Can we use MCRegisterInfo::getMatchingSuperReg to get do this conversion?

craig.topper: Can we use MCRegisterInfo::getMatchingSuperReg to get do this conversion?
else if (Kind == MCK_VRM4)
RegClassID = RISCV::VRM4RegClassID;
else if (Kind == MCK_VRM8)
RegClassID = RISCV::VRM8RegClassID;
else
return 0;
return RI.getMatchingSuperReg(Reg, RISCV::sub_vrm1_0,
&RISCVMCRegisterClasses[RegClassID]);
}
unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
unsigned Kind) { unsigned Kind) {
RISCVOperand &Op = static_cast<RISCVOperand &>(AsmOp); RISCVOperand &Op = static_cast<RISCVOperand &>(AsmOp);
if (!Op.isReg()) if (!Op.isReg())
return Match_InvalidOperand; return Match_InvalidOperand;
MCRegister Reg = Op.getReg(); MCRegister Reg = Op.getReg();
bool IsRegFPR64 = bool IsRegFPR64 =
RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg); RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg);
bool IsRegFPR64C = bool IsRegFPR64C =
RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg); RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);
// As the parser couldn't differentiate an FPR32 from an FPR64, coerce the // As the parser couldn't differentiate an FPR32 from an FPR64, coerce the
// register from FPR64 to FPR32 or FPR64C to FPR32C if necessary. // register from FPR64 to FPR32 or FPR64C to FPR32C if necessary.
if ((IsRegFPR64 && Kind == MCK_FPR32) || if ((IsRegFPR64 && Kind == MCK_FPR32) ||
(IsRegFPR64C && Kind == MCK_FPR32C)) { (IsRegFPR64C && Kind == MCK_FPR32C)) {
Op.Reg.RegNum = convertFPR64ToFPR32(Reg); Op.Reg.RegNum = convertFPR64ToFPR32(Reg);
return Match_Success; return Match_Success;
} }
// As the parser couldn't differentiate an FPR16 from an FPR64, coerce the // As the parser couldn't differentiate an FPR16 from an FPR64, coerce the
// register from FPR64 to FPR16 if necessary. // register from FPR64 to FPR16 if necessary.
if (IsRegFPR64 && Kind == MCK_FPR16) { if (IsRegFPR64 && Kind == MCK_FPR16) {
Op.Reg.RegNum = convertFPR64ToFPR16(Reg); Op.Reg.RegNum = convertFPR64ToFPR16(Reg);
return Match_Success; return Match_Success;
} }
// As the parser couldn't differentiate an VRM2/VRM4/VRM8 from an VR, coerce
// the register from VR to VRM2/VRM4/VRM8 if necessary.
if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) {
Op.Reg.RegNum = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind);
if (Op.Reg.RegNum == 0)
return Match_InvalidOperand;
return Match_Success;
}
return Match_InvalidOperand; return Match_InvalidOperand;
} }
bool RISCVAsmParser::generateImmOutOfRangeError( bool RISCVAsmParser::generateImmOutOfRangeError(
OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper, OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper,
Twine Msg = "immediate must be an integer in the range") { Twine Msg = "immediate must be an integer in the range") {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]"); return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]");
▲ Show 20 Lines • Show All 1,700 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
if (RegNo >= 32) if (RegNo >= 32)
return MCDisassembler::Fail; return MCDisassembler::Fail;
MCRegister Reg = RISCV::V0 + RegNo; MCRegister Reg = RISCV::V0 + RegNo;
Inst.addOperand(MCOperand::createReg(Reg)); Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo >= 32)
return MCDisassembler::Fail;
if (RegNo % 2)
return MCDisassembler::Fail;
craig.topperUnsubmitted
Done
ReplyInline Actions

Can we get the VR register name with RISCV::V0 + RegNo and then convert with getMatchingSuperReg?

craig.topper: Can we get the VR register name with RISCV::V0 + RegNo and then convert with…
craig.topperUnsubmitted
Done
ReplyInline Actions

Though we might not be able to get to MRI from here?

craig.topper: Though we might not be able to get to MRI from here?
const RISCVDisassembler *Dis =
static_cast<const RISCVDisassembler *>(Decoder);
const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
MCRegister Reg =
RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
&RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo >= 32)
return MCDisassembler::Fail;
if (RegNo % 4)
return MCDisassembler::Fail;
const RISCVDisassembler *Dis =
static_cast<const RISCVDisassembler *>(Decoder);
const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
MCRegister Reg =
RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
&RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo >= 32)
return MCDisassembler::Fail;
if (RegNo % 8)
return MCDisassembler::Fail;
const RISCVDisassembler *Dis =
static_cast<const RISCVDisassembler *>(Decoder);
const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
MCRegister Reg =
RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
&RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
MCRegister Reg = RISCV::NoRegister; MCRegister Reg = RISCV::NoRegister;
switch (RegNo) { switch (RegNo) {
default: default:
return MCDisassembler::Fail; return MCDisassembler::Fail;
case 0: case 0:
Reg = RISCV::V0; Reg = RISCV::V0;
▲ Show 20 Lines • Show All 230 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
// load vd, (rs1), vs2, vm // load vd, (rs1), vs2, vm
class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr> class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
: RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0}, : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0},
(outs VR:$vd), (outs VR:$vd),
(ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
"$vd, (${rs1}), $vs2$vm">; "$vd, (${rs1}), $vs2$vm">;
// vl<nf>r.v vd, (rs1) // vl<nf>r.v vd, (rs1)
class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr> class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC>
: RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg, : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg,
width.Value{2-0}, (outs VR:$vd), (ins GPR:$rs1), width.Value{2-0}, (outs VRC:$vd), (ins GPR:$rs1),
opcodestr, "$vd, (${rs1})"> { opcodestr, "$vd, (${rs1})"> {
let vm = 1; let vm = 1;
let Uses = []; let Uses = [];
let RVVConstraint = NoConstraint; let RVVConstraint = NoConstraint;
} }
// segment load vd, (rs1), vm // segment load vd, (rs1), vm
class VUnitStrideSegmentLoad<bits<3> nf, RISCVLSUMOP lumop, class VUnitStrideSegmentLoad<bits<3> nf, RISCVLSUMOP lumop,
Show All 40 Lines
// store vd, vs3, (rs1), vs2, vm // store vd, vs3, (rs1), vs2, vm
class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr> class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
: RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs), : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
(ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm), (ins VR:$vs3, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
opcodestr, "$vs3, (${rs1}), $vs2$vm">; opcodestr, "$vs3, (${rs1}), $vs2$vm">;
// vs<nf>r.v vd, (rs1) // vs<nf>r.v vd, (rs1)
class VWholeStore<bits<3> nf, string opcodestr> class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC>
: RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg, : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg,
0b000, (outs), (ins VR:$vs3, GPR:$rs1), 0b000, (outs), (ins VRC:$vs3, GPR:$rs1),
opcodestr, "$vs3, (${rs1})"> { opcodestr, "$vs3, (${rs1})"> {
let vm = 1; let vm = 1;
let Uses = []; let Uses = [];
} }
// segment store vd, vs3, (rs1), vm // segment store vd, vs3, (rs1), vm
class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr> class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
: RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0}, : RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
▲ Show 20 Lines • Show All 242 Lines • ▼ Show 20 Linesmulticlass VALU_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>; def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>;
} }
multiclass VAMO<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> { multiclass VAMO<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> {
def _WD : VAMOWd<amoop, width, opcodestr>; def _WD : VAMOWd<amoop, width, opcodestr>;
def _UNWD : VAMONoWd<amoop, width, opcodestr>; def _UNWD : VAMONoWd<amoop, width, opcodestr>;
} }
multiclass VWholeLoad<bits<3> nf, string opcodestr> { multiclass VWholeLoad<bits<3> nf, string opcodestr, RegisterClass VRC> {
def E8_V : VWholeLoad<nf, LSWidth8, opcodestr # "e8.v">; def E8_V : VWholeLoad<nf, LSWidth8, opcodestr # "e8.v", VRC>;
def E16_V : VWholeLoad<nf, LSWidth16, opcodestr # "e16.v">; def E16_V : VWholeLoad<nf, LSWidth16, opcodestr # "e16.v", VRC>;
def E32_V : VWholeLoad<nf, LSWidth32, opcodestr # "e32.v">; def E32_V : VWholeLoad<nf, LSWidth32, opcodestr # "e32.v", VRC>;
def E64_V : VWholeLoad<nf, LSWidth64, opcodestr # "e64.v">; def E64_V : VWholeLoad<nf, LSWidth64, opcodestr # "e64.v", VRC>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instructions // Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
def VSUXEI32_V : VIndexedStore<MOPSTIndexedUnord, LSWidth32, "vsuxei32.v">; def VSUXEI32_V : VIndexedStore<MOPSTIndexedUnord, LSWidth32, "vsuxei32.v">;
def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">; def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">;
def VSOXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsoxei8.v">; def VSOXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsoxei8.v">;
def VSOXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsoxei16.v">; def VSOXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsoxei16.v">;
def VSOXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsoxei32.v">; def VSOXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsoxei32.v">;
def VSOXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsoxei64.v">; def VSOXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsoxei64.v">;
defm VL1R : VWholeLoad<1, "vl1r">; defm VL1R : VWholeLoad<1, "vl1r", VR>;
defm VL2R : VWholeLoad<2, "vl2r">; defm VL2R : VWholeLoad<2, "vl2r", VRM2>;
defm VL4R : VWholeLoad<4, "vl4r">; defm VL4R : VWholeLoad<4, "vl4r", VRM4>;
defm VL8R : VWholeLoad<8, "vl8r">; defm VL8R : VWholeLoad<8, "vl8r", VRM8>;
def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>;
def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VR:$vd, GPR:$rs1)>; def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>;
def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VR:$vd, GPR:$rs1)>; def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>;
def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VR:$vd, GPR:$rs1)>; def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>;
def VS1R_V : VWholeStore<1, "vs1r.v">; def VS1R_V : VWholeStore<1, "vs1r.v", VR>;
def VS2R_V : VWholeStore<2, "vs2r.v">; def VS2R_V : VWholeStore<2, "vs2r.v", VRM2>;
def VS4R_V : VWholeStore<4, "vs4r.v">; def VS4R_V : VWholeStore<4, "vs4r.v", VRM4>;
def VS8R_V : VWholeStore<8, "vs8r.v">; def VS8R_V : VWholeStore<8, "vs8r.v", VRM8>;
// Vector Single-Width Integer Add and Subtract // Vector Single-Width Integer Add and Subtract
defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>; defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>; defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
▲ Show 20 Lines • Show All 639 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Linesclass GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew,
RegisterClass ScalarReg = GPR> RegisterClass ScalarReg = GPR>
: VTypeInfo<Vec, Mas, Sew, Reg, M, Scal, ScalarReg> : VTypeInfo<Vec, Mas, Sew, Reg, M, Scal, ScalarReg>
{ {
ValueType VectorM1 = VecM1; ValueType VectorM1 = VecM1;
} }
defset list<VTypeInfo> AllVectors = { defset list<VTypeInfo> AllVectors = {
defset list<VTypeInfo> AllIntegerVectors = { defset list<VTypeInfo> AllIntegerVectors = {
defset list<VTypeInfo> NoGroupIntegerVectors = { defset list<VTypeInfo> NoGroupIntegerVectors = {
defset list<VTypeInfo> FractionalGroupIntegerVectors = {
craig.topperUnsubmitted
Done
ReplyInline Actions

indent these lines?

craig.topper: indent these lines?
def VI8MF8: VTypeInfo<vint8mf8_t, vbool64_t, 8, VR, V_MF8>; def VI8MF8: VTypeInfo<vint8mf8_t, vbool64_t, 8, VR, V_MF8>;
def VI8MF4: VTypeInfo<vint8mf4_t, vbool32_t, 8, VR, V_MF4>; def VI8MF4: VTypeInfo<vint8mf4_t, vbool32_t, 8, VR, V_MF4>;
def VI8MF2: VTypeInfo<vint8mf2_t, vbool16_t, 8, VR, V_MF2>; def VI8MF2: VTypeInfo<vint8mf2_t, vbool16_t, 8, VR, V_MF2>;
def VI8M1: VTypeInfo<vint8m1_t, vbool8_t, 8, VR, V_M1>;
def VI16MF4: VTypeInfo<vint16mf4_t, vbool64_t, 16, VR, V_MF4>; def VI16MF4: VTypeInfo<vint16mf4_t, vbool64_t, 16, VR, V_MF4>;
def VI16MF2: VTypeInfo<vint16mf2_t, vbool32_t, 16, VR, V_MF2>; def VI16MF2: VTypeInfo<vint16mf2_t, vbool32_t, 16, VR, V_MF2>;
def VI16M1: VTypeInfo<vint16m1_t, vbool16_t, 16, VR, V_M1>;
def VI32MF2: VTypeInfo<vint32mf2_t, vbool64_t, 32, VR, V_MF2>; def VI32MF2: VTypeInfo<vint32mf2_t, vbool64_t, 32, VR, V_MF2>;
}
def VI8M1: VTypeInfo<vint8m1_t, vbool8_t, 8, VR, V_M1>;
def VI16M1: VTypeInfo<vint16m1_t, vbool16_t, 16, VR, V_M1>;
def VI32M1: VTypeInfo<vint32m1_t, vbool32_t, 32, VR, V_M1>; def VI32M1: VTypeInfo<vint32m1_t, vbool32_t, 32, VR, V_M1>;
def VI64M1: VTypeInfo<vint64m1_t, vbool64_t, 64, VR, V_M1>; def VI64M1: VTypeInfo<vint64m1_t, vbool64_t, 64, VR, V_M1>;
} }
defset list<GroupVTypeInfo> GroupIntegerVectors = { defset list<GroupVTypeInfo> GroupIntegerVectors = {
def VI8M2: GroupVTypeInfo<vint8m2_t, vint8m1_t, vbool4_t, 8, VRM2, V_M2>; def VI8M2: GroupVTypeInfo<vint8m2_t, vint8m1_t, vbool4_t, 8, VRM2, V_M2>;
def VI8M4: GroupVTypeInfo<vint8m4_t, vint8m1_t, vbool2_t, 8, VRM4, V_M4>; def VI8M4: GroupVTypeInfo<vint8m4_t, vint8m1_t, vbool2_t, 8, VRM4, V_M4>;
def VI8M8: GroupVTypeInfo<vint8m8_t, vint8m1_t, vbool1_t, 8, VRM8, V_M8>; def VI8M8: GroupVTypeInfo<vint8m8_t, vint8m1_t, vbool1_t, 8, VRM8, V_M8>;
def VI16M2: GroupVTypeInfo<vint16m2_t,vint16m1_t,vbool8_t, 16,VRM2, V_M2>; def VI16M2: GroupVTypeInfo<vint16m2_t,vint16m1_t,vbool8_t, 16,VRM2, V_M2>;
def VI16M4: GroupVTypeInfo<vint16m4_t,vint16m1_t,vbool4_t, 16,VRM4, V_M4>; def VI16M4: GroupVTypeInfo<vint16m4_t,vint16m1_t,vbool4_t, 16,VRM4, V_M4>;
def VI16M8: GroupVTypeInfo<vint16m8_t,vint16m1_t,vbool2_t, 16,VRM8, V_M8>; def VI16M8: GroupVTypeInfo<vint16m8_t,vint16m1_t,vbool2_t, 16,VRM8, V_M8>;
def VI32M2: GroupVTypeInfo<vint32m2_t,vint32m1_t,vbool16_t,32,VRM2, V_M2>; def VI32M2: GroupVTypeInfo<vint32m2_t,vint32m1_t,vbool16_t,32,VRM2, V_M2>;
def VI32M4: GroupVTypeInfo<vint32m4_t,vint32m1_t,vbool8_t, 32,VRM4, V_M4>; def VI32M4: GroupVTypeInfo<vint32m4_t,vint32m1_t,vbool8_t, 32,VRM4, V_M4>;
def VI32M8: GroupVTypeInfo<vint32m8_t,vint32m1_t,vbool4_t, 32,VRM8, V_M8>; def VI32M8: GroupVTypeInfo<vint32m8_t,vint32m1_t,vbool4_t, 32,VRM8, V_M8>;
def VI64M2: GroupVTypeInfo<vint64m2_t,vint64m1_t,vbool32_t,64,VRM2, V_M2>; def VI64M2: GroupVTypeInfo<vint64m2_t,vint64m1_t,vbool32_t,64,VRM2, V_M2>;
def VI64M4: GroupVTypeInfo<vint64m4_t,vint64m1_t,vbool16_t,64,VRM4, V_M4>; def VI64M4: GroupVTypeInfo<vint64m4_t,vint64m1_t,vbool16_t,64,VRM4, V_M4>;
def VI64M8: GroupVTypeInfo<vint64m8_t,vint64m1_t,vbool8_t, 64,VRM8, V_M8>; def VI64M8: GroupVTypeInfo<vint64m8_t,vint64m1_t,vbool8_t, 64,VRM8, V_M8>;
} }
} }
defset list<VTypeInfo> AllFloatVectors = { defset list<VTypeInfo> AllFloatVectors = {
defset list<VTypeInfo> NoGroupFloatVectors = { defset list<VTypeInfo> NoGroupFloatVectors = {
defset list<VTypeInfo> FractionalGroupFloatVectors = {
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def VF16MF4: VTypeInfo<vfloat16mf4_t, vbool64_t, 16, VR, V_MF4, f16, FPR16>; def VF16MF4: VTypeInfo<vfloat16mf4_t, vbool64_t, 16, VR, V_MF4, f16, FPR16>;
def VF16MF2: VTypeInfo<vfloat16mf2_t, vbool32_t, 16, VR, V_MF2, f16, FPR16>; def VF16MF2: VTypeInfo<vfloat16mf2_t, vbool32_t, 16, VR, V_MF2, f16, FPR16>;
def VF16M1: VTypeInfo<vfloat16m1_t, vbool16_t, 16, VR, V_M1, f16, FPR16>;
def VF32MF2: VTypeInfo<vfloat32mf2_t,vbool64_t, 32, VR, V_MF2, f32, FPR32>; def VF32MF2: VTypeInfo<vfloat32mf2_t,vbool64_t, 32, VR, V_MF2, f32, FPR32>;
}
def VF16M1: VTypeInfo<vfloat16m1_t, vbool16_t, 16, VR, V_M1, f16, FPR16>;
def VF32M1: VTypeInfo<vfloat32m1_t, vbool32_t, 32, VR, V_M1, f32, FPR32>; def VF32M1: VTypeInfo<vfloat32m1_t, vbool32_t, 32, VR, V_M1, f32, FPR32>;
def VF64M1: VTypeInfo<vfloat64m1_t, vbool64_t, 64, VR, V_M1, f64, FPR64>; def VF64M1: VTypeInfo<vfloat64m1_t, vbool64_t, 64, VR, V_M1, f64, FPR64>;
} }
defset list<GroupVTypeInfo> GroupFloatVectors = { defset list<GroupVTypeInfo> GroupFloatVectors = {
def VF16M2: GroupVTypeInfo<vfloat16m2_t, vfloat16m1_t, vbool8_t, 16, def VF16M2: GroupVTypeInfo<vfloat16m2_t, vfloat16m1_t, vbool8_t, 16,
VRM2, V_M2, f16, FPR16>; VRM2, V_M2, f16, FPR16>;
def VF16M4: GroupVTypeInfo<vfloat16m4_t, vfloat16m1_t, vbool4_t, 16, def VF16M4: GroupVTypeInfo<vfloat16m4_t, vfloat16m1_t, vbool4_t, 16,
VRM4, V_M4, f16, FPR16>; VRM4, V_M4, f16, FPR16>;
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llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Linesmulticlass VPatUSLoadStoreSDNode<LLVMType type,
// Load // Load
def : Pat<(type (load RVVBaseAddr:$rs1)), def : Pat<(type (load RVVBaseAddr:$rs1)),
(load_instr RVVBaseAddr:$rs1, avl, sew)>; (load_instr RVVBaseAddr:$rs1, avl, sew)>;
// Store // Store
def : Pat<(store type:$rs2, RVVBaseAddr:$rs1), def : Pat<(store type:$rs2, RVVBaseAddr:$rs1),
(store_instr reg_class:$rs2, RVVBaseAddr:$rs1, avl, sew)>; (store_instr reg_class:$rs2, RVVBaseAddr:$rs1, avl, sew)>;
} }
multiclass VPatUSLoadStoreWholeVRSDNode<LLVMType type,
int sew,
LMULInfo vlmul,
VReg reg_class>
{
defvar load_instr =
!cond(!eq(vlmul.value, V_M1.value): !cast<Instruction>("VL1RE"#sew#"_V"),
!eq(vlmul.value, V_M2.value): !cast<Instruction>("VL2RE"#sew#"_V"),
!eq(vlmul.value, V_M4.value): !cast<Instruction>("VL4RE"#sew#"_V"),
!eq(vlmul.value, V_M8.value): !cast<Instruction>("VL8RE"#sew#"_V"));
defvar store_instr =
!cond(!eq(vlmul.value, V_M1.value): VS1R_V,
!eq(vlmul.value, V_M2.value): VS2R_V,
!eq(vlmul.value, V_M4.value): VS4R_V,
!eq(vlmul.value, V_M8.value): VS8R_V);
// Load
def : Pat<(type (load RVVBaseAddr:$rs1)),
(load_instr RVVBaseAddr:$rs1)>;
// Store
def : Pat<(store type:$rs2, RVVBaseAddr:$rs1),
(store_instr reg_class:$rs2, RVVBaseAddr:$rs1)>;
}
multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m> multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
{ {
defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#m.BX); defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#m.BX);
defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#m.BX); defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#m.BX);
// Load // Load
def : Pat<(m.Mask (load RVVBaseAddr:$rs1)), def : Pat<(m.Mask (load RVVBaseAddr:$rs1)),
(load_instr RVVBaseAddr:$rs1, m.AVL, m.SEW)>; (load_instr RVVBaseAddr:$rs1, m.AVL, m.SEW)>;
// Store // Store
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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Patterns. // Patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
// 7.4. Vector Unit-Stride Instructions // 7.4. Vector Unit-Stride Instructions
foreach vti = AllVectors in foreach vti = !listconcat(FractionalGroupIntegerVectors,
FractionalGroupFloatVectors) in
defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.SEW, vti.LMul, defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.SEW, vti.LMul,
vti.AVL, vti.RegClass>; vti.AVL, vti.RegClass>;
foreach vti = [VI8M1, VI16M1, VI32M1, VI64M1, VF16M1, VF32M1, VF64M1] in
defm "" : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.SEW, vti.LMul,
vti.RegClass>;
foreach vti = !listconcat(GroupIntegerVectors, GroupFloatVectors) in
defm "" : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.SEW, vti.LMul,
vti.RegClass>;
foreach mti = AllMasks in foreach mti = AllMasks in
defm "" : VPatUSLoadStoreMaskSDNode<mti>; defm "" : VPatUSLoadStoreMaskSDNode<mti>;
// 12.1. Vector Single-Width Integer Add and Subtract // 12.1. Vector Single-Width Integer Add and Subtract
defm "" : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">; defm "" : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
defm "" : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">; defm "" : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">;
// Handle VRSUB specially since it's the only integer binary op with reversed // Handle VRSUB specially since it's the only integer binary op with reversed
// pattern operands // pattern operands
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llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Linesbool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
auto FII = FixedCSRFIMap.find(Reg); auto FII = FixedCSRFIMap.find(Reg);
if (FII == FixedCSRFIMap.end()) if (FII == FixedCSRFIMap.end())
return false; return false;
FrameIdx = FII->second; FrameIdx = FII->second;
return true; return true;
} }
static bool isRVVWholeLoadStore(unsigned Opcode) {
switch (Opcode) {
default:
return false;
case RISCV::VS1R_V:
case RISCV::VS2R_V:
case RISCV::VS4R_V:
case RISCV::VS8R_V:
case RISCV::VL1RE8_V:
case RISCV::VL2RE8_V:
case RISCV::VL4RE8_V:
case RISCV::VL8RE8_V:
case RISCV::VL1RE16_V:
case RISCV::VL2RE16_V:
case RISCV::VL4RE16_V:
case RISCV::VL8RE16_V:
case RISCV::VL1RE32_V:
case RISCV::VL2RE32_V:
case RISCV::VL4RE32_V:
case RISCV::VL8RE32_V:
case RISCV::VL1RE64_V:
case RISCV::VL2RE64_V:
case RISCV::VL4RE64_V:
case RISCV::VL8RE64_V:
return true;
}
}
void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum, int SPAdj, unsigned FIOperandNum,
RegScavenger *RS) const { RegScavenger *RS) const {
assert(SPAdj == 0 && "Unexpected non-zero SPAdj value"); assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
MachineInstr &MI = *II; MachineInstr &MI = *II;
MachineFunction &MF = *MI.getParent()->getParent(); MachineFunction &MF = *MI.getParent()->getParent();
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo(); const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
DebugLoc DL = MI.getDebugLoc(); DebugLoc DL = MI.getDebugLoc();
int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
Register FrameReg; Register FrameReg;
StackOffset Offset = StackOffset Offset =
getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg); getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
const auto *RVVInfo = RISCVVPseudosTable::getPseudoInfo(MI.getOpcode()); bool isRVV = RISCVVPseudosTable::getPseudoInfo(MI.getOpcode()) ||
if (!RVVInfo) isRVVWholeLoadStore(MI.getOpcode());
if (!isRVV)
Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm()); Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
if (!isInt<32>(Offset.getFixed())) { if (!isInt<32>(Offset.getFixed())) {
report_fatal_error( report_fatal_error(
"Frame offsets outside of the signed 32-bit range not supported"); "Frame offsets outside of the signed 32-bit range not supported");
} }
MachineBasicBlock &MBB = *MI.getParent(); MachineBasicBlock &MBB = *MI.getParent();
Show All 11 Lines if (!isInt<12>(Offset.getFixed())) {
FrameReg = ScratchReg; FrameReg = ScratchReg;
FrameRegIsKill = true; FrameRegIsKill = true;
} }
if (!Offset.getScalable()) { if (!Offset.getScalable()) {
// Offset = (fixed offset, 0) // Offset = (fixed offset, 0)
MI.getOperand(FIOperandNum) MI.getOperand(FIOperandNum)
.ChangeToRegister(FrameReg, false, false, FrameRegIsKill); .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
if (!RVVInfo) if (!isRVV)
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed()); MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
else { else {
if (Offset.getFixed()) { if (Offset.getFixed()) {
Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg) BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg)
.addReg(FrameReg, getKillRegState(FrameRegIsKill)) .addReg(FrameReg, getKillRegState(FrameRegIsKill))
.addImm(Offset.getFixed()); .addImm(Offset.getFixed());
MI.getOperand(FIOperandNum) MI.getOperand(FIOperandNum)
Show All 14 Lines Register FactorRegister =
TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue); TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);
// 2. Calculate address: FrameReg + result of multiply // 2. Calculate address: FrameReg + result of multiply
Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass); Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
BuildMI(MBB, II, DL, TII->get(Opc), VL) BuildMI(MBB, II, DL, TII->get(Opc), VL)
.addReg(FrameReg, getKillRegState(FrameRegIsKill)) .addReg(FrameReg, getKillRegState(FrameRegIsKill))
.addReg(FactorRegister, RegState::Kill); .addReg(FactorRegister, RegState::Kill);
if (RVVInfo && Offset.getFixed()) { if (isRVV && Offset.getFixed()) {
// Scalable load/store has no immediate argument. We need to add the // Scalable load/store has no immediate argument. We need to add the
// fixed part into the load/store base address. // fixed part into the load/store base address.
BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VL) BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VL)
.addReg(VL) .addReg(VL)
.addImm(Offset.getFixed()); .addImm(Offset.getFixed());
} }
// 3. Replace address register with calculated address register // 3. Replace address register with calculated address register
MI.getOperand(FIOperandNum).ChangeToRegister(VL, false, false, true); MI.getOperand(FIOperandNum).ChangeToRegister(VL, false, false, true);
if (!RVVInfo) if (!isRVV)
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed()); MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
} }
} }
Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = getFrameLowering(MF); const TargetFrameLowering *TFI = getFrameLowering(MF);
return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2; return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
} }
Show All 22 Lines

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \
; RUN: | FileCheck %s -check-prefix=RV64IV ; RUN: | FileCheck %s -check-prefix=RV64IV
define <vscale x 1 x i64> @access_fixed_object(i64 *%val) { define <vscale x 1 x i64> @access_fixed_object(i64 *%val) {
; RV64IV-LABEL: access_fixed_object: ; RV64IV-LABEL: access_fixed_object:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -528 ; RV64IV-NEXT: addi sp, sp, -528
; RV64IV-NEXT: .cfi_def_cfa_offset 528 ; RV64IV-NEXT: .cfi_def_cfa_offset 528
; RV64IV-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; RV64IV-NEXT: addi a1, sp, 8 ; RV64IV-NEXT: addi a1, sp, 8
; RV64IV-NEXT: vle64.v v8, (a1) ; RV64IV-NEXT: vl1re64.v v8, (a1)
; RV64IV-NEXT: ld a1, 520(sp) ; RV64IV-NEXT: ld a1, 520(sp)
; RV64IV-NEXT: sd a1, 0(a0) ; RV64IV-NEXT: sd a1, 0(a0)
; RV64IV-NEXT: addi sp, sp, 528 ; RV64IV-NEXT: addi sp, sp, 528
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local = alloca i64 %local = alloca i64
%array = alloca [64 x i64] %array = alloca [64 x i64]
%vptr = bitcast [64 x i64]* %array to <vscale x 1 x i64>* %vptr = bitcast [64 x i64]* %array to <vscale x 1 x i64>*
%v = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vptr %v = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vptr
Show All 9 Lines
define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) { define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) {
; RV64IV-LABEL: access_fixed_and_vector_objects: ; RV64IV-LABEL: access_fixed_and_vector_objects:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -528 ; RV64IV-NEXT: addi sp, sp, -528
; RV64IV-NEXT: .cfi_def_cfa_offset 528 ; RV64IV-NEXT: .cfi_def_cfa_offset 528
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: addi a0, a0, 8 ; RV64IV-NEXT: addi a0, a0, 8
; RV64IV-NEXT: vle64.v v25, (a0) ; RV64IV-NEXT: vl1re64.v v25, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: ld a0, 520(a0) ; RV64IV-NEXT: ld a0, 520(a0)
; RV64IV-NEXT: vle64.v v26, (sp) ; RV64IV-NEXT: vl1re64.v v26, (sp)
; RV64IV-NEXT: vsetvli a0, a0, e64,m1,ta,mu ; RV64IV-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; RV64IV-NEXT: vadd.vv v8, v25, v26 ; RV64IV-NEXT: vadd.vv v8, v25, v26
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add sp, sp, a0 ; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: addi sp, sp, 528 ; RV64IV-NEXT: addi sp, sp, 528
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local = alloca i64 %local = alloca i64
%vector = alloca <vscale x 1 x i64> %vector = alloca <vscale x 1 x i64>
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llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll

Show All 14 Lines
{ {
%va = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pa %va = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pa
%vb = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pb %vb = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pb
%vc = add <vscale x 1 x i64> %va, %vb %vc = add <vscale x 1 x i64> %va, %vb
store <vscale x 1 x i64> %vc, <vscale x 1 x i64> *%pc store <vscale x 1 x i64> %vc, <vscale x 1 x i64> *%pc
ret void ret void
} }
; PRE-INSERTER: %3:vr = PseudoVLE64_V_M1 %1, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) ; PRE-INSERTER: %3:vr = VL1RE64_V %1 :: (load unknown-size from %ir.pa, align 8)
; PRE-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $x0, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8) ; PRE-INSERTER: %4:vr = VL1RE64_V %2 :: (load unknown-size from %ir.pb, align 8)
; PRE-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $x0, 64, implicit $vl, implicit $vtype ; PRE-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $x0, 64, implicit $vl, implicit $vtype
; PRE-INSERTER: PseudoVSE64_V_M1 killed %5, %0, $x0, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) ; PRE-INSERTER: VS1R_V killed %5, %0 :: (store unknown-size into %ir.pc, align 8)
; POST-INSERTER: %3:vr = VL1RE64_V %1 :: (load unknown-size from %ir.pa, align 8)
; POST-INSERTER: %4:vr = VL1RE64_V %2 :: (load unknown-size from %ir.pb, align 8)
; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
; POST-INSERTER: %3:vr = PseudoVLE64_V_M1 %1, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
; POST-INSERTER: dead %7:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
; POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8)
; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype
; POST-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $noreg, -1, implicit $vl, implicit $vtype ; POST-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $noreg, -1, implicit $vl, implicit $vtype
; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: VS1R_V killed %5, %0 :: (store unknown-size into %ir.pc, align 8)
; POST-INSERTER: PseudoVSE64_V_M1 killed %5, %0, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8)

llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \ ; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \ ; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
define void @vadd_vint16m1(<vscale x 4 x i16> *%pc, <vscale x 4 x i16> *%pa, <vscale x 4 x i16> *%pb) nounwind { define void @vadd_vint16m1(<vscale x 4 x i16> *%pc, <vscale x 4 x i16> *%pa, <vscale x 4 x i16> *%pb) nounwind {
; CHECK-LABEL: vadd_vint16m1: ; CHECK-LABEL: vadd_vint16m1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e16,m1,ta,mu ; CHECK-NEXT: vl1re16.v v25, (a1)
; CHECK-NEXT: vle16.v v25, (a1) ; CHECK-NEXT: vl1re16.v v26, (a2)
; CHECK-NEXT: vle16.v v26, (a2) ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: vse16.v v25, (a0) ; CHECK-NEXT: vs1r.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pa %va = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pa
%vb = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pb %vb = load <vscale x 4 x i16>, <vscale x 4 x i16>* %pb
%vc = add <vscale x 4 x i16> %va, %vb %vc = add <vscale x 4 x i16> %va, %vb
store <vscale x 4 x i16> %vc, <vscale x 4 x i16> *%pc store <vscale x 4 x i16> %vc, <vscale x 4 x i16> *%pc
ret void ret void
} }
define void @vadd_vint16m2(<vscale x 8 x i16> *%pc, <vscale x 8 x i16> *%pa, <vscale x 8 x i16> *%pb) nounwind { define void @vadd_vint16m2(<vscale x 8 x i16> *%pc, <vscale x 8 x i16> *%pa, <vscale x 8 x i16> *%pb) nounwind {
; CHECK-LABEL: vadd_vint16m2: ; CHECK-LABEL: vadd_vint16m2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu ; CHECK-NEXT: vl2re16.v v26, (a1)
; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vl2re16.v v28, (a2)
; CHECK-NEXT: vle16.v v28, (a2) ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vadd.vv v26, v26, v28 ; CHECK-NEXT: vadd.vv v26, v26, v28
; CHECK-NEXT: vse16.v v26, (a0) ; CHECK-NEXT: vs2r.v v26, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pa %va = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pa
%vb = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pb %vb = load <vscale x 8 x i16>, <vscale x 8 x i16>* %pb
%vc = add <vscale x 8 x i16> %va, %vb %vc = add <vscale x 8 x i16> %va, %vb
store <vscale x 8 x i16> %vc, <vscale x 8 x i16> *%pc store <vscale x 8 x i16> %vc, <vscale x 8 x i16> *%pc
ret void ret void
} }
define void @vadd_vint16m4(<vscale x 16 x i16> *%pc, <vscale x 16 x i16> *%pa, <vscale x 16 x i16> *%pb) nounwind { define void @vadd_vint16m4(<vscale x 16 x i16> *%pc, <vscale x 16 x i16> *%pa, <vscale x 16 x i16> *%pb) nounwind {
; CHECK-LABEL: vadd_vint16m4: ; CHECK-LABEL: vadd_vint16m4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a1)
; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: vl4re16.v v8, (a2)
; CHECK-NEXT: vle16.v v8, (a2) ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vadd.vv v28, v28, v8 ; CHECK-NEXT: vadd.vv v28, v28, v8
; CHECK-NEXT: vse16.v v28, (a0) ; CHECK-NEXT: vs4r.v v28, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pa %va = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pa
%vb = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pb %vb = load <vscale x 16 x i16>, <vscale x 16 x i16>* %pb
%vc = add <vscale x 16 x i16> %va, %vb %vc = add <vscale x 16 x i16> %va, %vb
store <vscale x 16 x i16> %vc, <vscale x 16 x i16> *%pc store <vscale x 16 x i16> %vc, <vscale x 16 x i16> *%pc
ret void ret void
} }
define void @vadd_vint16m8(<vscale x 32 x i16> *%pc, <vscale x 32 x i16> *%pa, <vscale x 32 x i16> *%pb) nounwind { define void @vadd_vint16m8(<vscale x 32 x i16> *%pc, <vscale x 32 x i16> *%pa, <vscale x 32 x i16> *%pb) nounwind {
; CHECK-LABEL: vadd_vint16m8: ; CHECK-LABEL: vadd_vint16m8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v8, (a1)
; CHECK-NEXT: vle16.v v8, (a1) ; CHECK-NEXT: vl8re16.v v16, (a2)
; CHECK-NEXT: vle16.v v16, (a2) ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 32 x i16>, <vscale x 32 x i16>* %pa %va = load <vscale x 32 x i16>, <vscale x 32 x i16>* %pa
%vb = load <vscale x 32 x i16>, <vscale x 32 x i16>* %pb %vb = load <vscale x 32 x i16>, <vscale x 32 x i16>* %pb
%vc = add <vscale x 32 x i16> %va, %vb %vc = add <vscale x 32 x i16> %va, %vb
store <vscale x 32 x i16> %vc, <vscale x 32 x i16> *%pc store <vscale x 32 x i16> %vc, <vscale x 32 x i16> *%pc
ret void ret void
} }
Show All 31 Lines

llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \ ; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \ ; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
define void @vadd_vint32m1(<vscale x 2 x i32> *%pc, <vscale x 2 x i32> *%pa, <vscale x 2 x i32> *%pb) nounwind { define void @vadd_vint32m1(<vscale x 2 x i32> *%pc, <vscale x 2 x i32> *%pa, <vscale x 2 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m1: ; CHECK-LABEL: vadd_vint32m1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e32,m1,ta,mu ; CHECK-NEXT: vl1re32.v v25, (a1)
; CHECK-NEXT: vle32.v v25, (a1) ; CHECK-NEXT: vl1re32.v v26, (a2)
; CHECK-NEXT: vle32.v v26, (a2) ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: vse32.v v25, (a0) ; CHECK-NEXT: vs1r.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pa %va = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pa
%vb = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pb %vb = load <vscale x 2 x i32>, <vscale x 2 x i32>* %pb
%vc = add <vscale x 2 x i32> %va, %vb %vc = add <vscale x 2 x i32> %va, %vb
store <vscale x 2 x i32> %vc, <vscale x 2 x i32> *%pc store <vscale x 2 x i32> %vc, <vscale x 2 x i32> *%pc
ret void ret void
} }
define void @vadd_vint32m2(<vscale x 4 x i32> *%pc, <vscale x 4 x i32> *%pa, <vscale x 4 x i32> *%pb) nounwind { define void @vadd_vint32m2(<vscale x 4 x i32> *%pc, <vscale x 4 x i32> *%pa, <vscale x 4 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m2: ; CHECK-LABEL: vadd_vint32m2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e32,m2,ta,mu ; CHECK-NEXT: vl2re32.v v26, (a1)
; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vl2re32.v v28, (a2)
; CHECK-NEXT: vle32.v v28, (a2) ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vadd.vv v26, v26, v28 ; CHECK-NEXT: vadd.vv v26, v26, v28
; CHECK-NEXT: vse32.v v26, (a0) ; CHECK-NEXT: vs2r.v v26, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pa %va = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pa
%vb = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pb %vb = load <vscale x 4 x i32>, <vscale x 4 x i32>* %pb
%vc = add <vscale x 4 x i32> %va, %vb %vc = add <vscale x 4 x i32> %va, %vb
store <vscale x 4 x i32> %vc, <vscale x 4 x i32> *%pc store <vscale x 4 x i32> %vc, <vscale x 4 x i32> *%pc
ret void ret void
} }
define void @vadd_vint32m4(<vscale x 8 x i32> *%pc, <vscale x 8 x i32> *%pa, <vscale x 8 x i32> *%pb) nounwind { define void @vadd_vint32m4(<vscale x 8 x i32> *%pc, <vscale x 8 x i32> *%pa, <vscale x 8 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m4: ; CHECK-LABEL: vadd_vint32m4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu ; CHECK-NEXT: vl4re32.v v28, (a1)
; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: vl4re32.v v8, (a2)
; CHECK-NEXT: vle32.v v8, (a2) ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vadd.vv v28, v28, v8 ; CHECK-NEXT: vadd.vv v28, v28, v8
; CHECK-NEXT: vse32.v v28, (a0) ; CHECK-NEXT: vs4r.v v28, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pa %va = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pa
%vb = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pb %vb = load <vscale x 8 x i32>, <vscale x 8 x i32>* %pb
%vc = add <vscale x 8 x i32> %va, %vb %vc = add <vscale x 8 x i32> %va, %vb
store <vscale x 8 x i32> %vc, <vscale x 8 x i32> *%pc store <vscale x 8 x i32> %vc, <vscale x 8 x i32> *%pc
ret void ret void
} }
define void @vadd_vint32m8(<vscale x 16 x i32> *%pc, <vscale x 16 x i32> *%pa, <vscale x 16 x i32> *%pb) nounwind { define void @vadd_vint32m8(<vscale x 16 x i32> *%pc, <vscale x 16 x i32> *%pa, <vscale x 16 x i32> *%pb) nounwind {
; CHECK-LABEL: vadd_vint32m8: ; CHECK-LABEL: vadd_vint32m8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v8, (a1)
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vl8re32.v v16, (a2)
; CHECK-NEXT: vle32.v v16, (a2) ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 16 x i32>, <vscale x 16 x i32>* %pa %va = load <vscale x 16 x i32>, <vscale x 16 x i32>* %pa
%vb = load <vscale x 16 x i32>, <vscale x 16 x i32>* %pb %vb = load <vscale x 16 x i32>, <vscale x 16 x i32>* %pb
%vc = add <vscale x 16 x i32> %va, %vb %vc = add <vscale x 16 x i32> %va, %vb
store <vscale x 16 x i32> %vc, <vscale x 16 x i32> *%pc store <vscale x 16 x i32> %vc, <vscale x 16 x i32> *%pc
ret void ret void
} }
Show All 15 Lines

llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \ ; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \ ; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
define void @vadd_vint64m1(<vscale x 1 x i64> *%pc, <vscale x 1 x i64> *%pa, <vscale x 1 x i64> *%pb) nounwind { define void @vadd_vint64m1(<vscale x 1 x i64> *%pc, <vscale x 1 x i64> *%pa, <vscale x 1 x i64> *%pb) nounwind {
; CHECK-LABEL: vadd_vint64m1: ; CHECK-LABEL: vadd_vint64m1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e64,m1,ta,mu ; CHECK-NEXT: vl1re64.v v25, (a1)
; CHECK-NEXT: vle64.v v25, (a1) ; CHECK-NEXT: vl1re64.v v26, (a2)
; CHECK-NEXT: vle64.v v26, (a2) ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: vse64.v v25, (a0) ; CHECK-NEXT: vs1r.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pa %va = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pa
%vb = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pb %vb = load <vscale x 1 x i64>, <vscale x 1 x i64>* %pb
%vc = add <vscale x 1 x i64> %va, %vb %vc = add <vscale x 1 x i64> %va, %vb
store <vscale x 1 x i64> %vc, <vscale x 1 x i64> *%pc store <vscale x 1 x i64> %vc, <vscale x 1 x i64> *%pc
ret void ret void
} }
define void @vadd_vint64m2(<vscale x 2 x i64> *%pc, <vscale x 2 x i64> *%pa, <vscale x 2 x i64> *%pb) nounwind { define void @vadd_vint64m2(<vscale x 2 x i64> *%pc, <vscale x 2 x i64> *%pa, <vscale x 2 x i64> *%pb) nounwind {
; CHECK-LABEL: vadd_vint64m2: ; CHECK-LABEL: vadd_vint64m2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e64,m2,ta,mu ; CHECK-NEXT: vl2re64.v v26, (a1)
; CHECK-NEXT: vle64.v v26, (a1) ; CHECK-NEXT: vl2re64.v v28, (a2)
; CHECK-NEXT: vle64.v v28, (a2) ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu
; CHECK-NEXT: vadd.vv v26, v26, v28 ; CHECK-NEXT: vadd.vv v26, v26, v28
; CHECK-NEXT: vse64.v v26, (a0) ; CHECK-NEXT: vs2r.v v26, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 2 x i64>, <vscale x 2 x i64>* %pa %va = load <vscale x 2 x i64>, <vscale x 2 x i64>* %pa
%vb = load <vscale x 2 x i64>, <vscale x 2 x i64>* %pb %vb = load <vscale x 2 x i64>, <vscale x 2 x i64>* %pb
%vc = add <vscale x 2 x i64> %va, %vb %vc = add <vscale x 2 x i64> %va, %vb
store <vscale x 2 x i64> %vc, <vscale x 2 x i64> *%pc store <vscale x 2 x i64> %vc, <vscale x 2 x i64> *%pc
ret void ret void
} }
define void @vadd_vint64m4(<vscale x 4 x i64> *%pc, <vscale x 4 x i64> *%pa, <vscale x 4 x i64> *%pb) nounwind { define void @vadd_vint64m4(<vscale x 4 x i64> *%pc, <vscale x 4 x i64> *%pa, <vscale x 4 x i64> *%pb) nounwind {
; CHECK-LABEL: vadd_vint64m4: ; CHECK-LABEL: vadd_vint64m4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e64,m4,ta,mu ; CHECK-NEXT: vl4re64.v v28, (a1)
; CHECK-NEXT: vle64.v v28, (a1) ; CHECK-NEXT: vl4re64.v v8, (a2)
; CHECK-NEXT: vle64.v v8, (a2) ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu
; CHECK-NEXT: vadd.vv v28, v28, v8 ; CHECK-NEXT: vadd.vv v28, v28, v8
; CHECK-NEXT: vse64.v v28, (a0) ; CHECK-NEXT: vs4r.v v28, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 4 x i64>, <vscale x 4 x i64>* %pa %va = load <vscale x 4 x i64>, <vscale x 4 x i64>* %pa
%vb = load <vscale x 4 x i64>, <vscale x 4 x i64>* %pb %vb = load <vscale x 4 x i64>, <vscale x 4 x i64>* %pb
%vc = add <vscale x 4 x i64> %va, %vb %vc = add <vscale x 4 x i64> %va, %vb
store <vscale x 4 x i64> %vc, <vscale x 4 x i64> *%pc store <vscale x 4 x i64> %vc, <vscale x 4 x i64> *%pc
ret void ret void
} }
define void @vadd_vint64m8(<vscale x 8 x i64> *%pc, <vscale x 8 x i64> *%pa, <vscale x 8 x i64> *%pb) nounwind { define void @vadd_vint64m8(<vscale x 8 x i64> *%pc, <vscale x 8 x i64> *%pa, <vscale x 8 x i64> *%pb) nounwind {
; CHECK-LABEL: vadd_vint64m8: ; CHECK-LABEL: vadd_vint64m8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v8, (a1)
; CHECK-NEXT: vle64.v v8, (a1) ; CHECK-NEXT: vl8re64.v v16, (a2)
; CHECK-NEXT: vle64.v v16, (a2) ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 8 x i64>, <vscale x 8 x i64>* %pa %va = load <vscale x 8 x i64>, <vscale x 8 x i64>* %pa
%vb = load <vscale x 8 x i64>, <vscale x 8 x i64>* %pb %vb = load <vscale x 8 x i64>, <vscale x 8 x i64>* %pb
%vc = add <vscale x 8 x i64> %va, %vb %vc = add <vscale x 8 x i64> %va, %vb
store <vscale x 8 x i64> %vc, <vscale x 8 x i64> *%pc store <vscale x 8 x i64> %vc, <vscale x 8 x i64> *%pc
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \ ; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \ ; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \
; RUN: -verify-machineinstrs | FileCheck %s ; RUN: -verify-machineinstrs | FileCheck %s
define void @vadd_vint8m1(<vscale x 8 x i8> *%pc, <vscale x 8 x i8> *%pa, <vscale x 8 x i8> *%pb) nounwind { define void @vadd_vint8m1(<vscale x 8 x i8> *%pc, <vscale x 8 x i8> *%pa, <vscale x 8 x i8> *%pb) nounwind {
; CHECK-LABEL: vadd_vint8m1: ; CHECK-LABEL: vadd_vint8m1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu ; CHECK-NEXT: vl1r.v v25, (a1)
; CHECK-NEXT: vle8.v v25, (a1) ; CHECK-NEXT: vl1r.v v26, (a2)
; CHECK-NEXT: vle8.v v26, (a2) ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: vse8.v v25, (a0) ; CHECK-NEXT: vs1r.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 8 x i8>, <vscale x 8 x i8>* %pa %va = load <vscale x 8 x i8>, <vscale x 8 x i8>* %pa
%vb = load <vscale x 8 x i8>, <vscale x 8 x i8>* %pb %vb = load <vscale x 8 x i8>, <vscale x 8 x i8>* %pb
%vc = add <vscale x 8 x i8> %va, %vb %vc = add <vscale x 8 x i8> %va, %vb
store <vscale x 8 x i8> %vc, <vscale x 8 x i8> *%pc store <vscale x 8 x i8> %vc, <vscale x 8 x i8> *%pc
ret void ret void
} }
define void @vadd_vint8m2(<vscale x 16 x i8> *%pc, <vscale x 16 x i8> *%pa, <vscale x 16 x i8> *%pb) nounwind { define void @vadd_vint8m2(<vscale x 16 x i8> *%pc, <vscale x 16 x i8> *%pa, <vscale x 16 x i8> *%pb) nounwind {
; CHECK-LABEL: vadd_vint8m2: ; CHECK-LABEL: vadd_vint8m2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu ; CHECK-NEXT: vl2r.v v26, (a1)
; CHECK-NEXT: vle8.v v26, (a1) ; CHECK-NEXT: vl2r.v v28, (a2)
; CHECK-NEXT: vle8.v v28, (a2) ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vadd.vv v26, v26, v28 ; CHECK-NEXT: vadd.vv v26, v26, v28
; CHECK-NEXT: vse8.v v26, (a0) ; CHECK-NEXT: vs2r.v v26, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 16 x i8>, <vscale x 16 x i8>* %pa %va = load <vscale x 16 x i8>, <vscale x 16 x i8>* %pa
%vb = load <vscale x 16 x i8>, <vscale x 16 x i8>* %pb %vb = load <vscale x 16 x i8>, <vscale x 16 x i8>* %pb
%vc = add <vscale x 16 x i8> %va, %vb %vc = add <vscale x 16 x i8> %va, %vb
store <vscale x 16 x i8> %vc, <vscale x 16 x i8> *%pc store <vscale x 16 x i8> %vc, <vscale x 16 x i8> *%pc
ret void ret void
} }
define void @vadd_vint8m4(<vscale x 32 x i8> *%pc, <vscale x 32 x i8> *%pa, <vscale x 32 x i8> *%pb) nounwind { define void @vadd_vint8m4(<vscale x 32 x i8> *%pc, <vscale x 32 x i8> *%pa, <vscale x 32 x i8> *%pb) nounwind {
; CHECK-LABEL: vadd_vint8m4: ; CHECK-LABEL: vadd_vint8m4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu ; CHECK-NEXT: vl4r.v v28, (a1)
; CHECK-NEXT: vle8.v v28, (a1) ; CHECK-NEXT: vl4r.v v8, (a2)
; CHECK-NEXT: vle8.v v8, (a2) ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vadd.vv v28, v28, v8 ; CHECK-NEXT: vadd.vv v28, v28, v8
; CHECK-NEXT: vse8.v v28, (a0) ; CHECK-NEXT: vs4r.v v28, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 32 x i8>, <vscale x 32 x i8>* %pa %va = load <vscale x 32 x i8>, <vscale x 32 x i8>* %pa
%vb = load <vscale x 32 x i8>, <vscale x 32 x i8>* %pb %vb = load <vscale x 32 x i8>, <vscale x 32 x i8>* %pb
%vc = add <vscale x 32 x i8> %va, %vb %vc = add <vscale x 32 x i8> %va, %vb
store <vscale x 32 x i8> %vc, <vscale x 32 x i8> *%pc store <vscale x 32 x i8> %vc, <vscale x 32 x i8> *%pc
ret void ret void
} }
define void @vadd_vint8m8(<vscale x 64 x i8> *%pc, <vscale x 64 x i8> *%pa, <vscale x 64 x i8> *%pb) nounwind { define void @vadd_vint8m8(<vscale x 64 x i8> *%pc, <vscale x 64 x i8> *%pa, <vscale x 64 x i8> *%pb) nounwind {
; CHECK-LABEL: vadd_vint8m8: ; CHECK-LABEL: vadd_vint8m8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8r.v v8, (a1)
; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vl8r.v v16, (a2)
; CHECK-NEXT: vle8.v v16, (a2) ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%va = load <vscale x 64 x i8>, <vscale x 64 x i8>* %pa %va = load <vscale x 64 x i8>, <vscale x 64 x i8>* %pa
%vb = load <vscale x 64 x i8>, <vscale x 64 x i8>* %pb %vb = load <vscale x 64 x i8>, <vscale x 64 x i8>* %pb
%vc = add <vscale x 64 x i8> %va, %vb %vc = add <vscale x 64 x i8> %va, %vb
store <vscale x 64 x i8> %vc, <vscale x 64 x i8> *%pc store <vscale x 64 x i8> %vc, <vscale x 64 x i8> *%pc
ret void ret void
} }
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llvm/test/CodeGen/RISCV/rvv/localvar.ll

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define void @local_var_m1() { define void @local_var_m1() {
; RV64IV-LABEL: local_var_m1: ; RV64IV-LABEL: local_var_m1:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: .cfi_def_cfa_offset 0 ; RV64IV-NEXT: .cfi_def_cfa_offset 0
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: vle8.v v25, (a0) ; RV64IV-NEXT: vl1r.v v25, (a0)
; RV64IV-NEXT: vle8.v v25, (sp) ; RV64IV-NEXT: vl1r.v v25, (sp)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add sp, sp, a0 ; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local0 = alloca <vscale x 8 x i8> %local0 = alloca <vscale x 8 x i8>
%local1 = alloca <vscale x 8 x i8> %local1 = alloca <vscale x 8 x i8>
load volatile <vscale x 8 x i8>, <vscale x 8 x i8>* %local0 load volatile <vscale x 8 x i8>, <vscale x 8 x i8>* %local0
load volatile <vscale x 8 x i8>, <vscale x 8 x i8>* %local1 load volatile <vscale x 8 x i8>, <vscale x 8 x i8>* %local1
ret void ret void
} }
define void @local_var_m2() { define void @local_var_m2() {
; RV64IV-LABEL: local_var_m2: ; RV64IV-LABEL: local_var_m2:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: .cfi_def_cfa_offset 0 ; RV64IV-NEXT: .cfi_def_cfa_offset 0
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: vle8.v v26, (a0) ; RV64IV-NEXT: vl2r.v v26, (a0)
; RV64IV-NEXT: vle8.v v26, (sp) ; RV64IV-NEXT: vl2r.v v26, (sp)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: add sp, sp, a0 ; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local0 = alloca <vscale x 16 x i8> %local0 = alloca <vscale x 16 x i8>
%local1 = alloca <vscale x 16 x i8> %local1 = alloca <vscale x 16 x i8>
load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0 load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0
load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local1 load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local1
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; RV64IV-NEXT: .cfi_offset ra, -8 ; RV64IV-NEXT: .cfi_offset ra, -8
; RV64IV-NEXT: .cfi_offset s0, -16 ; RV64IV-NEXT: .cfi_offset s0, -16
; RV64IV-NEXT: addi s0, sp, 32 ; RV64IV-NEXT: addi s0, sp, 32
; RV64IV-NEXT: .cfi_def_cfa s0, 0 ; RV64IV-NEXT: .cfi_def_cfa s0, 0
; RV64IV-NEXT: andi sp, sp, -32 ; RV64IV-NEXT: andi sp, sp, -32
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 3 ; RV64IV-NEXT: slli a0, a0, 3
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: vle8.v v28, (a0) ; RV64IV-NEXT: vl4r.v v28, (a0)
; RV64IV-NEXT: vle8.v v28, (sp) ; RV64IV-NEXT: vl4r.v v28, (sp)
; RV64IV-NEXT: addi sp, s0, -32 ; RV64IV-NEXT: addi sp, s0, -32
; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 32 ; RV64IV-NEXT: addi sp, sp, 32
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local0 = alloca <vscale x 32 x i8> %local0 = alloca <vscale x 32 x i8>
%local1 = alloca <vscale x 32 x i8> %local1 = alloca <vscale x 32 x i8>
load volatile <vscale x 32 x i8>, <vscale x 32 x i8>* %local0 load volatile <vscale x 32 x i8>, <vscale x 32 x i8>* %local0
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; RV64IV-NEXT: .cfi_offset ra, -8 ; RV64IV-NEXT: .cfi_offset ra, -8
; RV64IV-NEXT: .cfi_offset s0, -16 ; RV64IV-NEXT: .cfi_offset s0, -16
; RV64IV-NEXT: addi s0, sp, 64 ; RV64IV-NEXT: addi s0, sp, 64
; RV64IV-NEXT: .cfi_def_cfa s0, 0 ; RV64IV-NEXT: .cfi_def_cfa s0, 0
; RV64IV-NEXT: andi sp, sp, -64 ; RV64IV-NEXT: andi sp, sp, -64
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 4 ; RV64IV-NEXT: slli a0, a0, 4
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: vsetvli a0, zero, e8,m8,ta,mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 3 ; RV64IV-NEXT: slli a0, a0, 3
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: vl8r.v v8, (a0)
; RV64IV-NEXT: vle8.v v8, (sp) ; RV64IV-NEXT: vl8r.v v8, (sp)
; RV64IV-NEXT: addi sp, s0, -64 ; RV64IV-NEXT: addi sp, s0, -64
; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 64 ; RV64IV-NEXT: addi sp, sp, 64
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local0 = alloca <vscale x 64 x i8> %local0 = alloca <vscale x 64 x i8>
%local1 = alloca <vscale x 64 x i8> %local1 = alloca <vscale x 64 x i8>
load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local0 load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local0
load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local1 load volatile <vscale x 64 x i8>, <vscale x 64 x i8>* %local1
ret void ret void
} }
define void @local_var_m2_mix_local_scalar() { define void @local_var_m2_mix_local_scalar() {
; RV64IV-LABEL: local_var_m2_mix_local_scalar: ; RV64IV-LABEL: local_var_m2_mix_local_scalar:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: addi sp, sp, -16 ; RV64IV-NEXT: addi sp, sp, -16
; RV64IV-NEXT: .cfi_def_cfa_offset 16 ; RV64IV-NEXT: .cfi_def_cfa_offset 16
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: lw a0, 12(a0) ; RV64IV-NEXT: lw a0, 12(a0)
; RV64IV-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: vle8.v v26, (a0) ; RV64IV-NEXT: vl2r.v v26, (a0)
; RV64IV-NEXT: vle8.v v26, (sp) ; RV64IV-NEXT: vl2r.v v26, (sp)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: lw a0, 8(a0) ; RV64IV-NEXT: lw a0, 8(a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: add sp, sp, a0 ; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: addi sp, sp, 16 ; RV64IV-NEXT: addi sp, sp, 16
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; RV64IV-NEXT: andi a0, a0, -16 ; RV64IV-NEXT: andi a0, a0, -16
; RV64IV-NEXT: sub a0, sp, a0 ; RV64IV-NEXT: sub a0, sp, a0
; RV64IV-NEXT: mv sp, a0 ; RV64IV-NEXT: mv sp, a0
; RV64IV-NEXT: csrr a1, vlenb ; RV64IV-NEXT: csrr a1, vlenb
; RV64IV-NEXT: slli a1, a1, 1 ; RV64IV-NEXT: slli a1, a1, 1
; RV64IV-NEXT: sub a1, s0, a1 ; RV64IV-NEXT: sub a1, s0, a1
; RV64IV-NEXT: addi a1, a1, -16 ; RV64IV-NEXT: addi a1, a1, -16
; RV64IV-NEXT: call notdead@plt ; RV64IV-NEXT: call notdead@plt
; RV64IV-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub a0, s0, a0 ; RV64IV-NEXT: sub a0, s0, a0
; RV64IV-NEXT: addi a0, a0, -16 ; RV64IV-NEXT: addi a0, a0, -16
; RV64IV-NEXT: vle8.v v26, (a0) ; RV64IV-NEXT: vl2r.v v26, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub a0, s0, a0 ; RV64IV-NEXT: sub a0, s0, a0
; RV64IV-NEXT: addi a0, a0, -16 ; RV64IV-NEXT: addi a0, a0, -16
; RV64IV-NEXT: vle8.v v26, (a0) ; RV64IV-NEXT: vl2r.v v26, (a0)
; RV64IV-NEXT: addi sp, s0, -16 ; RV64IV-NEXT: addi sp, s0, -16
; RV64IV-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 16 ; RV64IV-NEXT: addi sp, sp, 16
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%1 = alloca i8, i64 %n %1 = alloca i8, i64 %n
%2 = alloca <vscale x 16 x i8> %2 = alloca <vscale x 16 x i8>
%3 = alloca <vscale x 16 x i8> %3 = alloca <vscale x 16 x i8>
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; RV64IV-NEXT: mv sp, a0 ; RV64IV-NEXT: mv sp, a0
; RV64IV-NEXT: addi a1, s1, 128 ; RV64IV-NEXT: addi a1, s1, 128
; RV64IV-NEXT: csrr a2, vlenb ; RV64IV-NEXT: csrr a2, vlenb
; RV64IV-NEXT: slli a2, a2, 1 ; RV64IV-NEXT: slli a2, a2, 1
; RV64IV-NEXT: sub a2, s1, a2 ; RV64IV-NEXT: sub a2, s1, a2
; RV64IV-NEXT: mv a2, a2 ; RV64IV-NEXT: mv a2, a2
; RV64IV-NEXT: call notdead2@plt ; RV64IV-NEXT: call notdead2@plt
; RV64IV-NEXT: lw a0, 124(s1) ; RV64IV-NEXT: lw a0, 124(s1)
; RV64IV-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1 ; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: sub a0, s1, a0 ; RV64IV-NEXT: sub a0, s1, a0
; RV64IV-NEXT: vle8.v v26, (a0) ; RV64IV-NEXT: vl2r.v v26, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2 ; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub a0, s1, a0 ; RV64IV-NEXT: sub a0, s1, a0
; RV64IV-NEXT: vle8.v v26, (a0) ; RV64IV-NEXT: vl2r.v v26, (a0)
; RV64IV-NEXT: lw a0, 120(s1) ; RV64IV-NEXT: lw a0, 120(s1)
; RV64IV-NEXT: addi sp, s0, -256 ; RV64IV-NEXT: addi sp, s0, -256
; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 240(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 248(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 256 ; RV64IV-NEXT: addi sp, sp, 256
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%1 = alloca i8, i64 %n %1 = alloca i8, i64 %n
Show All 15 Lines

llvm/test/CodeGen/RISCV/rvv/memory-args.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v -O2 < %s \
; RUN: | FileCheck %s -check-prefix=RV64IV ; RUN: | FileCheck %s -check-prefix=RV64IV
declare <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8( declare <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
i64); i64);
define <vscale x 64 x i8> @callee(<vscale x 64 x i8> %arg0, <vscale x 64 x i8> %arg1, <vscale x 64 x i8> %arg2) { define <vscale x 64 x i8> @callee(<vscale x 64 x i8> %arg0, <vscale x 64 x i8> %arg1, <vscale x 64 x i8> %arg2) {
; RV64IV-LABEL: callee: ; RV64IV-LABEL: callee:
; RV64IV: # %bb.0: ; RV64IV: # %bb.0:
; RV64IV-NEXT: vsetvli a1, zero, e8,m8,ta,mu ; RV64IV-NEXT: vl8r.v v24, (a0)
; RV64IV-NEXT: vle8.v v24, (a0)
; RV64IV-NEXT: addi a0, zero, 1024 ; RV64IV-NEXT: addi a0, zero, 1024
; RV64IV-NEXT: vsetvli a0, a0, e8,m8,tu,mu ; RV64IV-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; RV64IV-NEXT: vmacc.vv v8, v16, v24 ; RV64IV-NEXT: vmacc.vv v8, v16, v24
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%ret = call <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8( %ret = call <vscale x 64 x i8> @llvm.riscv.vmacc.nxv64i8.nxv64i8(
<vscale x 64 x i8> %arg0, <vscale x 64 x i8> %arg0,
<vscale x 64 x i8> %arg1, <vscale x 64 x i8> %arg1,
<vscale x 64 x i8> %arg2, i64 1024) <vscale x 64 x i8> %arg2, i64 1024)
Show All 10 Lines
; RV64IV-NEXT: .cfi_offset ra, -8 ; RV64IV-NEXT: .cfi_offset ra, -8
; RV64IV-NEXT: .cfi_offset s0, -16 ; RV64IV-NEXT: .cfi_offset s0, -16
; RV64IV-NEXT: addi s0, sp, 64 ; RV64IV-NEXT: addi s0, sp, 64
; RV64IV-NEXT: .cfi_def_cfa s0, 0 ; RV64IV-NEXT: .cfi_def_cfa s0, 0
; RV64IV-NEXT: andi sp, sp, -64 ; RV64IV-NEXT: andi sp, sp, -64
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 5 ; RV64IV-NEXT: slli a0, a0, 5
; RV64IV-NEXT: sub sp, sp, a0 ; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: vsetvli a0, zero, e8,m8,ta,mu
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: addi a1, zero, 24 ; RV64IV-NEXT: addi a1, zero, 24
; RV64IV-NEXT: mul a0, a0, a1 ; RV64IV-NEXT: mul a0, a0, a1
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: vle8.v v8, (a0) ; RV64IV-NEXT: vl8r.v v8, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 4 ; RV64IV-NEXT: slli a0, a0, 4
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: vle8.v v16, (a0) ; RV64IV-NEXT: vl8r.v v16, (a0)
; RV64IV-NEXT: csrr a0, vlenb ; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 3 ; RV64IV-NEXT: slli a0, a0, 3
; RV64IV-NEXT: add a0, sp, a0 ; RV64IV-NEXT: add a0, sp, a0
; RV64IV-NEXT: vle8.v v24, (a0) ; RV64IV-NEXT: vl8r.v v24, (a0)
; RV64IV-NEXT: mv a0, sp ; RV64IV-NEXT: mv a0, sp
; RV64IV-NEXT: vse8.v v24, (sp) ; RV64IV-NEXT: vs8r.v v24, (sp)
; RV64IV-NEXT: call callee@plt ; RV64IV-NEXT: call callee@plt
; RV64IV-NEXT: addi sp, s0, -64 ; RV64IV-NEXT: addi sp, s0, -64
; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64IV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 64 ; RV64IV-NEXT: addi sp, sp, 64
; RV64IV-NEXT: ret ; RV64IV-NEXT: ret
%local0 = alloca <vscale x 64 x i8> %local0 = alloca <vscale x 64 x i8>
%local1 = alloca <vscale x 64 x i8> %local1 = alloca <vscale x 64 x i8>
Show All 9 Lines

llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vasub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vasub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vasub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vasub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vdiv.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vdiv.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vdiv.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vdivu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vdivu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vdivu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll

Show First 20 Lines • Show All 246 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 695 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfdiv.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfdiv.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfdiv.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfdiv.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfdiv.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfdiv.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfdiv.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfdiv.mask.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfdiv.mask.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfdiv.mask.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfdiv.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfdiv.mask.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfdiv.mask.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 695 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 16 x half> %vd ret <vscale x 16 x half> %vd
} }
declare <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>) declare <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>)
define <vscale x 32 x half> @vfmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) { define <vscale x 32 x half> @vfmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) {
; CHECK-LABEL: vfmadd_vv_nxv32f16: ; CHECK-LABEL: vfmadd_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu
; CHECK-NEXT: vfmadd.vv v16, v24, v8 ; CHECK-NEXT: vfmadd.vv v16, v24, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %vc, <vscale x 32 x half> %vb, <vscale x 32 x half> %va) %vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %vc, <vscale x 32 x half> %vb, <vscale x 32 x half> %va)
ret <vscale x 32 x half> %vd ret <vscale x 32 x half> %vd
} }
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x float> %vd ret <vscale x 8 x float> %vd
} }
declare <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>) declare <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>)
define <vscale x 16 x float> @vfmadd_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) { define <vscale x 16 x float> @vfmadd_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) {
; CHECK-LABEL: vfmadd_vv_nxv16f32: ; CHECK-LABEL: vfmadd_vv_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu
; CHECK-NEXT: vfmadd.vv v8, v24, v16 ; CHECK-NEXT: vfmadd.vv v8, v24, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %va, <vscale x 16 x float> %vb) %vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %va, <vscale x 16 x float> %vb)
ret <vscale x 16 x float> %vd ret <vscale x 16 x float> %vd
} }
define <vscale x 16 x float> @vfmadd_vf_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, float %c) { define <vscale x 16 x float> @vfmadd_vf_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, float %c) {
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 4 x double> %vd ret <vscale x 4 x double> %vd
} }
declare <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x double>) declare <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x double>)
define <vscale x 8 x double> @vfmadd_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) { define <vscale x 8 x double> @vfmadd_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) {
; CHECK-LABEL: vfmadd_vv_nxv8f64: ; CHECK-LABEL: vfmadd_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu
; CHECK-NEXT: vfmadd.vv v24, v16, v8 ; CHECK-NEXT: vfmadd.vv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %vc, <vscale x 8 x double> %va) %vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %vc, <vscale x 8 x double> %va)
ret <vscale x 8 x double> %vd ret <vscale x 8 x double> %vd
} }
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 695 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 695 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 16 x half> %vd ret <vscale x 16 x half> %vd
} }
declare <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>) declare <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>)
define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) { define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv32f16: ; CHECK-LABEL: vfmsub_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu
; CHECK-NEXT: vfmsub.vv v16, v24, v8 ; CHECK-NEXT: vfmsub.vv v16, v24, v8
; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = fneg <vscale x 32 x half> %va %neg = fneg <vscale x 32 x half> %va
%vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %vc, <vscale x 32 x half> %vb, <vscale x 32 x half> %neg) %vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %vc, <vscale x 32 x half> %vb, <vscale x 32 x half> %neg)
ret <vscale x 32 x half> %vd ret <vscale x 32 x half> %vd
} }
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x float> %vd ret <vscale x 8 x float> %vd
} }
declare <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>) declare <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>)
define <vscale x 16 x float> @vfmsub_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) { define <vscale x 16 x float> @vfmsub_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv16f32: ; CHECK-LABEL: vfmsub_vv_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu
; CHECK-NEXT: vfmsub.vv v8, v24, v16 ; CHECK-NEXT: vfmsub.vv v8, v24, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = fneg <vscale x 16 x float> %vb %neg = fneg <vscale x 16 x float> %vb
%vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %va, <vscale x 16 x float> %neg) %vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %va, <vscale x 16 x float> %neg)
ret <vscale x 16 x float> %vd ret <vscale x 16 x float> %vd
} }
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 4 x double> %vd ret <vscale x 4 x double> %vd
} }
declare <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x double>) declare <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x double>)
define <vscale x 8 x double> @vfmsub_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) { define <vscale x 8 x double> @vfmsub_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv8f64: ; CHECK-LABEL: vfmsub_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu
; CHECK-NEXT: vfmsub.vv v24, v16, v8 ; CHECK-NEXT: vfmsub.vv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = fneg <vscale x 8 x double> %va %neg = fneg <vscale x 8 x double> %va
%vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %vc, <vscale x 8 x double> %neg) %vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %vc, <vscale x 8 x double> %neg)
ret <vscale x 8 x double> %vd ret <vscale x 8 x double> %vd
} }
Show All 14 Lines

llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfmul.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmul.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfmul.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfmul.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmul.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfmul.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfmul.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmul.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfmul.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfmul.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmul.mask.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfmul.mask.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfmul.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmul.mask.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfmul.mask.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfmul.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmul.mask.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfmul.mask.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 695 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 16 x half> %vd ret <vscale x 16 x half> %vd
} }
declare <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>) declare <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>)
define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) { define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) {
; CHECK-LABEL: vfnmsub_vv_nxv32f16: ; CHECK-LABEL: vfnmsub_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu
; CHECK-NEXT: vfnmadd.vv v8, v24, v16 ; CHECK-NEXT: vfnmadd.vv v8, v24, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = fneg <vscale x 32 x half> %vc %neg = fneg <vscale x 32 x half> %vc
%neg2 = fneg <vscale x 32 x half> %vb %neg2 = fneg <vscale x 32 x half> %vb
%vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %neg, <vscale x 32 x half> %va, <vscale x 32 x half> %neg2) %vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %neg, <vscale x 32 x half> %va, <vscale x 32 x half> %neg2)
ret <vscale x 32 x half> %vd ret <vscale x 32 x half> %vd
} }
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x float> %vd ret <vscale x 8 x float> %vd
} }
declare <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>) declare <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>)
define <vscale x 16 x float> @vfnmsub_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) { define <vscale x 16 x float> @vfnmsub_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) {
; CHECK-LABEL: vfnmsub_vv_nxv16f32: ; CHECK-LABEL: vfnmsub_vv_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu
; CHECK-NEXT: vfnmadd.vv v24, v8, v16 ; CHECK-NEXT: vfnmadd.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = fneg <vscale x 16 x float> %va %neg = fneg <vscale x 16 x float> %va
%neg2 = fneg <vscale x 16 x float> %vb %neg2 = fneg <vscale x 16 x float> %vb
%vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %neg, <vscale x 16 x float> %neg2) %vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %neg, <vscale x 16 x float> %neg2)
ret <vscale x 16 x float> %vd ret <vscale x 16 x float> %vd
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 4 x double> %vd ret <vscale x 4 x double> %vd
} }
declare <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x double>) declare <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x double>)
define <vscale x 8 x double> @vfnmsub_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) { define <vscale x 8 x double> @vfnmsub_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) {
; CHECK-LABEL: vfnmsub_vv_nxv8f64: ; CHECK-LABEL: vfnmsub_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu
; CHECK-NEXT: vfnmadd.vv v24, v16, v8 ; CHECK-NEXT: vfnmadd.vv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = fneg <vscale x 8 x double> %vb %neg = fneg <vscale x 8 x double> %vb
%neg2 = fneg <vscale x 8 x double> %va %neg2 = fneg <vscale x 8 x double> %va
%vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %neg, <vscale x 8 x double> %vc, <vscale x 8 x double> %neg2) %vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %neg, <vscale x 8 x double> %vc, <vscale x 8 x double> %neg2)
ret <vscale x 8 x double> %vd ret <vscale x 8 x double> %vd
Show All 16 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 16 x half> %vd ret <vscale x 16 x half> %vd
} }
declare <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>) declare <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x half>)
define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) { define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) {
; CHECK-LABEL: vfnmsub_vv_nxv32f16: ; CHECK-LABEL: vfnmsub_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu
; CHECK-NEXT: vfnmsub.vv v8, v24, v16 ; CHECK-NEXT: vfnmsub.vv v8, v24, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = fneg <vscale x 32 x half> %vc %neg = fneg <vscale x 32 x half> %vc
%vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %neg, <vscale x 32 x half> %va, <vscale x 32 x half> %vb) %vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %neg, <vscale x 32 x half> %va, <vscale x 32 x half> %vb)
ret <vscale x 32 x half> %vd ret <vscale x 32 x half> %vd
} }
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x float> %vd ret <vscale x 8 x float> %vd
} }
declare <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>) declare <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x float>)
define <vscale x 16 x float> @vfnmsub_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) { define <vscale x 16 x float> @vfnmsub_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) {
; CHECK-LABEL: vfnmsub_vv_nxv16f32: ; CHECK-LABEL: vfnmsub_vv_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu
; CHECK-NEXT: vfnmsub.vv v24, v8, v16 ; CHECK-NEXT: vfnmsub.vv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = fneg <vscale x 16 x float> %va %neg = fneg <vscale x 16 x float> %va
%vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %neg, <vscale x 16 x float> %vb) %vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %neg, <vscale x 16 x float> %vb)
ret <vscale x 16 x float> %vd ret <vscale x 16 x float> %vd
} }
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ret <vscale x 4 x double> %vd ret <vscale x 4 x double> %vd
} }
declare <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x double>) declare <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x double>)
define <vscale x 8 x double> @vfnmsub_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) { define <vscale x 8 x double> @vfnmsub_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) {
; CHECK-LABEL: vfnmsub_vv_nxv8f64: ; CHECK-LABEL: vfnmsub_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu
; CHECK-NEXT: vfnmsub.vv v24, v16, v8 ; CHECK-NEXT: vfnmsub.vv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%neg = fneg <vscale x 8 x double> %vb %neg = fneg <vscale x 8 x double> %vb
%vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %neg, <vscale x 8 x double> %vc, <vscale x 8 x double> %va) %vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %neg, <vscale x 8 x double> %vc, <vscale x 8 x double> %va)
ret <vscale x 8 x double> %vd ret <vscale x 8 x double> %vd
} }
Show All 14 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfsgnj.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfsgnj.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfsgnj.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfsgnj.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfsgnj.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfsgnj.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfsgnj.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfsgnj.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfsgnj.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfsgnj.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfsgnj.mask.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfsgnj.mask.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfsgnj.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfsgnj.mask.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfsgnj.mask.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfsgnj.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfsgnj.mask.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfsgnj.mask.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 695 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfsgnjn.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfsgnjn.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfsgnjn.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfsgnjn.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfsgnjn.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfsgnjn.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.mask.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfsgnjn.mask.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfsgnjn.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.mask.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfsgnjn.mask.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfsgnjn.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfsgnjn.mask.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfsgnjn.mask.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 695 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfsgnjx.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfsgnjx.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfsgnjx.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfsgnjx.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfsgnjx.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfsgnjx.mask.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.mask.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfsgnjx.mask.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfsgnjx.mask.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.mask.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfsgnjx.mask.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfsgnjx.mask.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfsgnjx.mask.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfsgnjx.mask.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 695 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 727 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll

Show First 20 Lines • Show All 246 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16( %a = call <vscale x 32 x half> @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x half> %2, <vscale x 32 x half> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32( %a = call <vscale x 16 x float> @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x float> %2, <vscale x 16 x float> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64( %a = call <vscale x 8 x double> @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x double> %2, <vscale x 8 x double> %2,
▲ Show 20 Lines • Show All 695 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu ; CHECK-NEXT: vl4re32.v v28, (a0)
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu
; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
▲ Show 20 Lines • Show All 428 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu ; CHECK-NEXT: vl4re32.v v28, (a0)
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu
; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
▲ Show 20 Lines • Show All 428 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu ; CHECK-NEXT: vl4re32.v v28, (a0)
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu
; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
▲ Show 20 Lines • Show All 428 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu ; CHECK-NEXT: vl4re32.v v28, (a0)
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu
; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
▲ Show 20 Lines • Show All 428 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmax.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmax.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmax.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmax.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmaxu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmin.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmin.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmin.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmin.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vminu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vminu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vminu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vminu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmul.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmul.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmul.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmul.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmulh.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vmulhu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vrem.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrem.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vrem.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vrem.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrem.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vrem.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vrem.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrem.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vrem.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vrem.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrem.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vrem.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vrem.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrem.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vrem.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vrem.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrem.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vrem.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vrem.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrem.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vrem.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vremu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vremu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vremu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vremu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vremu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vremu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vremu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vremu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vremu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vremu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vremu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vremu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vremu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vremu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vremu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vremu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vremu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vremu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vremu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vremu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vremu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll

Show First 20 Lines • Show All 296 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32( %a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.nxv8i64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.nxv8i64( %a = call <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.nxv8i64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 2,579 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll

Show First 20 Lines • Show All 296 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vrgather.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgather.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32( %a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.nxv8i64(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64: ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.nxv8i64( %a = call <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.nxv8i64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 2,891 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll

Show First 20 Lines • Show All 521 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16( %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu ; CHECK-NEXT: vl2re16.v v26, (a0)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16( %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll

Show First 20 Lines • Show All 521 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vrgatherei16.mask.nxv8i64.nxv8i16(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64_nxv8i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu ; CHECK-NEXT: vl2re16.v v26, (a0)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.mask.nxv8i64.nxv8i16( %a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.mask.nxv8i64.nxv8i16(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
▲ Show 20 Lines • Show All 254 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16(
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16( %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.mask.nxv32f16.nxv32i16(
<vscale x 32 x half> %0, <vscale x 32 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16(
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16( %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.mask.nxv16f32.nxv16i16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16(
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16: ; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu ; CHECK-NEXT: vl2re16.v v26, (a0)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t ; CHECK-NEXT: vrgatherei16.vv v8, v16, v26, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16( %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.mask.nxv8f64.nxv8i16(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsadd.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsadd.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsadd.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsaddu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsaddu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsaddu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsll.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsll.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsll.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsll.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsmul.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsmul.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsmul.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsra.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsra.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsra.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssra.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssra.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssra.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssra.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vssub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssub.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vssub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssub.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vssub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssub.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vssub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssub.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vssub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssub.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vssub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssub.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vssub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssub.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vssubu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vssubu.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vssubu.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 797 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 973 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu ; CHECK-NEXT: vl4re8.v v28, (a0)
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu
; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 500 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu ; CHECK-NEXT: vl4re8.v v28, (a0)
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu
; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu ; CHECK-NEXT: vl4re32.v v28, (a0)
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu
; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
▲ Show 20 Lines • Show All 680 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu ; CHECK-NEXT: vl4re8.v v28, (a0)
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu
; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 500 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu ; CHECK-NEXT: vl4re8.v v28, (a0)
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu
; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu ; CHECK-NEXT: vl4re32.v v28, (a0)
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu
; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
▲ Show 20 Lines • Show All 680 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu ; CHECK-NEXT: vl4re8.v v28, (a0)
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu
; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 500 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu ; CHECK-NEXT: vl4re8.v v28, (a0)
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu
; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu ; CHECK-NEXT: vl4re32.v v28, (a0)
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu
; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
▲ Show 20 Lines • Show All 680 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu ; CHECK-NEXT: vl4re8.v v28, (a0)
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu
; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 500 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu ; CHECK-NEXT: vl4re8.v v28, (a0)
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu
; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu ; CHECK-NEXT: vl4re16.v v28, (a0)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu
; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu ; CHECK-NEXT: vl4re32.v v28, (a0)
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu
; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t ; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
▲ Show 20 Lines • Show All 680 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 64 x i8> @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 1,373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll

Show First 20 Lines • Show All 289 Lines • ▼ Show 20 Linesdeclare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 64 x i8> @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 64 x i8> @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vl8re8.v v24, (a0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu
; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8( %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(
<vscale x 64 x i8> %0, <vscale x 64 x i8> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 64 x i8> %2, <vscale x 64 x i8> %2,
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i16> @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu
; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16( %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 32 x i16> %2, <vscale x 32 x i16> %2,
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i32> @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu
; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32( %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 16 x i32> %2, <vscale x 16 x i32> %2,
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i64> @intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu ; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu
; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.nxv8i64( %a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.nxv8i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
▲ Show 20 Lines • Show All 1,677 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/scalable-vector-struct.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
; This demonstrates that we can pass a struct containing scalable vectors across ; This demonstrates that we can pass a struct containing scalable vectors across
; a basic block. ; a basic block.
define i32 @foo({ {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, <vscale x 2 x i32>* %y, <vscale x 2 x i32>* %z) { define i32 @foo({ {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, <vscale x 2 x i32>* %y, <vscale x 2 x i32>* %z) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a3, zero, e32,m1,ta,mu ; CHECK-NEXT: vs1r.v v8, (a1)
; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: vs1r.v v9, (a2)
; CHECK-NEXT: vse32.v v9, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %return br label %return
return: return:
%a = extractvalue { {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, 1 %a = extractvalue { {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, 1
%b = extractvalue { {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, 0, 0 %b = extractvalue { {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, 0, 0
%c = extractvalue { {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, 0, 1 %c = extractvalue { {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, 0, 1
store <vscale x 2 x i32> %b, <vscale x 2 x i32>* %y store <vscale x 2 x i32> %b, <vscale x 2 x i32>* %y
store <vscale x 2 x i32> %c, <vscale x 2 x i32>* %z store <vscale x 2 x i32> %c, <vscale x 2 x i32>* %z
ret i32 %a ret i32 %a
} }

llvm/test/MC/RISCV/rvv/invalid.s

Show First 20 Lines • Show All 583 Lines • ▼ Show 20 Lines
vnsrl.wv v0, v4, v20, v0.t vnsrl.wv v0, v4, v20, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vnsrl.wv v0, v4, v20, v0.t # CHECK-ERROR-LABEL: vnsrl.wv v0, v4, v20, v0.t
vfncvt.xu.f.w v0, v4, v0.t vfncvt.xu.f.w v0, v4, v0.t
# CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
# CHECK-ERROR-LABEL: vfncvt.xu.f.w v0, v4, v0.t # CHECK-ERROR-LABEL: vfncvt.xu.f.w v0, v4, v0.t
vl2re8.v v1, (a0)
# CHECK-ERROR: invalid operand for instruction
vl4re8.v v1, (a0)
# CHECK-ERROR: invalid operand for instruction
vl4re8.v v2, (a0)
# CHECK-ERROR: invalid operand for instruction
vl4re8.v v3, (a0)
# CHECK-ERROR: invalid operand for instruction
vl8re8.v v1, (a0)
# CHECK-ERROR: invalid operand for instruction
vl8re8.v v2, (a0)
# CHECK-ERROR: invalid operand for instruction
vl8re8.v v3, (a0)
# CHECK-ERROR: invalid operand for instruction
vl8re8.v v4, (a0)
# CHECK-ERROR: invalid operand for instruction
vl8re8.v v5, (a0)
# CHECK-ERROR: invalid operand for instruction
vl8re8.v v6, (a0)
# CHECK-ERROR: invalid operand for instruction
vl8re8.v v7, (a0)
# CHECK-ERROR: invalid operand for instruction
vs2r.v v1, (a0)
# CHECK-ERROR: invalid operand for instruction
vs4r.v v1, (a0)
# CHECK-ERROR: invalid operand for instruction
vs4r.v v2, (a0)
# CHECK-ERROR: invalid operand for instruction
vs4r.v v3, (a0)
# CHECK-ERROR: invalid operand for instruction
vs8r.v v1, (a0)
# CHECK-ERROR: invalid operand for instruction
vs8r.v v2, (a0)
# CHECK-ERROR: invalid operand for instruction
vs8r.v v3, (a0)
# CHECK-ERROR: invalid operand for instruction
vs8r.v v4, (a0)
# CHECK-ERROR: invalid operand for instruction
vs8r.v v5, (a0)
# CHECK-ERROR: invalid operand for instruction
vs8r.v v6, (a0)
# CHECK-ERROR: invalid operand for instruction
vs8r.v v7, (a0)
# CHECK-ERROR: invalid operand for instruction