[RISCV] Implement the MC layer support of P extension

[Jim]

Summary

Contribute Andes's the MC layer support of RVP extension.
The encoding of RVP instructions is according to 0.9.11 version in https://github.com/riscv/riscv-p-spec/.

There are three sub-extensions in RVP.
zbpbo contains instructions overlap with the B extension.
zpn is a basic sub-extension. Most of instructions are belong to zpn.
zpsfoperand is the instruction will read or write 64-bit operands. On RV32, 64-bit operand is even/odd paired-register.
p = zbpbo + zpn + zpsfoperand

This patch has the tests for assemble/disassemble each instructions.

There are four test files for invalid assembly testing.
rvp-invalid.s is for invalid immediate operand in zpn extension for both RV32 and RV64.
rv32zpsfoperand-invalid.s shows that operand should be even register for even/odd paired-register operand on RV32.
rv64zpsfoperand-invalid.s are for invalid immediate operand in zpsfoperand extension on RV64.
rv64zpn-invalid.s are for invalid immediate operand for RV64 only instructions.

[Jim]

Rebase

[Jim]

Rebase.
RVInstR4->RVInstR4Frm.

[Jim]

Rebase

[Jim]

Add tests for paired register operand for RV32.
Move testcases out of rvp directory.
Alias swap16 to pkbt16.

[Jim]

Rebase

[Jim]

Any comments? Thanks.

[Jim]

Fix comment 0.9 to 0.93

[Jim]

ping? Thanks.

[craig.topper]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

957

I think this can just be

return ((Reg - RISCV::X0) % 2) == 0 && Reg != RISCV::X0

Though the spec talks about what happens when X0_X1 is used as a source or dest, so should we really be forbidding X0?

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

443

Fold the 64-bit check into the if above with && to reduce nesting.

llvm/lib/Target/RISCV/RISCVInstrFormats.td

130

I think these opcodes are in numerical order, so please put this at the end to maintain that.

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

132

Are the positions correct? They don't match the 0.9.5-draft-20210617 pdf. Change log suggests it was modified in 0.5.3?

951

Why do these need EmitPriority = 2?

952

Can we give "def : SysReg<"vxsat", 0x009>;" a name in RISCVSystemOperands.td so we can reference it's encoding directly here like we do for these aliases

def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, INSTRET.Encoding, X0)>;                                                                                                                                                                                                    
def : InstAlias<"rdcycle $rd",   (CSRRS GPR:$rd, CYCLE.Encoding, X0)>;                                                                                                                                                                                                      
def : InstAlias<"rdtime $rd",    (CSRRS GPR:$rd, TIME.Encoding, X0)>;

[Jim]

1. Address comments about coding style
2. Append postfix valid to testcase file name
3. Fix the changes of encoding in version 0.5.3
4. Remove EmitPriority = 2 for rdov and clrov. It would emit no alias csrr rd, vxsat and csrci vxsat, 1 instead.
5. Give a name to sys register vxsat for reference its encoding.
6. Let X0 is a legal operand of even/odd paired-register. Add a dummy register ZERO to pair with X0. I am not sure that is a good implementation by adding a dummy register. X0 paired with X1 is not conformed with the spec.

[Jim]

Any comments? Thanks.

[Jim]

Ping? Thanks.

[Jim]

Rebase

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

600

It looks like the 0.9.3 spec lists this as an alias of MULSR64 and does not give it an encoding.

738

0.9.3 spec has this as an alias of KMAR64

836

I believe way this has been done on other extensions is to have (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, uimmlog2xlenbytes:$shamt) and let Constraints = "$rd = $rd_wb"

And I don't think it should inherit from RVInstR since it doesn't have a real rs2.

[luismarques]

This patch is nearly there! Just address the remaining review comments and it LGTM.

BTW, please mark all addressed inline comments as done. I think a few were missed, and it's helpful for a large patch like this.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

960–963

Nitpicking: perhaps this could use better terminology. You're asserting that Reg is a GPRPair, and then you convert Reg to a GPRPair, but the return value would fail an assert of isGPRPair...

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

69

What's the best way to address this?

llvm/test/MC/RISCV/rv32zpsfoperand-invalid.s

7–10

It would be nice to have a more specific error message, indicating the need for an even register operand. But not a deal-breaker, IMO.

[Jim]

Address comments.

1. Add alias for MULSR64 and KMAR64
2. Fix instr format for INSB.
3. Add new GPRPairOpOperand and implement parseGPRPairReg to report the need for an even register.

[Jim]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

69

sub_lo and sub_hi are only used for GPRPair register class to extract a register from pair registers on RV32.

[Jim]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

69

Do you mean that sub_lo and sub_hi only used on RV32? Does it need to rename or ..?

[Jim]

Rebase

[Jim]

ping? Thanks.

[craig.topper]

I think this looks good to me. @luismarques or @jrtc27 any further feedback?

[jrtc27]

I can't help but feel the assembly syntax for the register pair instructions should include both registers (perhaps in curly braces). The implicit use of the other register when reading the source is rather ugly, and particularly hard to remember when the RV64 versions *don't* do that. But that's a spec problem, not one with this patch, just something I'd like future spec revisions to give serious thought to...

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

442

The table is called RISCV32POnly but you're checking for Zpsfoperand (whatever that mouthful of an extension is). Which is it?

llvm/lib/Target/RISCV/RISCV.td

186–188

These aren't correct? RV64 doesn't have Zpsfoperand and RV32 doesn't have Zprvsfextra.

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

146

These lines look too long to me

177–178

232

Should probably have a TODO: to add scheduling information for these otherwise it'll get lost

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

69

Yes, these should have names that make it clear they're for each half of a 2*32-bit register pair. Otherwise it sounds like they're the 32-bit hi and lo halves of the 64-bit registers on RV64.

216

Ew, this is a gross quirk of the register pair instructions. ZERO is not a good name for it though, that's the ABI name for x0 so already taken and is pretty confusing. I assume LLVM doesn't like it if you create a register pair that is (X0, X0)?

226–228

IMO the register class should be GPR32Pair not GPRPair unless you also make it have a sensible interpretation for RV32 (which seems like a waste of time)

llvm/test/MC/RISCV/rv64zpn-invalid.s

6–24 ↗

(On Diff #360741)

This looks mostly the same as rv32zpn-invalid. The common tests should go in rv32zpn-invalid and have RV32 and RV64 RUN lines. Any truly RV32-only tests belong in something like rv32zpn-only-invalid. Any truly RV64-only tests can stay in rv64zpn-invalid.

[jrtc27]

Oh, technically none of the clang changes belong in this patch. Those are for the Clang driver and preprocessor, not the MC layer which is purely llvm.

[Jim]

1. Add TODO before instruction definitions that is lack scheduling information.
2. Rename sub_lo and sub_hi to gpr_pair_lo and gpr_pair_hi.
3. Rename ZERO register paired with X0 to REG_PAIR_WITH_X0 to avoid confusing.
4. Rename GPRPair to GPR32Pair. It only is used for RV32.
5. Move common invalid inst test to rvp-invalid.s. And add rv32zpn-only-invalid.s and rv64zpn-only-invalid.s.

[Jim]

Add missing changes on previous update.

[Jim]

In D95588#2898470, @jrtc27 wrote:

Oh, technically none of the clang changes belong in this patch. Those are for the Clang driver and preprocessor, not the MC layer which is purely llvm.

I move the clang changes to D95589 and D95590.

[Jim]

Rename decode table name RISCV32POnly_ to RISCV32Zpsfoperand_.

[Jim]

Apply git-clang-format

[Jim]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

442

Rename RISCV32POnly to RISCV32Zpsfoperand.
This is for the instruction with even/odd paired-register operands on RV32.

In RISCV32Zpsfoperand, two kinds of instruction defined for the same instruction in spec, one for RV32 with even/odd paired-register operands defined in RISCV32Zpsfoperand table , the other one for RV64 with normal GPR operands.

llvm/lib/Target/RISCV/RISCV.td

186–188

RV64 has Zpsfoperand extension that just has normal GPRs as operands (RV32 has even/odd paired-register operand).

RV32 doesn't have Zprvsfextra. All of instruction in Zprvsfextra are defined in Predicates = [HasStdExtZprvsfextra, IsRV64].

If P is enabled, it means Zpn+Zpsfoperand enabled on RV32, and Zpn+Zpsfoperand+Zprvsfextra enabled on RV64.

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

69

Rename it to gpr_pair_lo and gpr_pair_hi

216

Rename it to REG_PAIR_WITH_X0.

226–228

Rename it to GPR32Pair.

[Jim]

@jrtc27 Any more feedback? Thanks.

[Jim]

Rebase

[jrtc27]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

69

The names still do not reflect the fact that they are only for RV32; currently it *looks* like on RV64 it'd give you the 64-bit GPR

[Jim]

Rename gpr_pair_lo and gpr_pair_hi to gpr32_pair_lo and gpr32_pair_hi for indicating only for RV32.

[Jim]

Kindly ping? Thanks.

[Jim]

Rebase

[Jim]

Hi @jrtc27, any further feedback? Thanks.

[jrtc27]

llvm/lib/Target/RISCV/RISCV.td

186–188

My concern is that the internal inflexibility is going to leak out of LLVM, such as into the .riscv.attributes section, and thus produce broken binaries because they claim they need Zprvsfextra on RV32, which is an invalid combination.

And if Zpsfoperand exists for RV64 then it shouldn't be called Paired-register operand 'P' Instructions, because the operands are only paired on RV32.

[Jim]

Fix the description for Zpsfoperand to 64-bit operand 'P' Instructions

[Jim]

llvm/lib/Target/RISCV/RISCV.td

186–188

I upload a new patch https://reviews.llvm.org/D108189 to support P extension 's arch string.
If rv32izprvsfextra (Zprvsfextra on RV32) accepted from *.s arch attribute, it emits error message to forbid this invalid combination.
Before emitting _zprvsfextra string, it would check RV64 is enabled.

If llc is given -mattr=+experimental-zprvsfextra on RV32, it would be ignored.

[Jim]

Rebase

[Jim]

Hi, @jrtc27

About the concern the invalid combination RV32 + zprvsfextra on riscv attribute,
I upload a patch D108189 based on @kito-cheng 's patch D105168 to forbid emitting rv32+zprvsfextra arch string.
And It also deny to accept rv32izprvsfextra https://reviews.llvm.org/differential/changeset/?ref=2787775.

Patch D108189 have not emitted and accepted invalid arch string combined from rv32 and zprvsfextra.

Thanks for feedback.

[Jim]

Ping? Thanks.

[Jim]

Update to the newest P spec 0.96
https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#revision-history

1. Merger Zprvsfextra (sub-extension for RV64 only) into Zpn So, RV32 and RV64 have the same sub-extension combination policy. P = Zpn + Zpsfoperand @jrtc27's concern is not existed now.
2. Removed CLO* instructions.
3. Fix incorrect testcases.

[Jim]

Remove HasStdExtZprvsfextra and hasStdExtZprvsfextra() from RISCVSubtarget.h

[Jim]

Fix incorrect -mattr for testcases.

[Jim]

Move common invalid mc tests for both RV32 and RV64 to rvp-invalid.s

[Jim]

Any feedback? I think this patch is good enough to be accepted.

[Jim]

In D95588#3003090, @Jim wrote:

Any feedback? I think this patch is good enough to be accepted.

Ping? Thanks.

[jrtc27]

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

442

Is there a reason why this needs to be limited to Zpsfoperand? We don't have separate namespaces for every extension, we only add them when there are conflicts (with the "more common" extension being in the default namespace). I'd expect RISCV32Only_ with just a Feature64Bit check, like we do for some RV32C instructions, to be sufficient.

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

11

Isn't it 0.9.6 (or 0.9.7 now)? Not that that's a legal extension version number...

148

FOO32 vs FOO64 intuitively implies something about the width of operands to me, not what ISA they're for. For B the instruction definitions use _RV32 and _RV64 suffices.

Especially since the instructions are already called things like ADD64, this will generate nonsense ADD6432 and ADD6464 names...

170

This, RVPSMAL64Pair and RVPALU64Pair are all just RVPBinary with different numbers of the operands changed to GPR32PairOp, I think this would be better with default (to GPR) template arguments added to RVPBinary for rd/rs1/rs2 rather than having three almost-identical copies of the same thing under varying names

182

Similarly just make RVPTernary take template arguments for the types (in this case only one argument, for rd/rs3, needed)

910

Having the same instruction in two different extensions under two different names is insane. Currently this implementation lets you use the "wrong" name for kmar64 with Zpn. But I would prefer the spec weren't crazy.

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

219

Won't the order affect register allocation? Technically not an issue for this MC patch but the correct thing should be committed so there's no churn when adding codegen.

That or don't reuse this in the register class below and instead manually list the pairs in the class.

228

Why is this untyped?

[Jim]

1. Rename DecoderNamespace RISCV32Zpsoperand_ -> RISCV32Only_
2. 0.96 -> 0.9.6
3. Use suffices _32 and _64.
4. Reuse RVPBinary and RVPTernary for GPR32PairOp operand
5. Explict list register pair with allocation order

[Jim]

Rename suffices _32 to _RV32 and _64 to _RV64.

[Jim]

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

910

I am still working on fixing it (from spec or ...) . But it is spec issue.

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

228

GPR32Pair has untyped type.
In code generation, It captures some operation with i64 type supported by Zpsoperand to untyped during legalization.
In my mind, untyped is used to be represented special type don't need any legalization.
I refer to ARMRegisterInfo.td that defines GPRPair with untyped.

[jrtc27]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

219

You didn't need to manually list them all here...

228

So, presumably it can't be i64 because that would then make i64 a legal type? Maybe that's fine, maybe it's not, but alternatively it could be typed as v2i32 here (can include v4i16 and v8i8 too) and cast if/when needed. Craig maybe you have thoughts on this? But untyped always feels like laziness to me that results in TableGen being unable to help you when it comes to type checking, with rare exceptions.

[Jim]

Rebase

[Jim]

Remove inst alias smbb32 (alias to mulsr64) and kmar64 (alias to kmar64).
Having the same instruction in two different extensions under two different name is gone.

P-extension is not yet frozen. I am still cooperating with P-extension maintainer on this issue.

[Jim]

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

910

Remove alias inst first. I will discuss with P-extension maintainer on this issue.
Could this issue be fixed by a future revision?

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

228

All of operation node having untyped operands are customized SDNode lowered in RISCVISelLowering.cpp. And matched to a specific pattern.
untyped couldn't be as v2i32, v4i16 or v8i8 in the same time. The operand type has been checked in custom lowering.

The lowering for operation with specific operand types (v2i32, v4i16, v8i8 or i64 in this case) would be set cutsom and lowered to customized SDNode (This SDNode has untyped operands).
Different operand types with the same operation are lowered to different customized SDNode.

[Jim]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

4360 ↗

(On Diff #410235)

The change for this testcase is that GPRJALR regclass is subsumed by GPR32Pair_with_gpr32_pair_lo_in_GPRNoX0X2 regclass.
And register pressure calculation is different.

[Jim]

Rebase

[sunshaoce]

Hello @Jim! We are developing the P extension, are you still maintaining this patch? Or would you mind co-development together?

[sunshaoce]

Support for P extension version 0.9.11

[sunshaoce]

Fix early-clobber-tied-def-subreg-liveness.mir

[sunshaoce]

Rebase

[Jim]

In D95588#3622052, @sunshaoce wrote:

Hello @Jim! We are developing the P extension, are you still maintaining this patch? Or would you mind co-development together?

Yes, I am still on developing the P extension. But it seems spec has the issue https://github.com/riscv/riscv-p-spec/issues/137 need to clarify.
And some instruction (CLZ, FSR and FSRI) in Zbpbo only be aliased to B extension on RV32. It is complicated if P extension are enabled on RV64.

[sunshaoce]

In D95588#3641900, @Jim wrote:

In D95588#3622052, @sunshaoce wrote:

Hello @Jim! We are developing the P extension, are you still maintaining this patch? Or would you mind co-development together?

Yes, I am still on developing the P extension. But it seems spec has the issue https://github.com/riscv/riscv-p-spec/issues/137 need to clarify.
And some instruction (CLZ, FSR and FSRI) in Zbpbo only be aliased to B extension on RV32. It is complicated if P extension are enabled on RV64.

Yes, this problem does exist. Thanks for your reply, looking forward to more cooperation!

[sunshaoce]

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

600

0b011 should be 0b010. https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#847-ukstsa32-simd-32-bit-unsigned-saturating-straight-subtraction--addition

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

#include "RISCVGenAsmMatcher.inc"
   OperandMatchResultTy parseAtomicMemOp(OperandVector &Operands);
   OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
   OperandMatchResultTy parseBareSymbol(OperandVector &Operands);
   OperandMatchResultTy parseCallSymbol(OperandVector &Operands);
   OperandMatchResultTy parsePseudoJumpSymbol(OperandVector &Operands);
   OperandMatchResultTy parseJALOffset(OperandVector &Operands);
   OperandMatchResultTy parseVTypeI(OperandVector &Operands);
   OperandMatchResultTy parseMaskReg(OperandVector &Operands);
+  OperandMatchResultTy parseGPR32PairReg(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
   bool parseDirectiveOption();
   bool parseDirectiveAttribute();
 
   void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
     if (!(getSTI().getFeatureBits()[Feature])) {
public:
   bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
   bool isVType() const { return Kind == KindTy::VType; }
 
   bool isGPR() const {
     return Kind == KindTy::Register &&
            RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
   }
 
+  bool isGPR32Pair() const {
+    return Kind == KindTy::Register &&
+           RISCVMCRegisterClasses[RISCV::GPR32PairRegClassID].contains(
+               Reg.RegNum);
+  }
+
   static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
                                   RISCVMCExpr::VariantKind &VK) {
     if (auto *RE = dyn_cast<RISCVMCExpr>(Expr)) {
       VK = RE->getKind();
       return RE->evaluateAsConstant(Imm);
     }
 
     if (auto CE = dyn_cast<MCConstantExpr>(Expr)) {
bool isUImmLog2XLenHalf() const {
     if (!isImm())
       return false;
     if (!evaluateConstantImm(getImm(), Imm, VK) ||
         VK != RISCVMCExpr::VK_RISCV_None)
       return false;
     return (isRV64() && isUInt<5>(Imm)) || isUInt<4>(Imm);
   }
 
+  bool isUImmLog2XLenBytes() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    if (!evaluateConstantImm(getImm(), Imm, VK) ||
+        VK != RISCVMCExpr::VK_RISCV_None)
+      return false;
+    return (isRV64() && isUInt<3>(Imm)) || isUInt<2>(Imm);
+  }
+
+  bool isUImm3() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<3>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isUImm4() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<4>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm5() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
   else
     return 0;
   return RI.getMatchingSuperReg(Reg, RISCV::sub_vrm1_0,
                                 &RISCVMCRegisterClasses[RegClassID]);
 }
 
 unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
                                                     unsigned Kind) {
   RISCVOperand &Op = static_cast<RISCVOperand &>(AsmOp);
   if (!Op.isReg())
     return Match_InvalidOperand;
 
   MCRegister Reg = Op.getReg();
   bool IsRegFPR64 =
       RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg);
   bool IsRegFPR64C =
       RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
   bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);
 
   // As the parser couldn't differentiate an FPR32 from an FPR64, coerce the
   // register from FPR64 to FPR32 or FPR64C to FPR32C if necessary.
   if ((IsRegFPR64 && Kind == MCK_FPR32) ||
       (IsRegFPR64C && Kind == MCK_FPR32C)) {
     Op.Reg.RegNum = convertFPR64ToFPR32(Reg);
     return Match_Success;
   }
   // As the parser couldn't differentiate an FPR16 from an FPR64, coerce the
   // register from FPR64 to FPR16 if necessary.
   if (IsRegFPR64 && Kind == MCK_FPR16) {
     Op.Reg.RegNum = convertFPR64ToFPR16(Reg);
     return Match_Success;
   }
   // As the parser couldn't differentiate an VRM2/VRM4/VRM8 from an VR, coerce
   // the register from VR to VRM2/VRM4/VRM8 if necessary.
   if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) {
     Op.Reg.RegNum = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind);
     if (Op.Reg.RegNum == 0)
       return Match_InvalidOperand;
     return Match_Success;
   }
   return Match_InvalidOperand;
 }
 
bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidUImmLog2XLenNonZero:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
   case Match_InvalidUImmLog2XLenHalf:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
+  case Match_InvalidUImmLog2XLenBytes:
+    if (isRV64())
+      return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1);
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);
+  case Match_InvalidUImm3:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1);
+  case Match_InvalidUImm4:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
   case Match_InvalidUImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
   case Match_InvalidSImm5:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4),
                                       (1 << 4) - 1);
   case Match_InvalidSImm6:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5),
                                       (1 << 5) - 1);
if (OptionalImmOp && !OptionalImmOp->isImmZero()) {
     Error(OptionalImmOp->getStartLoc(), "optional integer offset must be 0",
           SMRange(OptionalImmOp->getStartLoc(), OptionalImmOp->getEndLoc()));
     return MatchOperand_ParseFail;
   }
 
   return MatchOperand_Success;
 }
 
+OperandMatchResultTy
+RISCVAsmParser::parseGPR32PairReg(OperandVector &Operands) {
+
+  switch (getLexer().getKind()) {
+  default:
+    return MatchOperand_NoMatch;
+  case AsmToken::Identifier:
+    StringRef Name = getLexer().getTok().getIdentifier();
+    MCRegister RegNo;
+    matchRegisterNameHelper(isRV32E(), RegNo, Name);
+
+    if (RegNo == RISCV::NoRegister)
+      return MatchOperand_NoMatch;
+
+    const MCRegisterClass &GPRRegClass =
+        RISCVMCRegisterClasses[RISCV::GPRRegClassID];
+    if (!GPRRegClass.contains(RegNo)) {
+      Error(getLoc(), "expected general purpose register");
+      return MatchOperand_ParseFail;
+    }
+
+    if (!isRV64()) {
+      if ((RegNo - RISCV::X0) % 2 != 0) {
+        Error(getLoc(), "expected even register");
+        return MatchOperand_ParseFail;
+      }
+      RegNo = (RegNo - RISCV::X0) / 2 + RISCV::X0_REG_PAIR_WITH_X0;
+    }
+    SMLoc S = getLoc();
+    SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
+    getLexer().Lex();
+    Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64()));
+  }
+
+  return MatchOperand_Success;
+}
+
 /// Looks at a token type and creates the relevant operand from this
 /// information, adding to Operands. If operand was parsed, returns false, else
 /// true.
 bool RISCVAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
   // Check if the current operand has a custom associated parser, if so, try to
   // custom parse the operand, or fallback to the general approach.
   OperandMatchResultTy Result =
       MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/true);

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

case 0:
     break;
   case 1:
     break;
   }
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeGPR32PairRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                                 uint64_t Address,
+                                                 const void *Decoder) {
+  if (RegNo >= 32 || RegNo & 1)
+    return MCDisassembler::Fail;
+
+  MCRegister Reg = RISCV::X0_REG_PAIR_WITH_X0 + (RegNo / 2);
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 // Add implied SP operand for instructions *SP compressed instructions. The SP
 // operand isn't explicitly encoded in the instruction.
 static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
   if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
       Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
       Inst.getOpcode() == RISCV::C_FLWSP ||
       Inst.getOpcode() == RISCV::C_FSWSP ||
       Inst.getOpcode() == RISCV::C_FLDSP ||
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
 
   // It's a 32 bit instruction if bit 0 and 1 are 1.
   if ((Bytes[0] & 0x3) == 0x3) {
     if (Bytes.size() < 4) {
       Size = 0;
       return MCDisassembler::Fail;
     }
     Insn = support::endian::read32le(Bytes.data());
+
+    if (STI.getFeatureBits()[RISCV::FeatureExtZpsfoperand] &&
+        !STI.getFeatureBits()[RISCV::Feature64Bit]) {
+      LLVM_DEBUG(dbgs() << "Trying RISCV32Zpsfoperand_32 table (Zpsfoperand "
+                           "32-bit Instruction):\n");
+      // Calling the auto-generated decoder function.
+      Result = decodeInstruction(DecoderTableRISCV32Zpsfoperand_32, MI, Insn,
+                                 Address, this, STI);
+      if (Result != MCDisassembler::Fail) {
+        Size = 4;
+        return Result;
+      }
+    }
+
     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
     Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
     Size = 4;
   } else {
     if (Bytes.size() < 2) {
       Size = 0;
       return MCDisassembler::Fail;
     }
     Insn = support::endian::read16le(Bytes.data());
 
     if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

enum {
   // multiple "bitmask" flags.
   MO_DIRECT_FLAG_MASK = 15
 };
 } // namespace RISCVII
 
 namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
-  OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM3 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM4,
   OPERAND_UIMM5,
   OPERAND_UIMM12,
   OPERAND_SIMM12,
   OPERAND_UIMM20,
   OPERAND_UIMMLOG2XLEN,
   OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN,
   // Operand is either a register or uimm5, this is used by V extension pseudo
   // instructions to represent a value that be passed as AVL to either vsetvli

llvm/lib/Target/RISCV/RISCV.td

: SubtargetFeature<"experimental-b", "HasStdExtB", "true",
                         FeatureExtZbp,
                         FeatureExtZbr,
                         FeatureExtZbs,
                         FeatureExtZbt]>;
 def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
                            AssemblerPredicate<(all_of FeatureStdExtB),
                            "'B' (Bit Manipulation Instructions)">;
 
+def FeatureExtZpn
+    : SubtargetFeature<"experimental-zpn", "HasStdExtZpn", "true",
+                       "'Zpn' (Normal 'P' Instructions)">;
+def HasStdExtZpn : Predicate<"Subtarget->hasStdExtZpn()">,
+                             AssemblerPredicate<(all_of FeatureExtZpn),
+                             "'Zpn' (Normal 'P' Instructions)">;
+
+def FeatureExtZpsfoperand
+    : SubtargetFeature<"experimental-zpsfoperand", "HasStdExtZpsfoperand", "true",
+                       "'Zpsfoperand' (Paired-register operand 'P' Instructions)">;
+def HasStdExtZpsfoperand : Predicate<"Subtarget->hasStdExtZpsfoperand()">,
+                           AssemblerPredicate<(all_of FeatureExtZpsfoperand),
+                           "'Zpsfoperand' (Paired-register operand 'P' Instructions)">;
+
+def FeatureExtZprvsfextra
+    : SubtargetFeature<"experimental-zprvsfextra", "HasStdExtZprvsfextra", "true",
+                       "'Zprvsfextra' (RV64 only 'P' Instructions)">;
+def HasStdExtZprvsfextra : Predicate<"Subtarget->hasStdExtZprvsfextra()">,
+                           AssemblerPredicate<(all_of FeatureExtZprvsfextra),
+                           "'Zprvsfextra' (RV64 only 'P' Instructions)">;
+
+def FeatureStdExtP
+    : SubtargetFeature<"experimental-p", "HasStdExtP", "true",
+                       "'P' (Packed-SIMD Instructions)",
+                       [FeatureExtZpsfoperand,
+                        FeatureExtZpn,
+                        FeatureExtZprvsfextra]>;
+def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">,
+                           AssemblerPredicate<(all_of FeatureStdExtP),
+                           "'P' (Packed-SIMD Instructions)">;
+
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                       "RVC Hint Instructions">;
 
 def FeatureStdExtV

llvm/lib/Target/RISCV/RISCVInstrFormats.td

 def OPC_OP        : RISCVOpcode<0b0110011>;
 def OPC_LUI       : RISCVOpcode<0b0110111>;
 def OPC_OP_32     : RISCVOpcode<0b0111011>;
 def OPC_MADD      : RISCVOpcode<0b1000011>;
 def OPC_MSUB      : RISCVOpcode<0b1000111>;
 def OPC_NMSUB     : RISCVOpcode<0b1001011>;
 def OPC_NMADD     : RISCVOpcode<0b1001111>;
 def OPC_OP_FP     : RISCVOpcode<0b1010011>;
 def OPC_OP_V      : RISCVOpcode<0b1010111>;
 def OPC_BRANCH    : RISCVOpcode<0b1100011>;
 def OPC_JALR      : RISCVOpcode<0b1100111>;
 def OPC_JAL       : RISCVOpcode<0b1101111>;
 def OPC_SYSTEM    : RISCVOpcode<0b1110011>;
+def OPC_OP_P      : RISCVOpcode<0b1110111>;
 
 class RVInst<dag outs, dag ins, string opcodestr, string argstr,
              list<dag> pattern, InstFormat format>
     : Instruction {
   field bits<32> Inst;
   // SoftFail is a field the disassembler can use to provide a way for
   // instructions to not match without killing the whole decode process. It is
   // mainly used for ARM, but Tablegen expects this field to exist or it fails

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
         OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
       const MachineOperand &MO = MI.getOperand(OI.index());
       if (MO.isImm()) {
         int64_t Imm = MO.getImm();
         bool Ok;
         switch (OpType) {
         default:
           llvm_unreachable("Unexpected operand type");
+        case RISCVOp::OPERAND_UIMM3:
+          Ok = isUInt<3>(Imm);
+          break;
         case RISCVOp::OPERAND_UIMM4:
           Ok = isUInt<4>(Imm);
           break;
         case RISCVOp::OPERAND_UIMM5:
           Ok = isUInt<5>(Imm);
           break;
         case RISCVOp::OPERAND_UIMM12:
           Ok = isUInt<12>(Imm);

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoB.td"
+include "RISCVInstrInfoP.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"

llvm/lib/Target/RISCV/RISCVInstrInfoP.td

+//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions from the standard 'P' SIMD
+/// extension, version 0.93.
+/// This version is still experimental as the 'P' extension hasn't been
+/// ratified yet.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm3 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<3>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<3>;
+  let DecoderMethod = "decodeUImmOperand<3>";
+  let OperandType = "OPERAND_UIMM3";
+  let OperandNamespace = "RISCVOp";
+}
+
+def uimm4 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<4>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<4>;
+  let DecoderMethod = "decodeUImmOperand<4>";
+  let OperandType = "OPERAND_UIMM4";
+  let OperandNamespace = "RISCVOp";
+}
+
+def UImmLog2XLenBytesAsmOperand : AsmOperandClass {
+  let Name = "UImmLog2XLenBytes";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = "InvalidUImmLog2XLenBytes";
+}
+
+def uimmlog2xlenbytes : Operand<XLenVT>, ImmLeaf<XLenVT, [{
+  if (Subtarget->is64Bit())
+    return isUInt<3>(Imm);
+  return isUInt<2>(Imm);
+}]> {
+  let ParserMatchClass = UImmLog2XLenBytesAsmOperand;
+  let DecoderMethod = "decodeUImmOperand<3>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    if (STI.getTargetTriple().isArch64Bit())
+      return isUInt<3>(Imm);
+    return isUInt<2>(Imm);
+  }];
+}
+
+def GPR32PairOpOperand : AsmOperandClass {
+  let Name = "GPR32PairOpOperand";
+  let RenderMethod = "addRegOperands";
+  let PredicateMethod = "isGPR32Pair";
+  let ParserMethod = "parseGPR32PairReg";
+}
+
+def GPR32PairOp : RegisterOperand<GPR32Pair> {
+  let ParserMatchClass = GPR32PairOpOperand;
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_P, (outs GPR:$rd), (ins GPR:$rs1),
+              opcodestr, "$rd, $rs1"> {
+  let Inst{24-20} = funct5;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinary<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_P,
+              (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+              opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPTernary<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_P,
+              (outs GPR:$rd), (ins GPR:$rs3, GPR:$rs1, GPR:$rs2),
+              opcodestr, "$rd, $rs1, $rs2"> {
+  let Constraints = "$rs3 = $rd";
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPShiftI3<bits<7> funct7, bits<2> funct2,
+                 bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_OP_P, (outs GPR:$rd), (ins GPR:$rs1, uimm3:$shamt),
+              opcodestr, "$rd, $rs1, $shamt"> {
+  bits<3> shamt;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-23} = funct2;
+  let Inst{22-20} = shamt;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPShiftI4<bits<7> funct7, bits<1> funct1,
+                 bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_OP_P, (outs GPR:$rd), (ins GPR:$rs1, uimm4:$shamt),
+              opcodestr, "$rd, $rs1, $shamt"> {
+  bits<4> shamt;
+
+  let Inst{31-25} = funct7;
+  let Inst{24} = funct1;
+  let Inst{23-20} = shamt;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPShiftI5<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_OP_P, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$shamt),
+              opcodestr, "$rd, $rs1, $shamt"> {
+  bits<5> shamt;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = shamt;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPShiftUImmLog2XLen<bits<6> funct6, bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_OP_P, (outs GPR:$rd),
+              (ins GPR:$rs1, uimmlog2xlen:$shamt),
+              opcodestr, "$rd, $rs1, $shamt"> {
+  bits<6> shamt;
+
+  let Inst{31-26} = funct6;
+  let Inst{25-20} = shamt;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPALU64Pair<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_P, (outs GPR32PairOp:$rd),
+              (ins GPR32PairOp:$rs1, GPR32PairOp:$rs2),
+              opcodestr, "$rd, $rs1, $rs2">;
+
+multiclass RVPALU64<bits<7> funct7, bits<3> funct3, string opcodestr> {
+  let DecoderNamespace = "RISCV32Zpsfoperand_",
+      Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def "32" : RVPALU64Pair<funct7, funct3, opcodestr>;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def "64" : RVPBinary<funct7, funct3, opcodestr>;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPSMAL64Pair<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_P, (outs GPR32PairOp:$rd),
+              (ins GPR32PairOp:$rs1, GPR:$rs2),
+              opcodestr, "$rd, $rs1, $rs2">;
+
+multiclass RVPSMAL64<bits<7> funct7, bits<3> funct3, string opcodestr> {
+  let DecoderNamespace = "RISCV32Zpsfoperand_",
+      Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def "32" : RVPSMAL64Pair<funct7, funct3, opcodestr>;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def "64" : RVPBinary<funct7, funct3, opcodestr>;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPMUL64Pair<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_P, (outs GPR32PairOp:$rd),
+              (ins GPR:$rs1, GPR:$rs2),
+              opcodestr, "$rd, $rs1, $rs2">;
+
+multiclass RVPMUL64<bits<7> funct7, bits<3> funct3, string opcodestr> {
+  let DecoderNamespace = "RISCV32Zpsfoperand_",
+      Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def "32" : RVPMUL64Pair<funct7, funct3, opcodestr>;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def "64" : RVPBinary<funct7, funct3, opcodestr>;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPMA64Pair<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_P, (outs GPR32PairOp:$rd),
+              (ins GPR32PairOp:$rs3, GPR:$rs1, GPR:$rs2),
+              opcodestr, "$rd, $rs1, $rs2"> {
+  let Constraints = "$rs3 = $rd";
+}
+
+multiclass RVPMA64<bits<7> funct7, bits<3> funct3, string opcodestr> {
+  let DecoderNamespace = "RISCV32Zpsfoperand_",
+      Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def "32" : RVPMA64Pair<funct7, funct3, opcodestr>;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def "64" : RVPTernary<funct7, funct3, opcodestr>;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPWEXTPair<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_P, (outs GPR:$rd),
+              (ins GPR32PairOp:$rs1, GPR:$rs2),
+              opcodestr, "$rd, $rs1, $rs2">;
+
+multiclass RVPWEXT<bits<7> funct7, bits<3> funct3, string opcodestr> {
+  let DecoderNamespace = "RISCV32Zpsfoperand_",
+      Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def "32" : RVPWEXTPair<funct7, funct3, opcodestr>;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def "64" : RVPBinary<funct7, funct3, opcodestr>;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPWEXTPairI<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstI<funct3, OPC_OP_P,
+              (outs GPR:$rd), (ins GPR32PairOp:$rs1, uimm5:$shamt),
+              opcodestr, "$rd, $rs1, $shamt"> {
+  bits<5> shamt;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = shamt;
+}
+
+multiclass RVPWEXTI<bits<7> funct7, bits<3> funct3, string opcodestr> {
+  let DecoderNamespace = "RISCV32Zpsfoperand_",
+      Predicates = [HasStdExtZpsfoperand, IsRV32] in
+  def "32" : RVPWEXTPairI<funct7, funct3, opcodestr>;
+  let Predicates = [HasStdExtZpsfoperand, IsRV64] in
+  def "64" : RVPShiftI5<funct7, funct3, opcodestr>;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+// TODO: Add scheduling information for these instructions.
+
+// Unary Instructions
+
+let Predicates = [HasStdExtZpn] in {
+def CLRS8     : RVPUnary<0b1010111, 0b00000, 0b000, "clrs8">,
+                Sched<[]>;
+def CLRS16    : RVPUnary<0b1010111, 0b01000, 0b000, "clrs16">,
+                Sched<[]>;
+def CLRS32    : RVPUnary<0b1010111, 0b11000, 0b000, "clrs32">,
+                Sched<[]>;
+def CLO8      : RVPUnary<0b1010111, 0b00011, 0b000, "clo8">,
+                Sched<[]>;
+def CLO16     : RVPUnary<0b1010111, 0b01011, 0b000, "clo16">,
+                Sched<[]>;
+def CLO32     : RVPUnary<0b1010111, 0b11011, 0b000, "clo32">,
+                Sched<[]>;
+def CLZ8      : RVPUnary<0b1010111, 0b00001, 0b000, "clz8">,
+                Sched<[]>;
+def CLZ16     : RVPUnary<0b1010111, 0b01001, 0b000, "clz16">,
+                Sched<[]>;
+def CLZ32     : RVPUnary<0b1010111, 0b11001, 0b000, "clz32">,
+                Sched<[]>;
+def KABS8     : RVPUnary<0b1010110, 0b10000, 0b000, "kabs8">,
+                Sched<[]>;
+def KABS16    : RVPUnary<0b1010110, 0b10001, 0b000, "kabs16">,
+                Sched<[]>;
+def KABSW     : RVPUnary<0b1010110, 0b10100, 0b000, "kabsw">,
+                Sched<[]>;
+def SUNPKD810 : RVPUnary<0b1010110, 0b01000, 0b000, "sunpkd810">,
+                Sched<[]>;
+def SUNPKD820 : RVPUnary<0b1010110, 0b01001, 0b000, "sunpkd820">,
+                Sched<[]>;
+def SUNPKD830 : RVPUnary<0b1010110, 0b01010, 0b000, "sunpkd830">,
+                Sched<[]>;
+def SUNPKD831 : RVPUnary<0b1010110, 0b01011, 0b000, "sunpkd831">,
+                Sched<[]>;
+def SUNPKD832 : RVPUnary<0b1010110, 0b10011, 0b000, "sunpkd832">,
+                Sched<[]>;
+def SWAP8     : RVPUnary<0b1010110, 0b11000, 0b000, "swap8">,
+                Sched<[]>;
+def ZUNPKD810 : RVPUnary<0b1010110, 0b01100, 0b000, "zunpkd810">,
+                Sched<[]>;
+def ZUNPKD820 : RVPUnary<0b1010110, 0b01101, 0b000, "zunpkd820">,
+                Sched<[]>;
+def ZUNPKD830 : RVPUnary<0b1010110, 0b01110, 0b000, "zunpkd830">,
+                Sched<[]>;
+def ZUNPKD831 : RVPUnary<0b1010110, 0b01111, 0b000, "zunpkd831">,
+                Sched<[]>;
+def ZUNPKD832 : RVPUnary<0b1010110, 0b10111, 0b000, "zunpkd832">,
+                Sched<[]>;
+} // Predicates = [HasStdExtZpn]
+
+let Predicates = [HasStdExtZprvsfextra, IsRV64] in
+def KABS32 : RVPUnary<0b1010110, 0b10010, 0b000, "kabs32">,
+             Sched<[]>;
+
+// Binary Instructions
+
+let Predicates = [HasStdExtZpn] in {
+def ADD8     : RVPBinary<0b0100100, 0b000, "add8">,
+               Sched<[]>;
+def ADD16    : RVPBinary<0b0100000, 0b000, "add16">,
+               Sched<[]>;
+def AVE      : RVPBinary<0b1110000, 0b000, "ave">,
+               Sched<[]>;
+def BITREV   : RVPBinary<0b1110011, 0b000, "bitrev">,
+               Sched<[]>;
+def CMPEQ8   : RVPBinary<0b0100111, 0b000, "cmpeq8">,
+               Sched<[]>;
+def CMPEQ16  : RVPBinary<0b0100110, 0b000, "cmpeq16">,
+               Sched<[]>;
+def CRAS16   : RVPBinary<0b0100010, 0b000, "cras16">,
+               Sched<[]>;
+def CRSA16   : RVPBinary<0b0100011, 0b000, "crsa16">,
+               Sched<[]>;
+def KADD8    : RVPBinary<0b0001100, 0b000, "kadd8">,
+               Sched<[]>;
+def KADD16   : RVPBinary<0b0001000, 0b000, "kadd16">,
+               Sched<[]>;
+def KADDH    : RVPBinary<0b0000010, 0b001, "kaddh">,
+               Sched<[]>;
+def KADDW    : RVPBinary<0b0000000, 0b001, "kaddw">,
+               Sched<[]>;
+def KCRAS16  : RVPBinary<0b0001010, 0b000, "kcras16">,
+               Sched<[]>;
+def KCRSA16  : RVPBinary<0b0001011, 0b000, "kcrsa16">,
+               Sched<[]>;
+def KDMBB    : RVPBinary<0b0000101, 0b001, "kdmbb">,
+               Sched<[]>;
+def KDMBT    : RVPBinary<0b0001101, 0b001, "kdmbt">,
+               Sched<[]>;
+def KDMTT    : RVPBinary<0b0010101, 0b001, "kdmtt">,
+               Sched<[]>;
+def KHM8     : RVPBinary<0b1000111, 0b000, "khm8">,
+               Sched<[]>;
+def KHMX8    : RVPBinary<0b1001111, 0b000, "khmx8">,
+               Sched<[]>;
+def KHM16    : RVPBinary<0b1000011, 0b000, "khm16">,
+               Sched<[]>;
+def KHMX16   : RVPBinary<0b1001011, 0b000, "khmx16">,
+               Sched<[]>;
+def KHMBB    : RVPBinary<0b0000110, 0b001, "khmbb">,
+               Sched<[]>;
+def KHMBT    : RVPBinary<0b0001110, 0b001, "khmbt">,
+               Sched<[]>;
+def KHMTT    : RVPBinary<0b0010110, 0b001, "khmtt">,
+               Sched<[]>;
+def KMDA     : RVPBinary<0b0011100, 0b001, "kmda">,
+               Sched<[]>;
+def KMXDA    : RVPBinary<0b0011101, 0b001, "kmxda">,
+               Sched<[]>;
+def KMMWB2   : RVPBinary<0b1000111, 0b001, "kmmwb2">,
+               Sched<[]>;
+def KMMWB2U  : RVPBinary<0b1001111, 0b001, "kmmwb2.u">,
+               Sched<[]>;
+def KMMWT2   : RVPBinary<0b1010111, 0b001, "kmmwt2">,
+               Sched<[]>;
+def KMMWT2U  : RVPBinary<0b1011111, 0b001, "kmmwt2.u">,
+               Sched<[]>;
+def KSLLW    : RVPBinary<0b0010011, 0b001, "ksllw">,
+               Sched<[]>;
+def KSLL8    : RVPBinary<0b0110110, 0b000, "ksll8">,
+               Sched<[]>;
+def KSLL16   : RVPBinary<0b0110010, 0b000, "ksll16">,
+               Sched<[]>;
+def KSLRA8   : RVPBinary<0b0101111, 0b000, "kslra8">,
+               Sched<[]>;
+def KSLRA8U  : RVPBinary<0b0110111, 0b000, "kslra8.u">,
+               Sched<[]>;
+def KSLRA16  : RVPBinary<0b0101011, 0b000, "kslra16">,
+               Sched<[]>;
+def KSLRA16U : RVPBinary<0b0110011, 0b000, "kslra16.u">,
+               Sched<[]>;
+def KSLRAW   : RVPBinary<0b0110111, 0b001, "kslraw">,
+               Sched<[]>;
+def KSLRAWU  : RVPBinary<0b0111111, 0b001, "kslraw.u">,
+               Sched<[]>;
+def KSTAS16  : RVPBinary<0b1100010, 0b010, "kstas16">,
+               Sched<[]>;
+def KSTSA16  : RVPBinary<0b1100011, 0b010, "kstsa16">,
+               Sched<[]>;
+def KSUB8    : RVPBinary<0b0001101, 0b000, "ksub8">,
+               Sched<[]>;
+def KSUB16   : RVPBinary<0b0001001, 0b000, "ksub16">,
+               Sched<[]>;
+def KSUBH    : RVPBinary<0b0000011, 0b001, "ksubh">,
+               Sched<[]>;
+def KSUBW    : RVPBinary<0b0000001, 0b001, "ksubw">,
+               Sched<[]>;
+def KWMMUL   : RVPBinary<0b0110001, 0b001, "kwmmul">,
+               Sched<[]>;
+def KWMMULU  : RVPBinary<0b0111001, 0b001, "kwmmul.u">,
+               Sched<[]>;
+def MAXW     : RVPBinary<0b1111001, 0b000, "maxw">,
+               Sched<[]>;
+def MINW     : RVPBinary<0b1111000, 0b000, "minw">,
+               Sched<[]>;
+def PBSAD    : RVPBinary<0b1111110, 0b000, "pbsad">,
+               Sched<[]>;
+def PKBB16   : RVPBinary<0b0000111, 0b001, "pkbb16">,
+               Sched<[]>;
+def PKBT16   : RVPBinary<0b0001111, 0b001, "pkbt16">,
+               Sched<[]>;
+def PKTT16   : RVPBinary<0b0010111, 0b001, "pktt16">,
+               Sched<[]>;
+def PKTB16   : RVPBinary<0b0011111, 0b001, "pktb16">,
+               Sched<[]>;
+def RADD8    : RVPBinary<0b0000100, 0b000, "radd8">,
+               Sched<[]>;
+def RADD16   : RVPBinary<0b0000000, 0b000, "radd16">,
+               Sched<[]>;
+def RADDW    : RVPBinary<0b0010000, 0b001, "raddw">,
+               Sched<[]>;
+def RCRAS16  : RVPBinary<0b0000010, 0b000, "rcras16">,
+               Sched<[]>;
+def RCRSA16  : RVPBinary<0b0000011, 0b000, "rcrsa16">,
+               Sched<[]>;
+def RSTAS16  : RVPBinary<0b1011010, 0b010, "rstas16">,
+               Sched<[]>;
+def RSTSA16  : RVPBinary<0b1011011, 0b010, "rstsa16">,
+               Sched<[]>;
+def RSUB8    : RVPBinary<0b0000101, 0b000, "rsub8">,
+               Sched<[]>;
+def RSUB16   : RVPBinary<0b0000001, 0b000, "rsub16">,
+               Sched<[]>;
+def RSUBW    : RVPBinary<0b0010001, 0b001, "rsubw">,
+               Sched<[]>;
+def SCMPLE8  : RVPBinary<0b0001111, 0b000, "scmple8">,
+               Sched<[]>;
+def SCMPLE16 : RVPBinary<0b0001110, 0b000, "scmple16">,
+               Sched<[]>;
+def SCMPLT8  : RVPBinary<0b0000111, 0b000, "scmplt8">,
+               Sched<[]>;
+def SCMPLT16 : RVPBinary<0b0000110, 0b000, "scmplt16">,
+               Sched<[]>;
+def SLL8     : RVPBinary<0b0101110, 0b000, "sll8">,
+               Sched<[]>;
+def SLL16    : RVPBinary<0b0101010, 0b000, "sll16">,
+               Sched<[]>;
+def SMAX8    : RVPBinary<0b1000101, 0b000, "smax8">,
+               Sched<[]>;
+def SMAX16   : RVPBinary<0b1000001, 0b000, "smax16">,
+               Sched<[]>;
+def SMBB16   : RVPBinary<0b0000100, 0b001, "smbb16">,
+               Sched<[]>;
+def SMBT16   : RVPBinary<0b0001100, 0b001, "smbt16">,
+               Sched<[]>;
+def SMTT16   : RVPBinary<0b0010100, 0b001, "smtt16">,
+               Sched<[]>;
+def SMDS     : RVPBinary<0b0101100, 0b001, "smds">,
+               Sched<[]>;
+def SMDRS    : RVPBinary<0b0110100, 0b001, "smdrs">,
+               Sched<[]>;
+def SMXDS    : RVPBinary<0b0111100, 0b001, "smxds">,
+               Sched<[]>;
+def SMIN8    : RVPBinary<0b1000100, 0b000, "smin8">,
+               Sched<[]>;
+def SMIN16   : RVPBinary<0b1000000, 0b000, "smin16">,
+               Sched<[]>;
+def SMMUL    : RVPBinary<0b0100000, 0b001, "smmul">,
+               Sched<[]>;
+def SMMULU   : RVPBinary<0b0101000, 0b001, "smmul.u">,
+               Sched<[]>;
+def SMMWB    : RVPBinary<0b0100010, 0b001, "smmwb">,
+               Sched<[]>;
+def SMMWBU   : RVPBinary<0b0101010, 0b001, "smmwb.u">,
+               Sched<[]>;
+def SMMWT    : RVPBinary<0b0110010, 0b001, "smmwt">,
+               Sched<[]>;
+def SMMWTU   : RVPBinary<0b0111010, 0b001, "smmwt.u">,
+               Sched<[]>;
+def SRAU     : RVPBinary<0b0010010, 0b001, "sra.u">,
+               Sched<[]>;
+def SRA8     : RVPBinary<0b0101100, 0b000, "sra8">,
+               Sched<[]>;
+def SRA8U    : RVPBinary<0b0110100, 0b000, "sra8.u">,
+               Sched<[]>;
+def SRA16    : RVPBinary<0b0101000, 0b000, "sra16">,
+               Sched<[]>;
+def SRA16U   : RVPBinary<0b0110000, 0b000, "sra16.u">,
+               Sched<[]>;
+def SRL8     : RVPBinary<0b0101101, 0b000, "srl8">,
+               Sched<[]>;
+def SRL8U    : RVPBinary<0b0110101, 0b000, "srl8.u">,
+               Sched<[]>;
+def SRL16    : RVPBinary<0b0101001, 0b000, "srl16">,
+               Sched<[]>;
+def SRL16U   : RVPBinary<0b0110001, 0b000, "srl16.u">,
+               Sched<[]>;
+def STAS16   : RVPBinary<0b1111010, 0b010, "stas16">,
+               Sched<[]>;
+def STSA16   : RVPBinary<0b1111011, 0b010, "stsa16">,
+               Sched<[]>;
+def SUB8     : RVPBinary<0b0100101, 0b000, "sub8">,
+               Sched<[]>;
+def SUB16    : RVPBinary<0b0100001, 0b000, "sub16">,
+               Sched<[]>;
+def UCMPLE8  : RVPBinary<0b0011111, 0b000, "ucmple8">,
+               Sched<[]>;
+def UCMPLE16 : RVPBinary<0b0011110, 0b000, "ucmple16">,
+               Sched<[]>;
+def UCMPLT8  : RVPBinary<0b0010111, 0b000, "ucmplt8">,
+               Sched<[]>;
+def UCMPLT16 : RVPBinary<0b0010110, 0b000, "ucmplt16">,
+               Sched<[]>;
+def UKADD8   : RVPBinary<0b0011100, 0b000, "ukadd8">,
+               Sched<[]>;
+def UKADD16  : RVPBinary<0b0011000, 0b000, "ukadd16">,
+               Sched<[]>;
+def UKADDH   : RVPBinary<0b0001010, 0b001, "ukaddh">,
+               Sched<[]>;
+def UKADDW   : RVPBinary<0b0001000, 0b001, "ukaddw">,
+               Sched<[]>;
+def UKCRAS16 : RVPBinary<0b0011010, 0b000, "ukcras16">,
+               Sched<[]>;
+def UKCRSA16 : RVPBinary<0b0011011, 0b000, "ukcrsa16">,
+               Sched<[]>;
+def UKSTAS16 : RVPBinary<0b1110010, 0b010, "ukstas16">,
+               Sched<[]>;
+def UKSTSA16 : RVPBinary<0b1110011, 0b010, "ukstsa16">,
+               Sched<[]>;
+def UKSUB8   : RVPBinary<0b0011101, 0b000, "uksub8">,
+               Sched<[]>;
+def UKSUB16  : RVPBinary<0b0011001, 0b000, "uksub16">,
+               Sched<[]>;
+def UKSUBH   : RVPBinary<0b0001011, 0b001, "uksubh">,
+               Sched<[]>;
+def UKSUBW   : RVPBinary<0b0001001, 0b001, "uksubw">,
+               Sched<[]>;
+def UMAX8    : RVPBinary<0b1001101, 0b000, "umax8">,
+               Sched<[]>;
+def UMAX16   : RVPBinary<0b1001001, 0b000, "umax16">,
+               Sched<[]>;
+def UMIN8    : RVPBinary<0b1001100, 0b000, "umin8">,
+               Sched<[]>;
+def UMIN16   : RVPBinary<0b1001000, 0b000, "umin16">,
+               Sched<[]>;
+def URADD8   : RVPBinary<0b0010100, 0b000, "uradd8">,
+               Sched<[]>;
+def URADD16  : RVPBinary<0b0010000, 0b000, "uradd16">,
+               Sched<[]>;
+def URADDW   : RVPBinary<0b0011000, 0b001, "uraddw">,
+               Sched<[]>;
+def URCRAS16 : RVPBinary<0b0010010, 0b000, "urcras16">,
+               Sched<[]>;
+def URCRSA16 : RVPBinary<0b0010011, 0b000, "urcrsa16">,
+               Sched<[]>;
+def URSTAS16 : RVPBinary<0b1101010, 0b010, "urstas16">,
+               Sched<[]>;
+def URSTSA16 : RVPBinary<0b1101011, 0b010, "urstsa16">,
+               Sched<[]>;
+def URSUB8   : RVPBinary<0b0010101, 0b000, "ursub8">,
+               Sched<[]>;
+def URSUB16  : RVPBinary<0b0010001, 0b000, "ursub16">,
+               Sched<[]>;
+def URSUBW   : RVPBinary<0b0011001, 0b001, "ursubw">,
+               Sched<[]>;
+} // Predicates = [HasStdExtZpn]
+
+let Predicates = [HasStdExtZprvsfextra, IsRV64] in {
+def ADD32    : RVPBinary<0b0100000, 0b010, "add32">,
+               Sched<[]>;
+def CRAS32   : RVPBinary<0b0100010, 0b010, "cras32">,
+               Sched<[]>;
+def CRSA32   : RVPBinary<0b0100011, 0b010, "crsa32">,
+               Sched<[]>;
+def KADD32   : RVPBinary<0b0001000, 0b010, "kadd32">,
+               Sched<[]>;
+def KCRAS32  : RVPBinary<0b0001010, 0b010, "kcras32">,
+               Sched<[]>;
+def KCRSA32  : RVPBinary<0b0001011, 0b010, "kcrsa32">,
+               Sched<[]>;
+def KDMBB16  : RVPBinary<0b1101101, 0b001, "kdmbb16">,
+               Sched<[]>;
+def KDMBT16  : RVPBinary<0b1110101, 0b001, "kdmbt16">,
+               Sched<[]>;
+def KDMTT16  : RVPBinary<0b1111101, 0b001, "kdmtt16">,
+               Sched<[]>;
+def KHMBB16  : RVPBinary<0b1101110, 0b001, "khmbb16">,
+               Sched<[]>;
+def KHMBT16  : RVPBinary<0b1110110, 0b001, "khmbt16">,
+               Sched<[]>;
+def KHMTT16  : RVPBinary<0b1111110, 0b001, "khmtt16">,
+               Sched<[]>;
+def KMDA32   : RVPBinary<0b0011100, 0b010, "kmda32">,
+               Sched<[]>;
+def KMXDA32  : RVPBinary<0b0011101, 0b010, "kmxda32">,
+               Sched<[]>;
+def KSLL32   : RVPBinary<0b0110010, 0b010, "ksll32">,
+               Sched<[]>;
+def KSLRA32  : RVPBinary<0b0101011, 0b010, "kslra32">,
+               Sched<[]>;
+def KSLRA32U : RVPBinary<0b0110011, 0b010, "kslra32.u">,
+               Sched<[]>;
+def KSTAS32  : RVPBinary<0b1100000, 0b010, "kstas32">,
+               Sched<[]>;
+def KSTSA32  : RVPBinary<0b1100001, 0b010, "kstsa32">,
+               Sched<[]>;
+def KSUB32   : RVPBinary<0b0001001, 0b010, "ksub32">,
+               Sched<[]>;
+def PKBB32   : RVPBinary<0b0000111, 0b010, "pkbb32">,
+               Sched<[]>;
+def PKBT32   : RVPBinary<0b0001111, 0b010, "pkbt32">,
+               Sched<[]>;
+def PKTT32   : RVPBinary<0b0010111, 0b010, "pktt32">,
+               Sched<[]>;
+def PKTB32   : RVPBinary<0b0011111, 0b010, "pktb32">,
+               Sched<[]>;
+def RADD32   : RVPBinary<0b0000000, 0b010, "radd32">,
+               Sched<[]>;
+def RCRAS32  : RVPBinary<0b0000010, 0b010, "rcras32">,
+               Sched<[]>;
+def RCRSA32  : RVPBinary<0b0000011, 0b010, "rcrsa32">,
+               Sched<[]>;
+def RSTAS32  : RVPBinary<0b1011000, 0b010, "rstas32">,
+               Sched<[]>;
+def RSTSA32  : RVPBinary<0b1011001, 0b010, "rstsa32">,
+               Sched<[]>;
+def RSUB32   : RVPBinary<0b0000001, 0b010, "rsub32">,
+               Sched<[]>;
+def SLL32    : RVPBinary<0b0101010, 0b010, "sll32">,
+               Sched<[]>;
+def SMAX32   : RVPBinary<0b1001001, 0b010, "smax32">,
+               Sched<[]>;
+def SMBT32   : RVPBinary<0b0001100, 0b010, "smbt32">,
+               Sched<[]>;
+def SMTT32   : RVPBinary<0b0010100, 0b010, "smtt32">,
+               Sched<[]>;
+def SMDS32   : RVPBinary<0b0101100, 0b010, "smds32">,
+               Sched<[]>;
+def SMDRS32  : RVPBinary<0b0110100, 0b010, "smdrs32">,
+               Sched<[]>;
+def SMXDS32  : RVPBinary<0b0111100, 0b010, "smxds32">,
+               Sched<[]>;
+def SMIN32   : RVPBinary<0b1001000, 0b010, "smin32">,
+               Sched<[]>;
+def SRA32    : RVPBinary<0b0101000, 0b010, "sra32">,
+               Sched<[]>;
+def SRA32U   : RVPBinary<0b0110000, 0b010, "sra32.u">,
+               Sched<[]>;
+def SRL32    : RVPBinary<0b0101001, 0b010, "srl32">,
+               Sched<[]>;
+def SRL32U   : RVPBinary<0b0110001, 0b010, "srl32.u">,
+               Sched<[]>;
+def STAS32   : RVPBinary<0b1111000, 0b010, "stas32">,
+               Sched<[]>;
+def STSA32   : RVPBinary<0b1111001, 0b010, "stsa32">,
+               Sched<[]>;
+def SUB32    : RVPBinary<0b0100001, 0b010, "sub32">,
+               Sched<[]>;
+def UKADD32  : RVPBinary<0b0011000, 0b010, "ukadd32">,
+               Sched<[]>;
+def UKCRAS32 : RVPBinary<0b0011010, 0b010, "ukcras32">,
+               Sched<[]>;
+def UKCRSA32 : RVPBinary<0b0011011, 0b010, "ukcrsa32">,
+               Sched<[]>;
+def UKSTAS32 : RVPBinary<0b1110000, 0b010, "ukstas32">,
+               Sched<[]>;
+def UKSTSA32 : RVPBinary<0b1110001, 0b011, "ukstsa32">,
+               Sched<[]>;
+def UKSUB32  : RVPBinary<0b0011001, 0b010, "uksub32">,
+               Sched<[]>;
+def UMAX32   : RVPBinary<0b1010001, 0b010, "umax32">,
+               Sched<[]>;
+def UMIN32   : RVPBinary<0b1010000, 0b010, "umin32">,
+               Sched<[]>;
+def URADD32  : RVPBinary<0b0010000, 0b010, "uradd32">,
+               Sched<[]>;
+def URCRAS32 : RVPBinary<0b0010010, 0b010, "urcras32">,
+               Sched<[]>;
+def URCRSA32 : RVPBinary<0b0010011, 0b010, "urcrsa32">,
+               Sched<[]>;
+def URSTAS32 : RVPBinary<0b1101000, 0b010, "urstas32">,
+               Sched<[]>;
+def URSTSA32 : RVPBinary<0b1101001, 0b010, "urstsa32">,
+               Sched<[]>;
+def URSUB32  : RVPBinary<0b0010001, 0b010, "ursub32">,
+               Sched<[]>;
+} // Predicates = [HasStdExtZprvsfextra, IsRV64]
+
+// Ternary Instructions
+
+let Predicates = [HasStdExtZpn] in {
+def KDMABB   : RVPTernary<0b1101001, 0b001, "kdmabb">,
+               Sched<[]>;
+def KDMABT   : RVPTernary<0b1110001, 0b001, "kdmabt">,
+               Sched<[]>;
+def KDMATT   : RVPTernary<0b1111001, 0b001, "kdmatt">,
+               Sched<[]>;
+def KMABB    : RVPTernary<0b0101101, 0b001, "kmabb">,
+               Sched<[]>;
+def KMABT    : RVPTernary<0b0110101, 0b001, "kmabt">,
+               Sched<[]>;
+def KMATT    : RVPTernary<0b0111101, 0b001, "kmatt">,
+               Sched<[]>;
+def KMADA    : RVPTernary<0b0100100, 0b001, "kmada">,
+               Sched<[]>;
+def KMAXDA   : RVPTernary<0b0100101, 0b001, "kmaxda">,
+               Sched<[]>;
+def KMADS    : RVPTernary<0b0101110, 0b001, "kmads">,
+               Sched<[]>;
+def KMADRS   : RVPTernary<0b0110110, 0b001, "kmadrs">,
+               Sched<[]>;
+def KMAXDS   : RVPTernary<0b0111110, 0b001, "kmaxds">,
+               Sched<[]>;
+def KMMAC    : RVPTernary<0b0110000, 0b001, "kmmac">,
+               Sched<[]>;
+def KMMACU   : RVPTernary<0b0111000, 0b001, "kmmac.u">,
+               Sched<[]>;
+def KMMAWB   : RVPTernary<0b0100011, 0b001, "kmmawb">,
+               Sched<[]>;
+def KMMAWBU  : RVPTernary<0b0101011, 0b001, "kmmawb.u">,
+               Sched<[]>;
+def KMMAWB2  : RVPTernary<0b1100111, 0b001, "kmmawb2">,
+               Sched<[]>;
+def KMMAWB2U : RVPTernary<0b1101111, 0b001, "kmmawb2.u">,
+               Sched<[]>;
+def KMMAWT   : RVPTernary<0b0110011, 0b001, "kmmawt">,
+               Sched<[]>;
+def KMMAWTU  : RVPTernary<0b0111011, 0b001, "kmmawt.u">,
+               Sched<[]>;
+def KMMAWT2  : RVPTernary<0b1110111, 0b001, "kmmawt2">,
+               Sched<[]>;
+def KMMAWT2U : RVPTernary<0b1111111, 0b001, "kmmawt2.u">,
+               Sched<[]>;
+def KMMSB    : RVPTernary<0b0100001, 0b001, "kmmsb">,
+               Sched<[]>;
+def KMMSBU   : RVPTernary<0b0101001, 0b001, "kmmsb.u">,
+               Sched<[]>;
+def KMSDA    : RVPTernary<0b0100110, 0b001, "kmsda">,
+               Sched<[]>;
+def KMSXDA   : RVPTernary<0b0100111, 0b001, "kmsxda">,
+               Sched<[]>;
+def MADDR32  : RVPTernary<0b1100010, 0b001, "maddr32">,
+               Sched<[]>;
+def MSUBR32  : RVPTernary<0b1100011, 0b001, "msubr32">,
+               Sched<[]>;
+def PBSADA   : RVPTernary<0b1111111, 0b000, "pbsada">,
+               Sched<[]>;
+def SMAQA    : RVPTernary<0b1100100, 0b000, "smaqa">,
+               Sched<[]>;
+def SMAQASU  : RVPTernary<0b1100101, 0b000, "smaqa.su">,
+               Sched<[]>;
+def UMAQA    : RVPTernary<0b1100110, 0b000, "umaqa">,
+               Sched<[]>;
+} // Predicates = [HasStdExtZpn]
+
+let Predicates = [HasStdExtZprvsfextra, IsRV64] in {
+def KDMABB16 : RVPTernary<0b1101100, 0b001, "kdmabb16">,
+               Sched<[]>;
+def KDMABT16 : RVPTernary<0b1110100, 0b001, "kdmabt16">,
+               Sched<[]>;
+def KDMATT16 : RVPTernary<0b1111100, 0b001, "kdmatt16">,
+               Sched<[]>;
+def KMABB32  : RVPTernary<0b0101101, 0b010, "kmabb32">,
+               Sched<[]>;
+def KMABT32  : RVPTernary<0b0110101, 0b010, "kmabt32">,
+               Sched<[]>;
+def KMATT32  : RVPTernary<0b0111101, 0b010, "kmatt32">,
+               Sched<[]>;
+def KMAXDA32 : RVPTernary<0b0100101, 0b010, "kmaxda32">,
+               Sched<[]>;
+def KMADS32  : RVPTernary<0b0101110, 0b010, "kmads32">,
+               Sched<[]>;
+def KMADRS32 : RVPTernary<0b0110110, 0b010, "kmadrs32">,
+               Sched<[]>;
+def KMAXDS32 : RVPTernary<0b0111110, 0b010, "kmaxds32">,
+               Sched<[]>;
+def KMSDA32  : RVPTernary<0b0100110, 0b010, "kmsda32">,
+               Sched<[]>;
+def KMSXDA32 : RVPTernary<0b0100111, 0b010, "kmsxda32">,
+               Sched<[]>;
+} // Predicates = [HasStdExtZprvsfextra, IsRV64]
+
+// Shift Instructions
+
+let Predicates = [HasStdExtZpn] in {
+def KSLLI8 : RVPShiftI3<0b0111110, 0b01, 0b000, "kslli8">,
+             Sched<[]>;
+def SCLIP8 : RVPShiftI3<0b1000110, 0b00, 0b000, "sclip8">,
+             Sched<[]>;
+def SLLI8  : RVPShiftI3<0b0111110, 0b00, 0b000, "slli8">,
+             Sched<[]>;
+def SRAI8  : RVPShiftI3<0b0111100, 0b00, 0b000, "srai8">,
+             Sched<[]>;
+def SRAI8U : RVPShiftI3<0b0111100, 0b01, 0b000, "srai8.u">,
+             Sched<[]>;
+def SRLI8  : RVPShiftI3<0b0111101, 0b00, 0b000, "srli8">,
+             Sched<[]>;
+def SRLI8U : RVPShiftI3<0b0111101, 0b01, 0b000, "srli8.u">,
+             Sched<[]>;
+def UCLIP8 : RVPShiftI3<0b1000110, 0b10, 0b000, "uclip8">,
+             Sched<[]>;
+} // Predicates = [HasStdExtZpn]
+
+let Predicates = [HasStdExtZpn] in {
+def KSLLI16 : RVPShiftI4<0b0111010, 0b1, 0b000, "kslli16">,
+              Sched<[]>;
+def SCLIP16 : RVPShiftI4<0b1000010, 0b0, 0b000, "sclip16">,
+              Sched<[]>;
+def SLLI16  : RVPShiftI4<0b0111010, 0b0, 0b000, "slli16">,
+              Sched<[]>;
+def SRAI16  : RVPShiftI4<0b0111000, 0b0, 0b000, "srai16">,
+              Sched<[]>;
+def SRAI16U : RVPShiftI4<0b0111000, 0b1, 0b000, "srai16.u">,
+              Sched<[]>;
+def SRLI16  : RVPShiftI4<0b0111001, 0b0, 0b000, "srli16">,
+              Sched<[]>;
+def SRLI16U : RVPShiftI4<0b0111001, 0b1, 0b000, "srli16.u">,
+              Sched<[]>;
+def UCLIP16 : RVPShiftI4<0b1000010, 0b1, 0b000, "uclip16">,
+              Sched<[]>;
+} // Predicates = [HasStdExtZpn]
+
+let Predicates = [HasStdExtZpn] in {
+def KSLLIW  : RVPShiftI5<0b0011011, 0b001, "kslliw">,
+              Sched<[]>;
+def SCLIP32 : RVPShiftI5<0b1110010, 0b000, "sclip32">,
+              Sched<[]>;
+def UCLIP32 : RVPShiftI5<0b1111010, 0b000, "uclip32">,
+              Sched<[]>;
+} // Predicates = [HasStdExtZpn]
+
+let Predicates = [HasStdExtZprvsfextra, IsRV64] in {
+def KSLLI32 : RVPShiftI5<0b1000010, 0b010, "kslli32">,
+              Sched<[]>;
+def SLLI32  : RVPShiftI5<0b0111010, 0b010, "slli32">,
+              Sched<[]>;
+def SRAI32  : RVPShiftI5<0b0111000, 0b010, "srai32">,
+              Sched<[]>;
+def SRAI32U : RVPShiftI5<0b1000000, 0b010, "srai32.u">,
+              Sched<[]>;
+def SRAIWU  : RVPShiftI5<0b0011010, 0b001, "sraiw.u">,
+              Sched<[]>;
+def SRLI32  : RVPShiftI5<0b0111001, 0b010, "srli32">,
+              Sched<[]>;
+def SRLI32U : RVPShiftI5<0b1000001, 0b010, "srli32.u">,
+              Sched<[]>;
+} // Predicates = [HasStdExtZprvsfextra, IsRV64]
+
+let Predicates = [HasStdExtZpn] in {
+def SRAIU : RVPShiftUImmLog2XLen<0b110101, 0b001, "srai.u">,
+            Sched<[]>;
+def BITREVI : RVPShiftUImmLog2XLen<0b111010, 0b000, "bitrevi">,
+              Sched<[]>;
+} // Predicates = [HasStdExtZpn]
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+    Predicates = [HasStdExtZpn] in
+def BPICK : RVInstR4<0b00, 0b011, OPC_OP_P, (outs GPR:$rd),
+                     (ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+                     "bpick", "$rd, $rs1, $rs2, $rs3">,
+            Sched<[]>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+    Predicates = [HasStdExtZpn] in
+def INSB : RVInstI<0b000, OPC_OP_P, (outs GPR:$rd_wb),
+                   (ins GPR:$rd, GPR:$rs1, uimmlog2xlenbytes:$shamt),
+                   "insb", "$rd, $rs1, $shamt">,
+           Sched<[]> {
+  bits<3> shamt;
+
+  let Constraints = "$rd = $rd_wb";
+  let Inst{31-25} = 0b1010110;
+  let Inst{24-23} = 0b00;
+  let Inst{22-20} = shamt;
+}
+
+// 64-bit Instructions
+
+defm ADD64   : RVPALU64<0b1100000, 0b001, "add64">,
+               Sched<[]>;
+defm KADD64  : RVPALU64<0b1001000, 0b001, "kadd64">,
+               Sched<[]>;
+defm KSUB64  : RVPALU64<0b1001001, 0b001, "ksub64">,
+               Sched<[]>;
+defm RADD64  : RVPALU64<0b1000000, 0b001, "radd64">,
+               Sched<[]>;
+defm RSUB64  : RVPALU64<0b1000001, 0b001, "rsub64">,
+               Sched<[]>;
+defm SUB64   : RVPALU64<0b1100001, 0b001, "sub64">,
+               Sched<[]>;
+defm UKADD64 : RVPALU64<0b1011000, 0b001, "ukadd64">,
+               Sched<[]>;
+defm UKSUB64 : RVPALU64<0b1011001, 0b001, "uksub64">,
+               Sched<[]>;
+defm URADD64 : RVPALU64<0b1010000, 0b001, "uradd64">,
+               Sched<[]>;
+defm URSUB64 : RVPALU64<0b1010001, 0b001, "ursub64">,
+               Sched<[]>;
+
+defm SMAL : RVPSMAL64<0b0101111, 0b001, "smal">,
+            Sched<[]>;
+
+defm MULR64  : RVPMUL64<0b1111000, 0b001, "mulr64">,
+               Sched<[]>;
+defm MULSR64 : RVPMUL64<0b1110000, 0b001, "mulsr64">,
+               Sched<[]>;
+defm SMUL8   : RVPMUL64<0b1010100, 0b000, "smul8">,
+               Sched<[]>;
+defm SMULX8  : RVPMUL64<0b1010101, 0b000, "smulx8">,
+               Sched<[]>;
+defm SMUL16  : RVPMUL64<0b1010000, 0b000, "smul16">,
+               Sched<[]>;
+defm SMULX16 : RVPMUL64<0b1010001, 0b000, "smulx16">,
+               Sched<[]>;
+defm UMUL8   : RVPMUL64<0b1011100, 0b000, "umul8">,
+               Sched<[]>;
+defm UMULX8  : RVPMUL64<0b1011101, 0b000, "umulx8">,
+               Sched<[]>;
+defm UMUL16  : RVPMUL64<0b1011000, 0b000, "umul16">,
+               Sched<[]>;
+defm UMULX16 : RVPMUL64<0b1011001, 0b000, "umulx16">,
+               Sched<[]>;
+
+defm KMAR64  : RVPMA64<0b1001010, 0b001, "kmar64">,
+               Sched<[]>;
+defm KMSR64  : RVPMA64<0b1001011, 0b001, "kmsr64">,
+               Sched<[]>;
+defm SMALBB  : RVPMA64<0b1000100, 0b001, "smalbb">,
+               Sched<[]>;
+defm SMALBT  : RVPMA64<0b1001100, 0b001, "smalbt">,
+               Sched<[]>;
+defm SMALTT  : RVPMA64<0b1010100, 0b001, "smaltt">,
+               Sched<[]>;
+defm SMALDA  : RVPMA64<0b1000110, 0b001, "smalda">,
+               Sched<[]>;
+defm SMALXDA : RVPMA64<0b1001110, 0b001, "smalxda">,
+               Sched<[]>;
+defm SMALDS  : RVPMA64<0b1000101, 0b001, "smalds">,
+               Sched<[]>;
+defm SMALDRS : RVPMA64<0b1001101, 0b001, "smaldrs">,
+               Sched<[]>;
+defm SMALXDS : RVPMA64<0b1010101, 0b001, "smalxds">,
+               Sched<[]>;
+defm SMAR64  : RVPMA64<0b1000010, 0b001, "smar64">,
+               Sched<[]>;
+defm SMSLDA  : RVPMA64<0b1010110, 0b001, "smslda">,
+               Sched<[]>;
+defm SMSLXDA : RVPMA64<0b1011110, 0b001, "smslxda">,
+               Sched<[]>;
+defm SMSR64  : RVPMA64<0b1000011, 0b001, "smsr64">,
+               Sched<[]>;
+defm UKMAR64 : RVPMA64<0b1011010, 0b001, "ukmar64">,
+               Sched<[]>;
+defm UKMSR64 : RVPMA64<0b1011011, 0b001, "ukmsr64">,
+               Sched<[]>;
+defm UMAR64  : RVPMA64<0b1010010, 0b001, "umar64">,
+               Sched<[]>;
+defm UMSR64  : RVPMA64<0b1010011, 0b001, "umsr64">,
+               Sched<[]>;
+
+defm WEXT : RVPWEXT<0b1100111, 0b000, "wext">,
+            Sched<[]>;
+
+defm WEXTI : RVPWEXTI<0b1101111, 0b000, "wexti">,
+             Sched<[]>;
+
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZpn] in {
+def : InstAlias<"rdov $rd", (CSRRS  GPR:$rd, SysRegVXSAT.Encoding, X0)>;
+def : InstAlias<"clrov",    (CSRRCI      X0, SysRegVXSAT.Encoding,  1)>;
+
+def : InstAlias<"swap16 $rd, $rs1", (PKBT16 GPR:$rd, GPR:$rs1, GPR:$rs1)>;
+}
+
+let Predicates = [HasStdExtZprvsfextra, IsRV64] in {
+def : InstAlias<"smbb32 $rd, $rs1, $rs2",
+                (MULSR6464 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+def : InstAlias<"kmada32 $rd, $rs1, $rs2",
+                (KMAR6464 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+}

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 def sub_vrm1_1 : SubRegIndex<64, 64>;
 def sub_vrm1_2 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_0>;
 def sub_vrm1_3 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_1>;
 def sub_vrm1_4 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_0>;
 def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>;
 def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>;
 def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
 
+def gpr32_pair_lo : SubRegIndex<32>;
+def gpr32_pair_hi : SubRegIndex<32, 32>;
+
 } // Namespace = "RISCV"
 
 // Integer registers
 // CostPerUse is set higher for registers that may not be compressible as they
 // are not part of GPRC, the most restrictive register class used by the
 // compressed instruction set. This will influence the greedy register
 // allocator to reduce the use of registers that can't be encoded in 16 bit
 // instructions. This affects register allocation even when compressed
def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
   )> {
   let RegInfos = XLenRI;
 }
 
 def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
   let RegInfos = XLenRI;
 }
 
+// Dummy zero register for pairing with X0.
+def REG_PAIR_WITH_X0 : RISCVReg<0, "0">;
+
+def GPR32Pairs : RegisterTuples<[gpr32_pair_lo, gpr32_pair_hi],
+                                [(add X0,  X2,  X4,  X6,
+                                      X8,  X10, X12, X14,
+                                      X16, X18, X20, X22,
+                                      X24, X26, X28, X30),
+                                 (add REG_PAIR_WITH_X0, X3,  X5,  X7,
+                                      X9,               X11, X13, X15,
+                                      X17,              X19, X21, X23,
+                                      X25,              X27, X29, X31)]>;
+
+def GPR32Pair : RegisterClass<"RISCV", [untyped], 64, (add GPR32Pairs)> {
+  let Size = 64;
+}
+
 // Floating point registers
 let RegAltNameIndices = [ABIRegAltName] in {
   def F0_H  : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
   def F1_H  : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>;
   def F2_H  : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>;
   def F3_H  : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>;
   def F4_H  : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>;
   def F5_H  : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>;

llvm/lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZbe = false;
   bool HasStdExtZbf = false;
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZbproposedc = false;
+  bool HasStdExtP = false;
+  bool HasStdExtZpsfoperand = false;
+  bool HasStdExtZpn = false;
+  bool HasStdExtZprvsfextra = false;
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
   bool HasStdExtZfh = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
public:
   bool hasStdExtZbe() const { return HasStdExtZbe; }
   bool hasStdExtZbf() const { return HasStdExtZbf; }
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
+  bool hasStdExtP() const { return HasStdExtP; }
+  bool hasStdExtZpsfoperand() const { return HasStdExtZpsfoperand; }
+  bool hasStdExtZpn() const { return HasStdExtZpn; }
+  bool hasStdExtZprvsfextra() const { return HasStdExtZprvsfextra; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 let AltName = "dscratch" in
 def : SysReg<"dscratch0", 0x7B2>;
 def : SysReg<"dscratch1", 0x7B3>;
 
 //===-----------------------------------------------
 // User Vector CSRs
 //===-----------------------------------------------
 def : SysReg<"vstart", 0x008>;
-def : SysReg<"vxsat", 0x009>;
+def SysRegVXSAT : SysReg<"vxsat", 0x009>;
 def : SysReg<"vxrm", 0x00A>;
 def : SysReg<"vl", 0xC20>;
 def : SysReg<"vtype", 0xC21>;
 def : SysReg<"vlenb", 0xC22>;

llvm/test/MC/RISCV/rv32zpn-only-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-p < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zpn < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 63]
+srai.u a0, a1, 70
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 63]
+bitrevi a0, a1, 70
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+insb a0, a1, 11

llvm/test/MC/RISCV/rv32zpsfoperand-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-p < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zpsfoperand < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# Paired register operand
+
+# CHECK-ERROR: error: expected even register
+smal a0, a1, a2
+
+# CHECK-ERROR: error: expected even register
+add64 a0, a1, a4
+
+# CHECK-ERROR: error: expected even register
+radd64 a0, a2, a3
+
+# CHECK-ERROR: error: expected even register
+uradd64 a0, a1, a4
+
+# CHECK-ERROR: error: expected even register
+kadd64 a0, a2, a3
+
+# CHECK-ERROR: error: expected even register
+ukadd64 a0, a1, a4
+
+# CHECK-ERROR: error: expected even register
+sub64 a0, a1, a4
+
+# CHECK-ERROR: error: expected even register
+rsub64 a0, a2, a3
+
+# CHECK-ERROR: error: expected even register
+ursub64 a0, a1, a4
+
+# CHECK-ERROR: error: expected even register
+ksub64 a0, a2, a3
+
+# CHECK-ERROR: error: expected even register
+uksub64 a0, a1, a4
+
+# CHECK-ERROR: error: expected even register
+smar64 a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+smsr64 a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+umar64 a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+umsr64 a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+kmar64 a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+kmsr64 a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+ukmar64 a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+ukmsr64 a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+smalbb a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+smalbt a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+smaltt s3, s4, s5
+
+# CHECK-ERROR: error: expected even register
+smalda a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+smalxda a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+smalds a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+smaldrs a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+smalxds s3, s4, s5
+
+# CHECK-ERROR: error: expected even register
+smslda a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+smslxda a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+mulr64 a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+mulsr64 a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+umul8 a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+umulx8 a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+umul16 a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+umulx16 a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+smul8 a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+smulx8 a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+smul16 a1, a2, a3
+
+# CHECK-ERROR: error: expected even register
+smulx16 a5, a6, a7
+
+# CHECK-ERROR: error: expected even register
+wexti a0, a1, 16
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+wexti a0, a2, 33
+
+# CHECK-ERROR: error: expected even register
+wext a0, a1, a2
+
+# CHECK-ERROR: error: expected general purpose register
+add64 fa0, a1, a4
+
+# CHECK-ERROR: error: expected general purpose register
+radd64 a0, fa1, a3
+
+# CHECK-ERROR: error: expected general purpose register
+kadd64 a0, a2, fa2

llvm/test/MC/RISCV/rv32zpsfoperand-valid.s

+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zpsfoperand %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpsfoperand %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpsfoperand - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpsfoperand %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# Signed 16-bit Multiply with 64-bit Add/Subtract
+
+# CHECK-INST: smal a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x5e]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 5e <unknown>
+smal a0, a2, a4
+
+# SIMD 64-bit Add/Subtract
+
+# CHECK-INST: add64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 c0 <unknown>
+add64 a0, a2, a4
+
+# CHECK-INST: kadd64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 90 <unknown>
+kadd64 a0, a2, a4
+
+# CHECK-INST: ksub64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 92 <unknown>
+ksub64 a0, a2, a4
+
+# CHECK-INST: radd64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 80 <unknown>
+radd64 a0, a2, a4
+
+# CHECK-INST: rsub64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 82 <unknown>
+rsub64 a0, a2, a4
+
+# CHECK-INST: sub64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 c2 <unknown>
+sub64 a0, a2, a4
+
+# CHECK-INST: ukadd64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 b0 <unknown>
+ukadd64 a0, a2, a4
+
+# CHECK-INST: uksub64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 b2 <unknown>
+uksub64 a0, a2, a4
+
+# CHECK-INST: uradd64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a0 <unknown>
+uradd64 a0, a2, a4
+
+# CHECK-INST: ursub64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a2 <unknown>
+ursub64 a0, a2, a4
+
+# 32-bit Multiply 64-bit Add/Subtract
+
+# CHECK-INST: smar64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 84 <unknown>
+smar64 a0, a2, a4
+
+# CHECK-INST: smsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 86 <unknown>
+smsr64 a0, a2, a4
+
+# CHECK-INST: umar64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a4 <unknown>
+umar64 a0, a2, a4
+
+# CHECK-INST: umsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a6 <unknown>
+umsr64 a0, a2, a4
+
+# CHECK-INST: kmar64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x94]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 94 <unknown>
+kmar64 a0, a2, a4
+
+# CHECK-INST: kmsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x96]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 96 <unknown>
+kmsr64 a0, a2, a4
+
+# CHECK-INST: ukmar64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xb4]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 b4 <unknown>
+ukmar64 a0, a2, a4
+
+# CHECK-INST: ukmsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xb6]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 b6 <unknown>
+ukmsr64 a0, a2, a4
+
+# Signed 16-bit Multiply 64-bit Add/Subtract
+
+# CHECK-INST: smalbb a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 88 <unknown>
+smalbb a0, a2, a4
+
+# CHECK-INST: smalbt a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 98 <unknown>
+smalbt a0, a2, a4
+
+# CHECK-INST: smaltt a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a8 <unknown>
+smaltt a0, a2, a4
+
+# CHECK-INST: smalda a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 8c <unknown>
+smalda a0, a2, a4
+
+# CHECK-INST: smalxda a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x9c]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 9c <unknown>
+smalxda a0, a2, a4
+
+# CHECK-INST: smalds a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 8a <unknown>
+smalds a0, a2, a4
+
+# CHECK-INST: smaldrs a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 9a <unknown>
+smaldrs a0, a2, a4
+
+# CHECK-INST: smalxds a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 aa <unknown>
+smalxds a0, a2, a4
+
+# CHECK-INST: smslda a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 ac <unknown>
+smslda a0, a2, a4
+
+# CHECK-INST: smslxda a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xbc]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 bc <unknown>
+smslxda a0, a2, a4
+
+# 32-bit Computation
+
+# CHECK-INST: mulr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 f0 <unknown>
+mulr64 a0, a2, a4
+
+# CHECK-INST: mulsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 e0 <unknown>
+mulsr64 a0, a2, a4
+
+# SIMD 16-bit Multiply
+
+# CHECK-INST: smul16 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 a0 <unknown>
+smul16 a0, a2, a4
+
+# CHECK-INST: smulx16 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 a2 <unknown>
+smulx16 a0, a2, a4
+
+# CHECK-INST: umul16 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 b0 <unknown>
+umul16 a0, a2, a4
+
+# CHECK-INST: umulx16 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 b2 <unknown>
+umulx16 a0, a2, a4
+
+# SIMD 8-bit Multiply
+
+# CHECK-INST: smul8 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 a8 <unknown>
+smul8 a0, a2, a4
+
+# CHECK-INST: smulx8 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 aa <unknown>
+smulx8 a0, a2, a4
+
+# CHECK-INST: umul8 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 b8 <unknown>
+umul8 a0, a2, a4
+
+# CHECK-INST: umulx8 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 ba <unknown>
+umulx8 a0, a2, a4
+
+# Miscellaneous
+
+# CHECK-INST: wext a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 ce <unknown>
+wext a0, a2, a4
+
+# CHECK-INST: wexti a0, a2, 7
+# CHECK-ENCODING: [0x77,0x05,0x76,0xde]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 76 de <unknown>
+wexti a0, a2, 7
+
+# Test with zero operand
+
+# CHECK-INST: add64 zero, a0, a2
+# CHECK-ENCODING: [0x77,0x10,0xc5,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 10 c5 c0 <unknown>
+add64 zero, a0, a2
+
+# CHECK-INST: add64 a0, zero, a2
+# CHECK-ENCODING: [0x77,0x15,0xc0,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 c0 c0 <unknown>
+add64 a0, zero, a2
+
+# CHECK-INST: add64 a0, a2, zero
+# CHECK-ENCODING: [0x77,0x15,0x06,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 06 c0 <unknown>
+add64 a0, a2, zero
+
+# CHECK-INST: add64 zero, zero, zero
+# CHECK-ENCODING: [0x77,0x10,0x00,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 10 00 c0 <unknown>
+add64 zero, zero, zero

llvm/test/MC/RISCV/rv64zpn-only-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-p < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zpn < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+srai.u a0, a1, 35
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+bitrevi a0, a1, 35
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 3]
+insb a0, a1, 5

llvm/test/MC/RISCV/rv64zprvsfextra-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-p < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zprvsfextra < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# RV64 only
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+srai32 a0, a1, 37
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+srai32.u a0, a1, 37
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+srli32 a0, a1, 37
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+srli32.u a0, a1, 37
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+slli32 a0, a1, 37
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+kslli32 a0, a1, 37

llvm/test/MC/RISCV/rv64zprvsfextra-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zprvsfextra extension:
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RV64P only
+
+# SIMD 32-bit Add/Subtract
+
+# CHECK-INST: add32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 40 <unknown>
+add32 a0, a1, a2
+
+# CHECK-INST: radd32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 00 <unknown>
+radd32 a0, a1, a2
+
+# CHECK-INST: uradd32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 20 <unknown>
+uradd32 a0, a1, a2
+
+# CHECK-INST: add32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x10]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 10 <unknown>
+kadd32 a0, a1, a2
+
+# CHECK-INST: add32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 30 <unknown>
+ukadd32 a0, a1, a2
+
+# CHECK-INST: sub32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 42 <unknown>
+sub32 a0, a1, a2
+
+# CHECK-INST: rsub32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x02]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 02 <unknown>
+rsub32 a0, a1, a2
+
+# CHECK-INST: ursub32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 22 <unknown>
+ursub32 a0, a1, a2
+
+# CHECK-INST: sub32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x12]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 12 <unknown>
+ksub32 a0, a1, a2
+
+# CHECK-INST: sub32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 32 <unknown>
+uksub32 a0, a1, a2
+
+# CHECK-INST: cras32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 44 <unknown>
+cras32 a0, a1, a2
+
+# CHECK-INST: rcras32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 04 <unknown>
+rcras32 a0, a1, a2
+
+# CHECK-INST: urcras32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 24 <unknown>
+urcras32 a0, a1, a2
+
+# CHECK-INST: kcras32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x14]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 14 <unknown>
+kcras32 a0, a1, a2
+
+# CHECK-INST: ukcras32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x34]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 34 <unknown>
+ukcras32 a0, a1, a2
+
+# CHECK-INST: crsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 46 <unknown>
+crsa32 a0, a1, a2
+
+# CHECK-INST: rcrsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x06]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 06 <unknown>
+rcrsa32 a0, a1, a2
+
+urcrsa32 a0, a1, a2
+# CHECK-INST: urcrsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 26 <unknown>
+
+# CHECK-INST: kcrsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x16]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 16 <unknown>
+kcrsa32 a0, a1, a2
+
+# CHECK-INST: ukcrsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x36]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 36 <unknown>
+ukcrsa32 a0, a1, a2
+
+# CHECK-INST: stas32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 f0 <unknown>
+stas32 a0, a1, a2
+
+# CHECK-INST: rstas32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 b0 <unknown>
+rstas32 a0, a1, a2
+
+# CHECK-INST: urstas32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xd0]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 d0 <unknown>
+urstas32 a0, a1, a2
+
+# CHECK-INST: kstas32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xc0]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 c0 <unknown>
+kstas32 a0, a1, a2
+
+# CHECK-INST: ukstas32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 e0 <unknown>
+ukstas32 a0, a1, a2
+
+# CHECK-INST: stsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 f2 <unknown>
+stsa32 a0, a1, a2
+
+# CHECK-INST: rstsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 b2 <unknown>
+rstsa32 a0, a1, a2
+
+# CHECK-INST: urstsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 d2 <unknown>
+urstsa32 a0, a1, a2
+
+# CHECK-INST: kstsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 c2 <unknown>
+kstsa32 a0, a1, a2
+
+# CHECK-INST: ukstsa32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xb5,0xc5,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 b5 c5 e2 <unknown>
+ukstsa32 a0, a1, a2
+
+# SIMD 32-bit Shift
+
+# CHECK-INST: sra32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 50 <unknown>
+sra32 a0, a1, a2
+
+# CHECK-INST: srai32 a0, a1, 19
+# CHECK-ENCODING: [0x77,0xa5,0x35,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 35 71 <unknown>
+srai32 a0, a1, 19
+
+# CHECK-INST: sra32.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 60 <unknown>
+sra32.u a0, a1, a2
+
+# CHECK-INST: srai32.u a0, a1, 16
+# CHECK-ENCODING: [0x77,0xa5,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 05 81 <unknown>
+srai32.u a0, a1, 16
+
+# CHECK-INST: srl32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 52 <unknown>
+srl32 a0, a1, a2
+
+# CHECK-INST: srli32 a0, a1, 9
+# CHECK-ENCODING: [0x77,0xa5,0x95,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 95 72 <unknown>
+srli32 a0, a1, 9
+
+# CHECK-INST: srl32.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 62 <unknown>
+srl32.u a0, a1, a2
+
+# CHECK-INST: srli32.u a0, a1, 15
+# CHECK-ENCODING: [0x77,0xa5,0xf5,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 f5 82 <unknown>
+srli32.u a0, a1, 15
+
+# CHECK-INST: sll32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 54 <unknown>
+sll32 a0, a1, a2
+
+# CHECK-INST: slli32 a0, a1, 23
+# CHECK-ENCODING: [0x77,0xa5,0x75,0x75]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 75 75 <unknown>
+slli32 a0, a1, 23
+
+# CHECK-INST: ksll32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 64 <unknown>
+ksll32 a0, a1, a2
+
+# CHECK-INST: kslli32 a0, a1, 29
+# CHECK-ENCODING: [0x77,0xa5,0xd5,0x85]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 d5 85 <unknown>
+kslli32 a0, a1, 29
+
+# CHECK-INST: kslra32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x56]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 56 <unknown>
+kslra32 a0, a1, a2
+
+# CHECK-INST: kslra32.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 66 <unknown>
+kslra32.u a0, a1, a2
+
+# SIMD 32-bit Miscellaneous
+
+# CHECK-INST: smin32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 90 <unknown>
+smin32 a0, a1, a2
+
+# CHECK-INST: umin32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 a0 <unknown>
+umin32 a0, a1, a2
+
+# CHECK-INST: smax32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 92 <unknown>
+smax32 a0, a1, a2
+
+# CHECK-INST: umax32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 a2 <unknown>
+umax32 a0, a1, a2
+
+# CHECK-INST: kabs32 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x25,0xad]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 25 ad <unknown>
+kabs32 a0, a1
+
+# SIMD Q15 saturating Multiply
+
+# CHECK-INST: khmbb16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xdc]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 dc <unknown>
+khmbb16 a0, a1, a2
+
+# CHECK-INST: khmbt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xec]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 ec <unknown>
+khmbt16 a0, a1, a2
+
+# CHECK-INST: khmtt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xfc]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 fc <unknown>
+khmtt16 a0, a1, a2
+
+# CHECK-INST: kdmbb16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 da <unknown>
+kdmbb16 a0, a1, a2
+
+# CHECK-INST: kdmbt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 ea <unknown>
+kdmbt16 a0, a1, a2
+
+# CHECK-INST: kdmtt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 fa <unknown>
+kdmtt16 a0, a1, a2
+
+# CHECK-INST: kdmabb16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 d8 <unknown>
+kdmabb16 a0, a1, a2
+
+# CHECK-INST: kdmabt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 e8 <unknown>
+kdmabt16 a0, a1, a2
+
+# CHECK-INST: kdmatt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 f8 <unknown>
+kdmatt16 a0, a1, a2
+
+# 32-bit Multiply
+
+# CHECK-INST: smbb32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 e0 <unknown>
+smbb32 a0, a1, a2
+
+# CHECK-INST: smbt32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x18]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 18 <unknown>
+smbt32 a0, a1, a2
+
+# CHECK-INST: smtt32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 28 <unknown>
+smtt32 a0, a1, a2
+
+# 32-bit Multiply & Add
+
+# CHECK-INST: kmabb32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 5a <unknown>
+kmabb32 a0, a1, a2
+
+# CHECK-INST: kmabt32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 6a <unknown>
+kmabt32 a0, a1, a2
+
+# CHECK-INST: kmatt32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 7a <unknown>
+kmatt32 a0, a1, a2
+
+# CHECK-INST: kmda32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 38 <unknown>
+kmda32 a0, a1, a2
+
+# CHECK-INST: kmxda32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 3a <unknown>
+kmxda32 a0, a1, a2
+
+# CHECK-INST: kmada32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x94]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 94 <unknown>
+kmada32 a0, a1, a2
+
+# CHECK-INST: kmaxda32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 4a <unknown>
+kmaxda32 a0, a1, a2
+
+# CHECK-INST: kmads32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x5c]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 5c <unknown>
+kmads32 a0, a1, a2
+
+# CHECK-INST: kmadrs32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 6c <unknown>
+kmadrs32 a0, a1, a2
+
+# CHECK-INST: kmaxds32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x7c]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 7c <unknown>
+kmaxds32 a0, a1, a2
+
+# CHECK-INST: kmsda32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 4c <unknown>
+kmsda32 a0, a1, a2
+
+# CHECK-INST: kmsxda32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 4e <unknown>
+kmsxda32 a0, a1, a2
+
+# CHECK-INST: smds32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 58 <unknown>
+smds32 a0, a1, a2
+
+# CHECK-INST: smdrs32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 68 <unknown>
+smdrs32 a0, a1, a2
+
+# CHECK-INST: smxds32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 78 <unknown>
+smxds32 a0, a1, a2
+
+# Non-SIMD 32-bit Shift
+
+# CHECK-INST: sraiw.u a0, a1, 17
+# CHECK-ENCODING: [0x77,0x95,0x15,0x35]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 15 35 <unknown>
+sraiw.u a0, a1, 17
+
+# 32-bit Packing
+
+# CHECK-INST: pkbb32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x0e]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 0e <unknown>
+pkbb32 a0, a1, a2
+
+# CHECK-INST: pkbt32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x1e]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 1e <unknown>
+pkbt32 a0, a1, a2
+
+# CHECK-INST: pktb32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x3e]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 3e <unknown>
+pktb32 a0, a1, a2
+
+# CHECK-INST: pktt32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zprvsfextra' (RV64 only 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 2e <unknown>
+pktt32 a0, a1, a2

llvm/test/MC/RISCV/rv64zpsfoperand-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-p < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zpsfoperand < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+wexti a0, a1, 33

llvm/test/MC/RISCV/rv64zpsfoperand-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p -riscv-no-aliases %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p -M no-aliases - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zpsfoperand extension:
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zpsfoperand %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpsfoperand %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpsfoperand - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpsfoperand %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# Signed 16-bit Multiply with 64-bit Add/Subtract
+
+# CHECK-INST: smal a1, a2, a3
+# CHECK-ENCODING: [0xf7,0x15,0xd6,0x5e]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: f7 15 d6 5e <unknown>
+smal a1, a2, a3
+
+# SIMD 64-bit Add/Subtract
+
+# CHECK-INST: add64 a4, a5, a6
+# CHECK-ENCODING: [0x77,0x97,0x07,0xc1]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 97 07 c1 <unknown>
+add64 a4, a5, a6
+
+# CHECK-INST: kadd64 a1, a2, a3
+# CHECK-ENCODING: [0xf7,0x15,0xd6,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: f7 15 d6 90 <unknown>
+kadd64 a1, a2, a3
+
+# CHECK-INST: ksub64 a4, a5, a6
+# CHECK-ENCODING: [0x77,0x97,0x07,0x93]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 97 07 93 <unknown>
+ksub64 a4, a5, a6
+
+# CHECK-INST: radd64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 80 <unknown>
+radd64 a0, a2, a4
+
+# CHECK-INST: rsub64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 82 <unknown>
+rsub64 a0, a2, a4
+
+# CHECK-INST: sub64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xc2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 c2 <unknown>
+sub64 a0, a2, a4
+
+# CHECK-INST: ukadd64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 b0 <unknown>
+ukadd64 a0, a2, a4
+
+# CHECK-INST: uksub64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 b2 <unknown>
+uksub64 a0, a2, a4
+
+# CHECK-INST: uradd64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a0 <unknown>
+uradd64 a0, a2, a4
+
+# CHECK-INST: ursub64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a2 <unknown>
+ursub64 a0, a2, a4
+
+# 32-bit Multiply 64-bit Add/Subtract
+
+# CHECK-INST: smar64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 84 <unknown>
+smar64 a0, a2, a4
+
+# CHECK-INST: smsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 86 <unknown>
+smsr64 a0, a2, a4
+
+# CHECK-INST: umar64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa4]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a4 <unknown>
+umar64 a0, a2, a4
+
+# CHECK-INST: umsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a6 <unknown>
+umsr64 a0, a2, a4
+
+# CHECK-INST: kmar64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x94]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 94 <unknown>
+kmar64 a0, a2, a4
+
+# CHECK-INST: kmsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x96]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 96 <unknown>
+kmsr64 a0, a2, a4
+
+# CHECK-INST: ukmar64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xb4]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 b4 <unknown>
+ukmar64 a0, a2, a4
+
+# CHECK-INST: ukmsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xb6]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 b6 <unknown>
+ukmsr64 a0, a2, a4
+
+# Signed 16-bit Multiply 64-bit Add/Subtract
+
+# CHECK-INST: smalbb a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 88 <unknown>
+smalbb a0, a2, a4
+
+# CHECK-INST: smalbt a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 98 <unknown>
+smalbt a0, a2, a4
+
+# CHECK-INST: smaltt a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 a8 <unknown>
+smaltt a0, a2, a4
+
+# CHECK-INST: smalda a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 8c <unknown>
+smalda a0, a2, a4
+
+# CHECK-INST: smalxda a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x9c]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 9c <unknown>
+smalxda a0, a2, a4
+
+# CHECK-INST: smalds a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 8a <unknown>
+smalds a0, a2, a4
+
+# CHECK-INST: smaldrs a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 9a <unknown>
+smaldrs a0, a2, a4
+
+# CHECK-INST: smalxds a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 aa <unknown>
+smalxds a0, a2, a4
+
+# CHECK-INST: smslda a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 ac <unknown>
+smslda a0, a2, a4
+
+# CHECK-INST: smslxda a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xbc]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 bc <unknown>
+smslxda a0, a2, a4
+
+# 32-bit Computation
+
+# CHECK-INST: mulr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 f0 <unknown>
+mulr64 a0, a2, a4
+
+# CHECK-INST: mulsr64 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x15,0xe6,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 15 e6 e0 <unknown>
+mulsr64 a0, a2, a4
+
+# SIMD 16-bit Multiply
+
+# CHECK-INST: smul16 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xa0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 a0 <unknown>
+smul16 a0, a2, a4
+
+# CHECK-INST: smulx16 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 a2 <unknown>
+smulx16 a0, a2, a4
+
+# CHECK-INST: umul16 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xb0]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 b0 <unknown>
+umul16 a0, a2, a4
+
+# CHECK-INST: umulx16 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 b2 <unknown>
+umulx16 a0, a2, a4
+
+# SIMD 8-bit Multiply
+
+# CHECK-INST: smul8 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xa8]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 a8 <unknown>
+smul8 a0, a2, a4
+
+# CHECK-INST: smulx8 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 aa <unknown>
+smulx8 a0, a2, a4
+
+# CHECK-INST: umul8 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xb8]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 b8 <unknown>
+umul8 a0, a2, a4
+
+# CHECK-INST: umulx8 a0, a2, a4
+# CHECK-ENCODING: [0x77,0x05,0xe6,0xba]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 05 e6 ba <unknown>
+umulx8 a0, a2, a4
+
+# Miscellaneous
+
+# CHECK-INST: wext a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 ce <unknown>
+wext a0, a1, a2
+
+# CHECK-INST: wexti a0, a1, 7
+# CHECK-ENCODING: [0x77,0x85,0x75,0xde]
+# CHECK-ERROR: instruction requires the following: 'Zpsfoperand' (Paired-register operand 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 75 de <unknown>
+wexti a0, a1, 7

llvm/test/MC/RISCV/rvp-invalid.s

+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-p < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zpn < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-p < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zpn < %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+# 16-bit shift
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+srai16 a0, a1, 21
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+srai16.u a0, a1, 21
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+srli16 a0, a1, 21
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+srli16.u a0, a1, 21
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+slli16 a0, a1, 21
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+kslli16 a0, a1, 21
+
+# 8-bit shift
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+srai8 a0, a1, 8
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+srai8.u a0, a1, 9
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+srli8 a0, a1, 8
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+srli8.u a0, a1, 9
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+slli8 a0, a1, 8
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+kslli8 a0, a1, 9
+
+# Misc
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+sclip8 a0, a1, 8
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
+uclip8 a0, a1, 8
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+sclip16 a0, a1, 21
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 15]
+uclip16 a0, a1, 21
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+sclip32 a0, a1, 37
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+uclip32 a0, a1, 37
+
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+kslliw a0, a1, 37

llvm/test/MC/RISCV/rvp-non-simd-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zpn extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# Non-SIMD Q15 saturation ALU
+
+# CHECK-INST: kaddh a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 04 <unknown>
+kaddh a0, a1, a2
+
+# CHECK-INST: ksubh a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x06]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 06 <unknown>
+ksubh a0, a1, a2
+
+# CHECK-INST: khmbb a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x0c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 0c <unknown>
+khmbb a0, a1, a2
+
+# CHECK-INST: khmbt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x1c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 1c <unknown>
+khmbt a0, a1, a2
+
+# CHECK-INST: khmtt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 2c <unknown>
+khmtt a0, a1, a2
+
+# CHECK-INST: ukaddh a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x14]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 14 <unknown>
+ukaddh a0, a1, a2
+
+# CHECK-INST: uksubh a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x16]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 16 <unknown>
+uksubh a0, a1, a2
+
+# Non-SIMD Q31 saturation ALU
+
+# CHECK-INST: kaddw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 00 <unknown>
+kaddw a0, a1, a2
+
+# CHECK-INST: ukaddw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x10]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 10 <unknown>
+ukaddw a0, a1, a2
+
+# CHECK-INST: ksubw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x02]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 02 <unknown>
+ksubw a0, a1, a2
+
+# CHECK-INST: uksubw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x12]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 12 <unknown>
+uksubw a0, a1, a2
+
+# CHECK-INST: kdmbb a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 0a <unknown>
+kdmbb a0, a1, a2
+
+# CHECK-INST: kdmbt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 1a <unknown>
+kdmbt a0, a1, a2
+
+# CHECK-INST: kdmtt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 2a <unknown>
+kdmtt a0, a1, a2
+
+# CHECK-INST: kslraw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 6e <unknown>
+kslraw a0, a1, a2
+
+# CHECK-INST: kslraw.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x7e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 7e <unknown>
+kslraw.u a0, a1, a2
+
+# CHECK-INST: ksllw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 26 <unknown>
+ksllw a0, a1, a2
+
+# CHECK-INST: kslliw a0, a1, 31
+# CHECK-ENCODING: [0x77,0x95,0xf5,0x37]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 f5 37 <unknown>
+kslliw a0, a1, 31
+
+# CHECK-INST: kdmabb a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xd2]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 d2 <unknown>
+kdmabb a0, a1, a2
+
+# CHECK-INST: kdmabt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xe2]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 e2 <unknown>
+kdmabt a0, a1, a2
+
+# CHECK-INST: kdmatt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 f2 <unknown>
+kdmatt a0, a1, a2
+
+# CHECK-INST: kabsw a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x45,0xad]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 45 ad <unknown>
+kabsw a0, a1
+
+# 32-bit Computation
+
+# CHECK-INST: raddw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 20 <unknown>
+raddw a0, a1, a2
+
+# CHECK-INST: uraddw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 30 <unknown>
+uraddw a0, a1, a2
+
+# CHECK-INST: rsubw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 22 <unknown>
+rsubw a0, a1, a2
+
+# CHECK-INST: ursubw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 32 <unknown>
+ursubw a0, a1, a2
+
+# CHECK-INST: maxw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xf2]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 f2 <unknown>
+maxw a0, a1, a2
+
+# CHECK-INST: minw a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xf0]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 f0 <unknown>
+minw a0, a1, a2
+
+# Overflow/Saturation status manipulation
+
+# CHECK-INST: csrr a5, vxsat
+# CHECK-ENCODING: [0xf3,0x27,0x90,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: f3 27 90 00 csrr a5, vxsat
+rdov a5
+
+# CHECK-INST: csrci vxsat, 1
+# CHECK-ENCODING: [0x73,0xf0,0x90,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 73 f0 90 00 csrci vxsat, 1
+clrov
+
+# Miscellaneous
+
+# CHECK-INST: ave a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xe0]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 e0 <unknown>
+ave a0, a1, a2
+
+# CHECK-INST: sra.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 24 <unknown>
+sra.u a0, a1, a2
+
+# CHECK-INST: srai.u a0, a1, 9
+# CHECK-ENCODING: [0x77,0x95,0x95,0xd4]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 95 d4 <unknown>
+srai.u a0, a1, 9
+
+# CHECK-INST: bitrev a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 e6 <unknown>
+bitrev a0, a1, a2
+
+# CHECK-INST: bitrevi a0, a1, 7
+# CHECK-ENCODING: [0x77,0x85,0x75,0xe8]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 75 e8 <unknown>
+bitrevi a0, a1, 7
+
+# CHECK-INST: bpick a0, a1, a2, a3
+# CHECK-ENCODING: [0x77,0xb5,0xc5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 b5 c5 68 <unknown>
+bpick a0, a1, a2, a3
+
+# CHECK-INST: insb a0, a1, 3
+# CHECK-ENCODING: [0x77,0x85,0x35,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 35 ac <unknown>
+insb a0, a1, 3
+
+# CHECK-INST: maddr32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 c4 <unknown>
+maddr32 a0, a1, a2
+
+# CHECK-INST: msubr32 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 c6 <unknown>
+msubr32 a0, a1, a2

llvm/test/MC/RISCV/rvp-partial-simd-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zpn extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# 16-bit Packing
+
+# CHECK-INST: pkbb16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x0e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 0e <unknown>
+pkbb16 a0, a1, a2
+
+# CHECK-INST: pkbt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x1e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 1e <unknown>
+pkbt16 a0, a1, a2
+
+# CHECK-INST: pktb16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x3e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 3e <unknown>
+pktb16 a0, a1, a2
+
+# CHECK-INST: pktt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 2e <unknown>
+pktt16 a0, a1, a2
+
+# Signed MSW 32x32 Multiply and Add
+
+# CHECK-INST: smmul a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 40 <unknown>
+smmul a0, a1, a2
+
+# CHECK-INST: smmul.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 50 <unknown>
+smmul.u a0, a1, a2
+
+# CHECK-INST: kmmac a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 60 <unknown>
+kmmac a0, a1, a2
+
+# CHECK-INST: kmmac.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 70 <unknown>
+kmmac.u a0, a1, a2
+
+# CHECK-INST: kmmsb a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 42 <unknown>
+kmmsb a0, a1, a2
+
+# CHECK-INST: kmmsb.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 52 <unknown>
+kmmsb.u a0, a1, a2
+
+# CHECK-INST: kwmmul a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 62 <unknown>
+kwmmul a0, a1, a2
+
+# CHECK-INST: kwmmul.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 72 <unknown>
+kwmmul.u a0, a1, a2
+
+# Signed MSW 32x16 Multiply and Add
+
+# CHECK-INST: smmwb a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 44 <unknown>
+smmwb a0, a1, a2
+
+# CHECK-INST: smmwb.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 54 <unknown>
+smmwb.u a0, a1, a2
+
+# CHECK-INST: smmwt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 64 <unknown>
+smmwt a0, a1, a2
+
+# CHECK-INST: smmwt.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x74]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 74 <unknown>
+smmwt.u a0, a1, a2
+
+# CHECK-INST: kmmawb a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 46 <unknown>
+kmmawb a0, a1, a2
+
+# CHECK-INST: kmmawb.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x56]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 56 <unknown>
+kmmawb.u a0, a1, a2
+
+# CHECK-INST: kmmawt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 66 <unknown>
+kmmawt a0, a1, a2
+
+# CHECK-INST: kmmawt.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x76]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 76 <unknown>
+kmmawt.u a0, a1, a2
+
+# CHECK-INST: kmmwb2 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 8e <unknown>
+kmmwb2 a0, a1, a2
+
+# CHECK-INST: kmmwb2.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x9e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 9e <unknown>
+kmmwb2.u a0, a1, a2
+
+# CHECK-INST: kmmwt2 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 ae <unknown>
+kmmwt2 a0, a1, a2
+
+# CHECK-INST: kmmwt2.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xbe]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 be <unknown>
+kmmwt2.u a0, a1, a2
+
+# CHECK-INST: kmmawb2 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xce]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 ce <unknown>
+kmmawb2 a0, a1, a2
+
+# CHECK-INST: kmmawb2.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xde]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 de <unknown>
+kmmawb2.u a0, a1, a2
+
+# CHECK-INST: kmmawt2 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 ee <unknown>
+kmmawt2 a0, a1, a2
+
+# CHECK-INST: kmmawt2.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0xfe]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 fe <unknown>
+kmmawt2.u a0, a1, a2
+
+# Signed 16-bit Multiply with 32-bit Add/Subtract
+
+# CHECK-INST: smbb16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x08]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 08 <unknown>
+smbb16 a0, a1, a2
+
+# CHECK-INST: smbt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x18]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 18 <unknown>
+smbt16 a0, a1, a2
+
+# CHECK-INST: smtt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 28 <unknown>
+smtt16 a0, a1, a2
+
+# CHECK-INST: kmda a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 38 <unknown>
+kmda a0, a1, a2
+
+# CHECK-INST: kmxda a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 3a <unknown>
+kmxda a0, a1, a2
+
+# CHECK-INST: smds a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 58 <unknown>
+smds a0, a1, a2
+
+# CHECK-INST: smdrs a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 68 <unknown>
+smdrs a0, a1, a2
+
+# CHECK-INST: smxds a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 78 <unknown>
+smxds a0, a1, a2
+
+# CHECK-INST: kmabb a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 5a <unknown>
+kmabb a0, a1, a2
+
+# CHECK-INST: kmabt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 6a <unknown>
+kmabt a0, a1, a2
+
+# CHECK-INST: kmatt a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 7a <unknown>
+kmatt a0, a1, a2
+
+# CHECK-INST: kmada a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 48 <unknown>
+kmada a0, a1, a2
+
+# CHECK-INST: kmaxda a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 4a <unknown>
+kmaxda a0, a1, a2
+
+# CHECK-INST: kmads a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x5c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 5c <unknown>
+kmads a0, a1, a2
+
+# CHECK-INST: kmadrs a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 6c <unknown>
+kmadrs a0, a1, a2
+
+# CHECK-INST: kmaxds a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x7c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 7c <unknown>
+kmaxds a0, a1, a2
+
+# CHECK-INST: kmsda a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 4c <unknown>
+kmsda a0, a1, a2
+
+# CHECK-INST: kmsxda a0, a1, a2
+# CHECK-ENCODING: [0x77,0x95,0xc5,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 c5 4e <unknown>
+kmsxda a0, a1, a2
+
+# Miscellaneous
+
+# CHECK-INST: sclip32 a0, a1, 21
+# CHECK-ENCODING: [0x77,0x85,0x55,0xe5]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 55 e5 <unknown>
+sclip32 a0, a1, 21
+
+# CHECK-INST: uclip32 a0, a1, 19
+# CHECK-ENCODING: [0x77,0x85,0x35,0xf5]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 35 f5 <unknown>
+uclip32 a0, a1, 19
+
+# CHECK-INST: clrs32 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x85,0xaf]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 85 af <unknown>
+clrs32 a0, a1
+
+# CHECK-INST: clz32 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x95,0xaf]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 95 af <unknown>
+clz32 a0, a1
+
+# CHECK-INST: clo32 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0xb5,0xaf]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 b5 af <unknown>
+clo32 a0, a1
+
+# CHECK-INST: pbsad a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xfc]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 fc <unknown>
+pbsad a0, a1, a2
+
+# CHECK-INST: pbsada a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xfe]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 fe <unknown>
+pbsada a0, a1, a2
+
+# 8-bit Multiply with 32-bit Add
+
+# CHECK-INST: smaqa a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 c8 <unknown>
+smaqa a0, a1, a2
+
+# CHECK-INST: umaqa a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xcc]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 cc <unknown>
+umaqa a0, a1, a2
+
+# CHECK-INST: smaqa.su a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xca]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 ca <unknown>
+smaqa.su a0, a1, a2

llvm/test/MC/RISCV/rvp-simd-alu-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zpn extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# SIMD 16-bit Add/Subtract
+
+# CHECK-INST: add16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x40]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 40 <unknown>
+add16 a0, a1, a2
+
+# CHECK-INST: radd16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 00 <unknown>
+radd16 a0, a1, a2
+
+# CHECK-INST: uradd16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x20]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 20 <unknown>
+uradd16 a0, a1, a2
+
+# CHECK-INST: kadd16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x10]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 10 <unknown>
+kadd16 a0, a1, a2
+
+# CHECK-INST: ukadd16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x30]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 30 <unknown>
+ukadd16 a0, a1, a2
+
+# CHECK-INST: sub16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x42]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 42 <unknown>
+sub16 a0, a1, a2
+
+# CHECK-INST: rsub16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x02]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 02 <unknown>
+rsub16 a0, a1, a2
+
+# CHECK-INST: ursub16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x22]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 22 <unknown>
+ursub16 a0, a1, a2
+
+# CHECK-INST: ksub16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x12]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 12 <unknown>
+ksub16 a0, a1, a2
+
+# CHECK-INST: uksub16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 32 <unknown>
+uksub16 a0, a1, a2
+
+# CHECK-INST: cras16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x44]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 44 <unknown>
+cras16 a0, a1, a2
+
+# CHECK-INST: rcras16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 04 <unknown>
+rcras16 a0, a1, a2
+
+# CHECK-INST: urcras16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x24]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 24 <unknown>
+urcras16 a0, a1, a2
+
+# CHECK-INST: kcras16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x14]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 14 <unknown>
+kcras16 a0, a1, a2
+
+# CHECK-INST: ukcras16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x34]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 34 <unknown>
+ukcras16 a0, a1, a2
+
+# CHECK-INST: crsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x46]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 46 <unknown>
+crsa16 a0, a1, a2
+
+# CHECK-INST: rcrsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x06]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 06 <unknown>
+rcrsa16 a0, a1, a2
+
+# CHECK-INST: urcrsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x26]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 26 <unknown>
+urcrsa16 a0, a1, a2
+
+# CHECK-INST: kcrsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x16]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 16 <unknown>
+kcrsa16 a0, a1, a2
+
+# CHECK-INST: ukcrsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x36]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 36 <unknown>
+ukcrsa16 a0, a1, a2
+
+# CHECK-INST: stas16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xf4]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 f4 <unknown>
+stas16 a0, a1, a2
+
+# CHECK-INST: rstas16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xb4]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 b4 <unknown>
+rstas16 a0, a1, a2
+
+# CHECK-INST: urstas16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xd4]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 d4 <unknown>
+urstas16 a0, a1, a2
+
+# CHECK-INST: kstas16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xc4]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 c4 <unknown>
+kstas16 a0, a1, a2
+
+# CHECK-INST: ukstas16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 e4 <unknown>
+ukstas16 a0, a1, a2
+
+# CHECK-INST: stsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xf6]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 f6 <unknown>
+stsa16 a0, a1, a2
+
+# CHECK-INST: rstsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xb6]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 b6 <unknown>
+rstsa16 a0, a1, a2
+
+# CHECK-INST: urstsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xd6]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 d6 <unknown>
+urstsa16 a0, a1, a2
+
+# CHECK-INST: kstsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xc6]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 c6 <unknown>
+kstsa16 a0, a1, a2
+
+# CHECK-INST: ukstsa16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0xa5,0xc5,0xe6]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 a5 c5 e6 <unknown>
+ukstsa16 a0, a1, a2
+
+# SIMD 8-bit Add/Subtract
+
+# CHECK-INST: add8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 48 <unknown>
+add8 a0, a1, a2
+
+# CHECK-INST: radd8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x08]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 08 <unknown>
+radd8 a0, a1, a2
+
+# CHECK-INST: uradd8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 28 <unknown>
+uradd8 a0, a1, a2
+
+# CHECK-INST: kadd8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x18]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 18 <unknown>
+kadd8 a0, a1, a2
+
+# CHECK-INST: ukadd8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x38]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 38 <unknown>
+ukadd8 a0, a1, a2
+
+# CHECK-INST: sub8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 4a <unknown>
+sub8 a0, a1, a2
+
+# CHECK-INST: rsub8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 0a <unknown>
+rsub8 a0, a1, a2
+
+# CHECK-INST: ursub8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 2a <unknown>
+ursub8 a0, a1, a2
+
+# CHECK-INST: ksub8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 1a <unknown>
+ksub8 a0, a1, a2
+
+# CHECK-INST: uksub8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 3a <unknown>
+uksub8 a0, a1, a2

llvm/test/MC/RISCV/rvp-simd-cmp-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zpn extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# SIMD 16-bit Compare
+
+# CHECK-INST: cmpeq16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x4c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 4c <unknown>
+cmpeq16 a0, a1, a2
+
+# CHECK-INST: scmplt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x0c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 0c <unknown>
+scmplt16 a0, a1, a2
+
+# CHECK-INST: scmple16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x1c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 1c <unknown>
+scmple16 a0, a1, a2
+
+# CHECK-INST: ucmplt16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 2c <unknown>
+ucmplt16 a0, a1, a2
+
+# CHECK-INST: ucmple16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x3c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 3c <unknown>
+ucmple16 a0, a1, a2
+
+# SIMD 8-bit Compare
+
+# CHECK-INST: cmpeq8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x4e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 4e <unknown>
+cmpeq8 a0, a1, a2
+
+# CHECK-INST: scmplt8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x0e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 0e <unknown>
+scmplt8 a0, a1, a2
+
+# CHECK-INST: scmple8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x1e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 1e <unknown>
+scmple8 a0, a1, a2
+
+# CHECK-INST: ucmplt8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 2e <unknown>
+ucmplt8 a0, a1, a2
+
+# CHECK-INST: ucmple8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x3e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 3e <unknown>
+ucmple8 a0, a1, a2

llvm/test/MC/RISCV/rvp-simd-misc-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zpn extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# SIMD 16-bit Miscellaneous
+
+# CHECK-INST: smin16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x80]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 80 <unknown>
+smin16 a0, a1, a2
+
+# CHECK-INST: umin16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x90]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 90 <unknown>
+umin16 a0, a1, a2
+
+# CHECK-INST: smax16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 82 <unknown>
+smax16 a0, a1, a2
+
+# CHECK-INST: umax16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x92]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 92 <unknown>
+umax16 a0, a1, a2
+
+# CHECK-INST: sclip16 a0, a1, 7
+# CHECK-ENCODING: [0x77,0x85,0x75,0x84]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 75 84 <unknown>
+sclip16 a0, a1, 7
+
+# CHECK-INST: uclip16 a0, a1, 8
+# CHECK-ENCODING: [0x77,0x85,0x85,0x85]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 85 85 <unknown>
+uclip16 a0, a1, 8
+
+# CHECK-INST: kabs16 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x15,0xad]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 15 ad <unknown>
+kabs16 a0, a1
+
+# CHECK-INST: clrs16 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x85,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 85 ae <unknown>
+clrs16 a0, a1
+
+# CHECK-INST: clz16 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x95,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 95 ae <unknown>
+clz16 a0, a1
+
+# CHECK-INST: clo16 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0xb5,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 b5 ae <unknown>
+clo16 a0, a1
+
+# CHECK-INST: swap16 a0, a1
+# CHECK-ENCODING: [0x77,0x95,0xb5,0x1e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 95 b5 1e <unknown>
+swap16 a0, a1
+
+# SIMD 8-bit Miscellaneous
+
+# CHECK-INST: smin8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x88]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 88 <unknown>
+smin8 a0, a1, a2
+
+# CHECK-INST: umin8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x98]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 98 <unknown>
+umin8 a0, a1, a2
+
+# CHECK-INST: smax8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 8a <unknown>
+smax8 a0, a1, a2
+
+# CHECK-INST: umax8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 9a <unknown>
+umax8 a0, a1, a2
+
+# CHECK-INST: sclip8 a0, a1, 4
+# CHECK-ENCODING: [0x77,0x85,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 45 8c <unknown>
+sclip8 a0, a1, 4
+
+# CHECK-INST: uclip8 a0, a1, 5
+# CHECK-ENCODING: [0x77,0x85,0x55,0x8d]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 55 8d <unknown>
+uclip8 a0, a1, 5
+
+# CHECK-INST: kabs8 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x05,0xad]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 05 ad <unknown>
+kabs8 a0, a1
+
+# CHECK-INST: clrs8 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x05,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 05 ae <unknown>
+clrs8 a0, a1
+
+# CHECK-INST: clz8 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x15,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 15 ae <unknown>
+clz8 a0, a1
+
+# CHECK-INST: clo8 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x35,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 35 ae <unknown>
+clo8 a0, a1
+
+# CHECK-INST: swap8 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x85,0xad]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 85 ad <unknown>
+swap8 a0, a1

llvm/test/MC/RISCV/rvp-simd-mul-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zpn extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# SIMD 16-bit Multiply
+
+# CHECK-INST: khm16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 86 <unknown>
+khm16 a0, a1, a2
+
+# CHECK-INST: khmx16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x96]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 96 <unknown>
+khmx16 a0, a1, a2
+
+# SIMD 8-bit Multiply
+
+# CHECK-INST: khm8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 8e <unknown>
+khm8 a0, a1, a2
+
+# CHECK-INST: khmx8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x9e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 9e <unknown>
+khmx8 a0, a1, a2

llvm/test/MC/RISCV/rvp-simd-shift-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zpn extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# SIMD 16-bit Shift
+
+# CHECK-INST: sra16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 50 <unknown>
+sra16 a0, a1, a2
+
+# CHECK-INST: srai16 a0, a1, 3
+# CHECK-ENCODING: [0x77,0x85,0x35,0x70]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 35 70 <unknown>
+srai16 a0, a1, 3
+
+# CHECK-INST: sra16.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x60]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 60 <unknown>
+sra16.u a0, a1, a2
+
+# CHECK-INST: srai16.u a0, a1, 4
+# CHECK-ENCODING: [0x77,0x85,0x45,0x71]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 45 71 <unknown>
+srai16.u a0, a1, 4
+
+# CHECK-INST: srl16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x52]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 52 <unknown>
+srl16 a0, a1, a2
+
+# CHECK-INST: srli16 a0, a1, 9
+# CHECK-ENCODING: [0x77,0x85,0x95,0x72]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 95 72 <unknown>
+srli16 a0, a1, 9
+
+# CHECK-INST: srl16.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x62]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 62 <unknown>
+srl16.u a0, a1, a2
+
+# CHECK-INST: srli16.u a0, a1, 10
+# CHECK-ENCODING: [0x77,0x85,0xa5,0x73]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 a5 73 <unknown>
+srli16.u a0, a1, 10
+
+# CHECK-INST: sll16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 54 <unknown>
+sll16 a0, a1, a2
+
+# CHECK-INST: slli16 a0, a1, 8
+# CHECK-ENCODING: [0x77,0x85,0x85,0x74]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 85 74 <unknown>
+slli16 a0, a1, 8
+
+# CHECK-INST: ksll16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x64]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 64 <unknown>
+ksll16 a0, a1, a2
+
+# CHECK-INST: kslli16 a0, a1, 5
+# CHECK-ENCODING: [0x77,0x85,0x55,0x75]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 55 75 <unknown>
+kslli16 a0, a1, 5
+
+# CHECK-INST: kslra16 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x56]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 56 <unknown>
+kslra16 a0, a1, a2
+
+# CHECK-INST: kslra16.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 66 <unknown>
+kslra16.u a0, a1, a2
+
+# SIMD 8-bit Shift
+
+# CHECK-INST: sra8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x58]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 58 <unknown>
+sra8 a0, a1, a2
+
+# CHECK-INST: srai8 a0, a1, 1
+# CHECK-ENCODING: [0x77,0x85,0x15,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 15 78 <unknown>
+srai8 a0, a1, 1
+
+# CHECK-INST: sra8.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x68]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 68 <unknown>
+sra8.u a0, a1, a2
+
+# CHECK-INST: srai8.u a0, a1, 2
+# CHECK-ENCODING: [0x77,0x85,0xa5,0x78]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 a5 78 <unknown>
+srai8.u a0, a1, 2
+
+# CHECK-INST: srl8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 5a <unknown>
+srl8 a0, a1, a2
+
+# CHECK-INST: srli8 a0, a1, 3
+# CHECK-ENCODING: [0x77,0x85,0x35,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 35 7a <unknown>
+srli8 a0, a1, 3
+
+# CHECK-INST: srl8.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 6a <unknown>
+srl8.u a0, a1, a2
+
+# CHECK-INST: srli8.u a0, a1, 4
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 7a <unknown>
+srli8.u a0, a1, 4
+
+# CHECK-INST: sll8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x5c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 5c <unknown>
+sll8 a0, a1, a2
+
+# CHECK-INST: slli8 a0, a1, 1
+# CHECK-ENCODING: [0x77,0x85,0x15,0x7c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 15 7c <unknown>
+slli8 a0, a1, 1
+
+# CHECK-INST: ksll8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x6c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 6c <unknown>
+ksll8 a0, a1, a2
+
+# CHECK-INST: kslli8 a0, a1, 6
+# CHECK-ENCODING: [0x77,0x85,0xe5,0x7c]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 e5 7c <unknown>
+kslli8 a0, a1, 6
+
+# CHECK-INST: kslra8 a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x5e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 5e <unknown>
+kslra8 a0, a1, a2
+
+# CHECK-INST: kslra8.u a0, a1, a2
+# CHECK-ENCODING: [0x77,0x85,0xc5,0x6e]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 6e <unknown>
+kslra8.u a0, a1, a2

llvm/test/MC/RISCV/rvp-simd-unpacking-valid.s

+# With P extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-p %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-p - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-p %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# With Zpn extension:
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zpn %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zpn - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zpn %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# 8-bit Unpacking
+
+# CHECK-INST: sunpkd810 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x85,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 85 ac <unknown>
+sunpkd810 a0, a1
+
+# CHECK-INST: sunpkd820 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x95,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 95 ac <unknown>
+sunpkd820 a0, a1
+
+# CHECK-INST: sunpkd830 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0xa5,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 a5 ac <unknown>
+sunpkd830 a0, a1
+
+# CHECK-INST: sunpkd831 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0xb5,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 b5 ac <unknown>
+sunpkd831 a0, a1
+
+# CHECK-INST: sunpkd832 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x35,0xad]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 35 ad <unknown>
+sunpkd832 a0, a1
+
+# CHECK-INST: zunpkd810 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0xc5,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 c5 ac <unknown>
+zunpkd810 a0, a1
+
+# CHECK-INST: zunpkd820 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0xd5,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 d5 ac <unknown>
+zunpkd820 a0, a1
+
+# CHECK-INST: zunpkd830 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0xe5,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 e5 ac <unknown>
+zunpkd830 a0, a1
+
+# CHECK-INST: zunpkd831 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0xf5,0xac]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 f5 ac <unknown>
+zunpkd831 a0, a1
+
+# CHECK-INST: zunpkd832 a0, a1
+# CHECK-ENCODING: [0x77,0x85,0x75,0xad]
+# CHECK-ERROR: instruction requires the following: 'Zpn' (Normal 'P' Instructions)
+# CHECK-UNKNOWN: 77 85 75 ad <unknown>
+zunpkd832 a0, a1