[RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec.

[craig.topper]

Summary

The 0.93 spec has this implementation for add.uw

uint_xlen_t adduw(uint_xlen_t rs1, uint_xlen_t rs2) {

uint_xlen_t rs1u = (uint32_t)rs1;
return rs1u + rs2;

}

The 0.92 spec had the usages of rs1 and rs2 swapped.

[craig.topper]

Rebase

[frasercrmck]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

def : Pat<(or (or (and (shl GPR:$rs1, (i64 1)), (i64 0x4444444444444444)),
           (SHFLI GPR:$rs1, (i64 1))>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZba, IsRV64] in {
 def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
-def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
+def : Pat<(add (and GPR:$rs1, (i64 0xFFFFFFFF)), GPR:$rs2),
           (ADDUW GPR:$rs1, GPR:$rs2)>;
 }
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)),
           (SLOW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(not (riscv_srlw (not GPR:$rs1), GPR:$rs2)),
           (SROW GPR:$rs1, GPR:$rs2)>;

llvm/test/CodeGen/RISCV/rv64Zba.ll

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: adduw:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    add.uw a0, a0, a1
+; RV64IB-NEXT:    add.uw a0, a1, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: adduw:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    add.uw a0, a0, a1
+; RV64IBA-NEXT:    add.uw a0, a1, a0
 ; RV64IBA-NEXT:    ret
   %and = and i64 %b, 4294967295
   %add = add i64 %and, %a
   ret i64 %add
 }
 
 define signext i8 @adduw_2(i32 signext %0, i8* %1) {
 ; RV64I-LABEL: adduw_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    lb a0, 0(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: adduw_2:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    add.uw a0, a1, a0
+; RV64IB-NEXT:    add.uw a0, a0, a1
 ; RV64IB-NEXT:    lb a0, 0(a0)
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: adduw_2:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    add.uw a0, a1, a0
+; RV64IBA-NEXT:    add.uw a0, a0, a1
 ; RV64IBA-NEXT:    lb a0, 0(a0)
 ; RV64IBA-NEXT:    ret
   %3 = zext i32 %0 to i64
   %4 = getelementptr inbounds i8, i8* %1, i64 %3
   %5 = load i8, i8* %4
   ret i8 %5
 }