[RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.

[craig.topper]

Summary

Also renamed Zbe instructions to resolve name conflict even though
that change is in the 0.94 draft.

[frasercrmck]

What are the implications of having the renamed Zbe instructions in what we'll advertise as 0.93?

[craig.topper]

In D94653#2509254, @frasercrmck wrote:

What are the implications of having the renamed Zbe instructions in what we'll advertise as 0.93?

I'm not sure. It doesn't look like binutils implements Zbe instructions yet so there's no other precedent for handling this conflict.

[craig.topper]

Rebase

[craig.topper]

Rebase

[frasercrmck]

LGTM

[asb]

LGTM, going with the 0.94 deconflicted naming seems the only reasonable thing to do https://github.com/riscv/riscv-bitmanip/pull/102/commits/b962f8a04be570a93c3c4788425ee2e8a14e9c56

[asb]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

357–358

It might be worth adding a comment here and for the W variants just to document that these have been renamed to match the v0.94 due to the name conflict in 0.93.

[craig.topper]

Add comment for Zbe instructions having their 0.94 names.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 // Check that it is a SLLIUW (Shift Logical Left Immediate Unsigned i32
 // on RV64).
 def SLLIUWPat : PatFrag<(ops node:$A, node:$B),
                         (and (shl node:$A, node:$B), imm), [{
   return MatchSLLIUW(N);
 }]>;
 
 // Checks if this mask has a single 0 bit and cannot be used with ANDI.
-def SBCLRMask : ImmLeaf<XLenVT, [{
+def BCLRMask : ImmLeaf<XLenVT, [{
   if (Subtarget->is64Bit())
     return !isInt<12>(Imm) && isPowerOf2_64(~Imm);
   return !isInt<12>(Imm) && isPowerOf2_32(~Imm);
 }]>;
 
 // Checks if this mask has a single 1 bit and cannot be used with ORI/XORI.
-def SBSETINVMask : ImmLeaf<XLenVT, [{
+def BSETINVMask : ImmLeaf<XLenVT, [{
   if (Subtarget->is64Bit())
     return !isInt<12>(Imm) && isPowerOf2_64(Imm);
   return !isInt<12>(Imm) && isPowerOf2_32(Imm);
 }]>;
 
-def SBCLRXForm : SDNodeXForm<imm, [{
+def BCLRXForm : SDNodeXForm<imm, [{
   // Find the lowest 0.
   return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingOnes(),
                                    SDLoc(N), N->getValueType(0));
 }]>;
 
-def SBSETINVXForm : SDNodeXForm<imm, [{
+def BSETINVXForm : SDNodeXForm<imm, [{
   // Find the lowest 1.
   return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingZeros(),
                                    SDLoc(N), N->getValueType(0));
 }]>;
 
 // Similar to above, but makes sure the immediate has 33 sign bits. When used
 // with an AND/OR/XOR where the other operand has at least 33 sign bits, the
-// result will have 33 sign bits. This can match SBCLRIW/SBSETIW/SBINVIW.
-def SBCLRWMask : ImmLeaf<i64, [{
+// result will have 33 sign bits. This can match BCLRIW/BSETIW/BINVIW.
+def BCLRWMask : ImmLeaf<i64, [{
   // After checking the sign bits, truncate to 32 bits for power of 2 check.
   return isInt<32>(Imm) && !isInt<12>(Imm) && isPowerOf2_32(~Imm);
 }]>;
 
-def SBSETINVWMask : ImmLeaf<i64, [{
+def BSETINVWMask : ImmLeaf<i64, [{
   return isInt<32>(Imm) && !isInt<12>(Imm) && isPowerOf2_32(Imm);
 }]>;
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 // Some of these templates should be moved to RISCVInstrFormats.td once the B

 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbbOrZbp] in {
 def ROL   : ALU_rr<0b0110000, 0b001, "rol">, Sched<[]>;
 def ROR   : ALU_rr<0b0110000, 0b101, "ror">, Sched<[]>;
 } // Predicates = [HasStdExtZbbOrZbp]
 
 let Predicates = [HasStdExtZbs] in {
-def SBCLR : ALU_rr<0b0100100, 0b001, "sbclr">, Sched<[]>;
-def SBSET : ALU_rr<0b0010100, 0b001, "sbset">, Sched<[]>;
-def SBINV : ALU_rr<0b0110100, 0b001, "sbinv">, Sched<[]>;
-def SBEXT : ALU_rr<0b0100100, 0b101, "sbext">, Sched<[]>;
+def BCLR : ALU_rr<0b0100100, 0b001, "bclr">, Sched<[]>;
+def BSET : ALU_rr<0b0010100, 0b001, "bset">, Sched<[]>;
+def BINV : ALU_rr<0b0110100, 0b001, "binv">, Sched<[]>;
+def BEXT : ALU_rr<0b0100100, 0b101, "bext">, Sched<[]>;
 } // Predicates = [HasStdExtZbs]
 
 let Predicates = [HasStdExtZbp] in {
 def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
 def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbp] in {
 def SLOI : RVBShift_ri<0b00100, 0b001, OPC_OP_IMM, "sloi">, Sched<[]>;
 def SROI : RVBShift_ri<0b00100, 0b101, OPC_OP_IMM, "sroi">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbbOrZbp] in
 def RORI  : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">, Sched<[]>;
 
 let Predicates = [HasStdExtZbs] in {
-def SBCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "sbclri">, Sched<[]>;
-def SBSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "sbseti">, Sched<[]>;
-def SBINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "sbinvi">, Sched<[]>;
-def SBEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "sbexti">, Sched<[]>;
+def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">, Sched<[]>;
+def BSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "bseti">, Sched<[]>;
+def BINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "binvi">, Sched<[]>;
+def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">, Sched<[]>;
 } // Predicates = [HasStdExtZbs]
 
 let Predicates = [HasStdExtZbp] in {
 def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>;
 def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbt] in {

 def MAXU : ALU_rr<0b0000101, 0b111, "maxu">, Sched<[]>;
 } // Predicates = [HasStdExtZbb]
 
 let Predicates = [HasStdExtZbp] in {
 def SHFL   : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
 def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbe] in {
-def BDEP : ALU_rr<0b0100100, 0b110, "bdep">, Sched<[]>;
-def BEXT : ALU_rr<0b0000100, 0b110, "bext">, Sched<[]>;
+def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
+def BCOMPRESS   : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
 } // Predicates = [HasStdExtZbe]
 
 let Predicates = [HasStdExtZbbOrZbp] in {
 def PACK  : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
 def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
 } // Predicates = [HasStdExtZbbOrZbp]
 
 let Predicates = [HasStdExtZbm, IsRV64] in {

 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
 def ROLW  : ALUW_rr<0b0110000, 0b001, "rolw">, Sched<[]>;
 def RORW  : ALUW_rr<0b0110000, 0b101, "rorw">, Sched<[]>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
 
 let Predicates = [HasStdExtZbs, IsRV64] in {
-def SBCLRW : ALUW_rr<0b0100100, 0b001, "sbclrw">, Sched<[]>;
-def SBSETW : ALUW_rr<0b0010100, 0b001, "sbsetw">, Sched<[]>;
-def SBINVW : ALUW_rr<0b0110100, 0b001, "sbinvw">, Sched<[]>;
-def SBEXTW : ALUW_rr<0b0100100, 0b101, "sbextw">, Sched<[]>;
+def BCLRW : ALUW_rr<0b0100100, 0b001, "bclrw">, Sched<[]>;
+def BSETW : ALUW_rr<0b0010100, 0b001, "bsetw">, Sched<[]>;
+def BINVW : ALUW_rr<0b0110100, 0b001, "binvw">, Sched<[]>;
+def BEXTW : ALUW_rr<0b0100100, 0b101, "bextw">, Sched<[]>;
 } // Predicates = [HasStdExtZbs, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def GORCW  : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
 def GREVW  : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def SLOIW  : RVBShiftW_ri<0b0010000, 0b001, OPC_OP_IMM_32, "sloiw">, Sched<[]>;
 def SROIW  : RVBShiftW_ri<0b0010000, 0b101, OPC_OP_IMM_32, "sroiw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
 def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">, Sched<[]>;
 
 let Predicates = [HasStdExtZbs, IsRV64] in {
-def SBCLRIW : RVBShiftW_ri<0b0100100, 0b001, OPC_OP_IMM_32, "sbclriw">,
+def BCLRIW : RVBShiftW_ri<0b0100100, 0b001, OPC_OP_IMM_32, "bclriw">,
               Sched<[]>;
-def SBSETIW : RVBShiftW_ri<0b0010100, 0b001, OPC_OP_IMM_32, "sbsetiw">,
+def BSETIW : RVBShiftW_ri<0b0010100, 0b001, OPC_OP_IMM_32, "bsetiw">,
               Sched<[]>;
-def SBINVIW : RVBShiftW_ri<0b0110100, 0b001, OPC_OP_IMM_32, "sbinviw">,
+def BINVIW : RVBShiftW_ri<0b0110100, 0b001, OPC_OP_IMM_32, "binviw">,
               Sched<[]>;
 } // Predicates = [HasStdExtZbs, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>;
 def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 

 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def SHFLW   : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
 def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbe, IsRV64] in {
-def BDEPW : ALUW_rr<0b0100100, 0b110, "bdepw">, Sched<[]>;
-def BEXTW : ALUW_rr<0b0000100, 0b110, "bextw">, Sched<[]>;
+def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
+def BCOMPRESSW   : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
 } // Predicates = [HasStdExtZbe, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
 def PACKW  : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
 def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
 
 let Predicates = [HasStdExtZbf, IsRV64] in

 
 let Predicates = [HasStdExtZbbOrZbp] in {
 def : Pat<(rotl GPR:$rs1, GPR:$rs2), (ROL GPR:$rs1, GPR:$rs2)>;
 def : Pat<(rotr GPR:$rs1, GPR:$rs2), (ROR GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbp]
 
 let Predicates = [HasStdExtZbs] in {
 def : Pat<(and (not (shiftop<shl> 1, GPR:$rs2)), GPR:$rs1),
-          (SBCLR GPR:$rs1, GPR:$rs2)>;
-def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (SBCLR GPR:$rs1, GPR:$rs2)>;
+          (BCLR GPR:$rs1, GPR:$rs2)>;
+def : Pat<(and (rotl -2, GPR:$rs2), GPR:$rs1), (BCLR GPR:$rs1, GPR:$rs2)>;
 def : Pat<(or (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
-          (SBSET GPR:$rs1, GPR:$rs2)>;
+          (BSET GPR:$rs1, GPR:$rs2)>;
 def : Pat<(xor (shiftop<shl> 1, GPR:$rs2), GPR:$rs1),
-          (SBINV GPR:$rs1, GPR:$rs2)>;
+          (BINV GPR:$rs1, GPR:$rs2)>;
 def : Pat<(and (shiftop<srl> GPR:$rs1, GPR:$rs2), 1),
-          (SBEXT GPR:$rs1, GPR:$rs2)>;
+          (BEXT GPR:$rs1, GPR:$rs2)>;
 
 def : Pat<(shiftop<shl> 1, GPR:$rs2),
-          (SBSET X0, GPR:$rs2)>;
+          (BSET X0, GPR:$rs2)>;
 
-def : Pat<(and GPR:$rs1, SBCLRMask:$mask),
-          (SBCLRI GPR:$rs1, (SBCLRXForm imm:$mask))>;
-def : Pat<(or GPR:$rs1, SBSETINVMask:$mask),
-          (SBSETI GPR:$rs1, (SBSETINVXForm imm:$mask))>;
-def : Pat<(xor GPR:$rs1, SBSETINVMask:$mask),
-          (SBINVI GPR:$rs1, (SBSETINVXForm imm:$mask))>;
+def : Pat<(and GPR:$rs1, BCLRMask:$mask),
+          (BCLRI GPR:$rs1, (BCLRXForm imm:$mask))>;
+def : Pat<(or GPR:$rs1, BSETINVMask:$mask),
+          (BSETI GPR:$rs1, (BSETINVXForm imm:$mask))>;
+def : Pat<(xor GPR:$rs1, BSETINVMask:$mask),
+          (BINVI GPR:$rs1, (BSETINVXForm imm:$mask))>;
 }
 
 let Predicates = [HasStdExtZbp] in {
 def : Pat<(SLOIPat GPR:$rs1, uimmlog2xlen:$shamt),
           (SLOI GPR:$rs1, uimmlog2xlen:$shamt)>;
 def : Pat<(SROIPat GPR:$rs1, uimmlog2xlen:$shamt),
           (SROI GPR:$rs1, uimmlog2xlen:$shamt)>;
 } // Predicates = [HasStdExtZbp]
 
 // There's no encoding for roli in the current version of the 'B' extension
 // (v0.92) as it can be implemented with rori by negating the immediate.
 let Predicates = [HasStdExtZbbOrZbp] in {
 def : Pat<(rotr GPR:$rs1, uimmlog2xlen:$shamt),
           (RORI GPR:$rs1, uimmlog2xlen:$shamt)>;
 def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
           (RORI GPR:$rs1, (ImmROTL2R uimmlog2xlen:$shamt))>;
 }
 
 // We don't pattern-match sbclri[w], sbseti[w], sbinvi[w] because they are
 // pattern-matched by simple andi, ori, and xori.
 let Predicates = [HasStdExtZbs] in
 def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
-          (SBEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
+          (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
 
 def riscv_grevi    : SDNode<"RISCVISD::GREVI", SDTIntBinOp, []>;
 def riscv_greviw   : SDNode<"RISCVISD::GREVIW", SDTIntBinOp, []>;
 def riscv_gorci    : SDNode<"RISCVISD::GORCI", SDTIntBinOp, []>;
 def riscv_gorciw   : SDNode<"RISCVISD::GORCIW", SDTIntBinOp, []>;
 
 let Predicates = [HasStdExtZbp] in {
 def : Pat<(riscv_grevi GPR:$rs1, timm:$shamt), (GREVI GPR:$rs1, timm:$shamt)>;

 def : Pat<(riscv_rorw GPR:$rs1, uimm5:$rs2),
           (RORIW GPR:$rs1, uimm5:$rs2)>;
 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
           (RORIW GPR:$rs1, (ImmROTL2RW uimm5:$rs2))>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
 
 let Predicates = [HasStdExtZbs, IsRV64] in {
 def : Pat<(and (not (riscv_sllw 1, GPR:$rs2)), (assertsexti32 GPR:$rs1)),
-          (SBCLRW GPR:$rs1, GPR:$rs2)>;
+          (BCLRW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(sext_inreg (and (not (riscv_sllw 1, GPR:$rs2)), GPR:$rs1), i32),
-          (SBCLRW GPR:$rs1, GPR:$rs2)>;
+          (BCLRW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(or (riscv_sllw 1, GPR:$rs2), (assertsexti32 GPR:$rs1)),
-          (SBSETW GPR:$rs1, GPR:$rs2)>;
+          (BSETW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(sext_inreg (or (riscv_sllw 1, GPR:$rs2), GPR:$rs1), i32),
-          (SBSETW GPR:$rs1, GPR:$rs2)>;
+          (BSETW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(xor (riscv_sllw 1, GPR:$rs2), (assertsexti32 GPR:$rs1)),
-          (SBINVW GPR:$rs1, GPR:$rs2)>;
+          (BINVW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(sext_inreg (xor (riscv_sllw 1, GPR:$rs2), GPR:$rs1), i32),
-          (SBINVW GPR:$rs1, GPR:$rs2)>;
+          (BINVW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(and (riscv_srlw GPR:$rs1, GPR:$rs2), 1),
-          (SBEXTW GPR:$rs1, GPR:$rs2)>;
+          (BEXTW GPR:$rs1, GPR:$rs2)>;
 
 def : Pat<(riscv_sllw 1, GPR:$rs2),
-          (SBSETW X0, GPR:$rs2)>;
+          (BSETW X0, GPR:$rs2)>;
 
-def : Pat<(and (assertsexti32 GPR:$rs1), SBCLRWMask:$mask),
-          (SBCLRIW GPR:$rs1, (SBCLRXForm imm:$mask))>;
-def : Pat<(or (assertsexti32 GPR:$rs1), SBSETINVWMask:$mask),
-          (SBSETIW GPR:$rs1, (SBSETINVXForm imm:$mask))>;
-def : Pat<(xor (assertsexti32 GPR:$rs1), SBSETINVWMask:$mask),
-          (SBINVIW GPR:$rs1, (SBSETINVXForm imm:$mask))>;
+def : Pat<(and (assertsexti32 GPR:$rs1), BCLRWMask:$mask),
+          (BCLRIW GPR:$rs1, (BCLRXForm imm:$mask))>;
+def : Pat<(or (assertsexti32 GPR:$rs1), BSETINVWMask:$mask),
+          (BSETIW GPR:$rs1, (BSETINVXForm imm:$mask))>;
+def : Pat<(xor (assertsexti32 GPR:$rs1), BSETINVWMask:$mask),
+          (BINVIW GPR:$rs1, (BSETINVXForm imm:$mask))>;
 
 } // Predicates = [HasStdExtZbs, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def : Pat<(sext_inreg (SLOIPat GPR:$rs1, uimm5:$shamt), i32),
           (SLOIW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(SROIWPat GPR:$rs1, uimm5:$shamt),
           (SROIW GPR:$rs1, uimm5:$shamt)>;

llvm/test/CodeGen/RISCV/rv32Zbs.ll

 ; RV32I-NEXT:    addi a2, zero, 1
 ; RV32I-NEXT:    sll a1, a2, a1
 ; RV32I-NEXT:    not a1, a1
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbclr_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbclr a0, a0, a1
+; RV32IB-NEXT:    bclr a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclr_i32:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbclr a0, a0, a1
+; RV32IBS-NEXT:    bclr a0, a0, a1
 ; RV32IBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %neg = xor i32 %shl, -1
   %and1 = and i32 %neg, %a
   ret i32 %and1
 }
 
 define i32 @sbclr_i32_no_mask(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: sbclr_i32_no_mask:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 1
 ; RV32I-NEXT:    sll a1, a2, a1
 ; RV32I-NEXT:    not a1, a1
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbclr_i32_no_mask:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbclr a0, a0, a1
+; RV32IB-NEXT:    bclr a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclr_i32_no_mask:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbclr a0, a0, a1
+; RV32IBS-NEXT:    bclr a0, a0, a1
 ; RV32IBS-NEXT:    ret
   %shl = shl nuw i32 1, %b
   %neg = xor i32 %shl, -1
   %and1 = and i32 %neg, %a
   ret i32 %and1
 }
 
 define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {

 ; RV32I-NEXT:    and a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbclr_i64:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    andi a3, a2, 63
 ; RV32IB-NEXT:    addi a3, a3, -32
 ; RV32IB-NEXT:    slti a4, a3, 0
-; RV32IB-NEXT:    sbset a5, zero, a3
+; RV32IB-NEXT:    bset a5, zero, a3
 ; RV32IB-NEXT:    cmov a4, a4, a5, zero
-; RV32IB-NEXT:    sbset a2, zero, a2
+; RV32IB-NEXT:    bset a2, zero, a2
 ; RV32IB-NEXT:    srai a3, a3, 31
 ; RV32IB-NEXT:    and a2, a3, a2
 ; RV32IB-NEXT:    andn a1, a1, a4
 ; RV32IB-NEXT:    andn a0, a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclr_i64:
 ; RV32IBS:       # %bb.0:
 ; RV32IBS-NEXT:    andi a3, a2, 63
 ; RV32IBS-NEXT:    addi a3, a3, -32
 ; RV32IBS-NEXT:    bltz a3, .LBB2_2
 ; RV32IBS-NEXT:  # %bb.1:
 ; RV32IBS-NEXT:    mv a2, zero
-; RV32IBS-NEXT:    sbset a3, zero, a3
+; RV32IBS-NEXT:    bset a3, zero, a3
 ; RV32IBS-NEXT:    j .LBB2_3
 ; RV32IBS-NEXT:  .LBB2_2:
 ; RV32IBS-NEXT:    mv a3, zero
-; RV32IBS-NEXT:    sbset a2, zero, a2
+; RV32IBS-NEXT:    bset a2, zero, a2
 ; RV32IBS-NEXT:  .LBB2_3:
 ; RV32IBS-NEXT:    not a3, a3
 ; RV32IBS-NEXT:    not a2, a2
 ; RV32IBS-NEXT:    and a0, a2, a0
 ; RV32IBS-NEXT:    and a1, a3, a1
 ; RV32IBS-NEXT:    ret
   %and = and i64 %b, 63
   %shl = shl nuw i64 1, %and
   %neg = xor i64 %shl, -1
   %and1 = and i64 %neg, %a
   ret i64 %and1
 }
 
 define i32 @sbset_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: sbset_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 1
 ; RV32I-NEXT:    sll a1, a2, a1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbset_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbset a0, a0, a1
+; RV32IB-NEXT:    bset a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbset_i32:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbset a0, a0, a1
+; RV32IBS-NEXT:    bset a0, a0, a1
 ; RV32IBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %or = or i32 %shl, %a
   ret i32 %or
 }
 
 define i32 @sbset_i32_no_mask(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: sbset_i32_no_mask:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 1
 ; RV32I-NEXT:    sll a1, a2, a1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbset_i32_no_mask:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbset a0, a0, a1
+; RV32IB-NEXT:    bset a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbset_i32_no_mask:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbset a0, a0, a1
+; RV32IBS-NEXT:    bset a0, a0, a1
 ; RV32IBS-NEXT:    ret
   %shl = shl nuw i32 1, %b
   %or = or i32 %shl, %a
   ret i32 %or
 }
 
 ; We can use sbsetw for 1 << x by setting the first source to zero.
 define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
 ; RV32I-LABEL: sbset_i32_zero:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 1
 ; RV32I-NEXT:    sll a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbset_i32_zero:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbset a0, zero, a0
+; RV32IB-NEXT:    bset a0, zero, a0
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbset_i32_zero:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbset a0, zero, a0
+; RV32IBS-NEXT:    bset a0, zero, a0
 ; RV32IBS-NEXT:    ret
   %shl = shl i32 1, %a
   ret i32 %shl
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
 ; This test is presented here in case future expansions of the experimental-b
 ; extension introduce instructions suitable for this pattern.
 
 define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: sbset_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a3, zero, 1
 ; RV32I-NEXT:    sll a2, a3, a2
 ; RV32I-NEXT:    srai a3, a2, 31
 ; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:    or a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbset_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbset a3, zero, a2
+; RV32IB-NEXT:    bset a3, zero, a2
 ; RV32IB-NEXT:    srai a3, a3, 31
-; RV32IB-NEXT:    sbset a0, a0, a2
+; RV32IB-NEXT:    bset a0, a0, a2
 ; RV32IB-NEXT:    or a1, a3, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbset_i64:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbset a3, zero, a2
+; RV32IBS-NEXT:    bset a3, zero, a2
 ; RV32IBS-NEXT:    srai a3, a3, 31
-; RV32IBS-NEXT:    sbset a0, a0, a2
+; RV32IBS-NEXT:    bset a0, a0, a2
 ; RV32IBS-NEXT:    or a1, a3, a1
 ; RV32IBS-NEXT:    ret
   %1 = trunc i64 %b to i32
   %conv = and i32 %1, 63
   %shl = shl nuw i32 1, %conv
   %conv1 = sext i32 %shl to i64
   %or = or i64 %conv1, %a
   ret i64 %or

 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    sll a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbset_i64_zero:
 ; RV32IB:       # %bb.0:
 ; RV32IB-NEXT:    addi a2, a0, -32
 ; RV32IB-NEXT:    slti a1, a2, 0
-; RV32IB-NEXT:    sbset a3, zero, a2
+; RV32IB-NEXT:    bset a3, zero, a2
 ; RV32IB-NEXT:    cmov a1, a1, a3, zero
-; RV32IB-NEXT:    sbset a0, zero, a0
+; RV32IB-NEXT:    bset a0, zero, a0
 ; RV32IB-NEXT:    srai a2, a2, 31
 ; RV32IB-NEXT:    and a0, a2, a0
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbset_i64_zero:
 ; RV32IBS:       # %bb.0:
 ; RV32IBS-NEXT:    addi a1, a0, -32
 ; RV32IBS-NEXT:    bltz a1, .LBB7_2
 ; RV32IBS-NEXT:  # %bb.1:
 ; RV32IBS-NEXT:    mv a0, zero
-; RV32IBS-NEXT:    sbset a1, zero, a1
+; RV32IBS-NEXT:    bset a1, zero, a1
 ; RV32IBS-NEXT:    ret
 ; RV32IBS-NEXT:  .LBB7_2:
 ; RV32IBS-NEXT:    mv a1, zero
-; RV32IBS-NEXT:    sbset a0, zero, a0
+; RV32IBS-NEXT:    bset a0, zero, a0
 ; RV32IBS-NEXT:    ret
   %shl = shl i64 1, %a
   ret i64 %shl
 }
 
 define i32 @sbinv_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: sbinv_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 1
 ; RV32I-NEXT:    sll a1, a2, a1
 ; RV32I-NEXT:    xor a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbinv_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbinv a0, a0, a1
+; RV32IB-NEXT:    binv a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbinv_i32:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbinv a0, a0, a1
+; RV32IBS-NEXT:    binv a0, a0, a1
 ; RV32IBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %xor = xor i32 %shl, %a
   ret i32 %xor
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.
 ; This test is presented here in case future expansions of the experimental-b
 ; extension introduce instructions suitable for this pattern.
 
 define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: sbinv_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a3, zero, 1
 ; RV32I-NEXT:    sll a2, a3, a2
 ; RV32I-NEXT:    srai a3, a2, 31
 ; RV32I-NEXT:    xor a0, a2, a0
 ; RV32I-NEXT:    xor a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbinv_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbset a3, zero, a2
+; RV32IB-NEXT:    bset a3, zero, a2
 ; RV32IB-NEXT:    srai a3, a3, 31
-; RV32IB-NEXT:    sbinv a0, a0, a2
+; RV32IB-NEXT:    binv a0, a0, a2
 ; RV32IB-NEXT:    xor a1, a3, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbinv_i64:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbset a3, zero, a2
+; RV32IBS-NEXT:    bset a3, zero, a2
 ; RV32IBS-NEXT:    srai a3, a3, 31
-; RV32IBS-NEXT:    sbinv a0, a0, a2
+; RV32IBS-NEXT:    binv a0, a0, a2
 ; RV32IBS-NEXT:    xor a1, a3, a1
 ; RV32IBS-NEXT:    ret
   %1 = trunc i64 %b to i32
   %conv = and i32 %1, 63
   %shl = shl nuw i32 1, %conv
   %conv1 = sext i32 %shl to i64
   %xor = xor i64 %conv1, %a
   ret i64 %xor
 }
 
 define i32 @sbext_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: sbext_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srl a0, a0, a1
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbext_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbext a0, a0, a1
+; RV32IB-NEXT:    bext a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbext_i32:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbext a0, a0, a1
+; RV32IBS-NEXT:    bext a0, a0, a1
 ; RV32IBS-NEXT:    ret
   %and = and i32 %b, 31
   %shr = lshr i32 %a, %and
   %and1 = and i32 %shr, 1
   ret i32 %and1
 }
 
 define i32 @sbext_i32_no_mask(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: sbext_i32_no_mask:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srl a0, a0, a1
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbext_i32_no_mask:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbext a0, a0, a1
+; RV32IB-NEXT:    bext a0, a0, a1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbext_i32_no_mask:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbext a0, a0, a1
+; RV32IBS-NEXT:    bext a0, a0, a1
 ; RV32IBS-NEXT:    ret
   %shr = lshr i32 %a, %b
   %and1 = and i32 %shr, 1
   ret i32 %and1
 }
 
 ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
 ; don't have yet any matching bit manipulation instructions on RV32.

 ; RV32I-LABEL: sbexti_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a0, a0, 5
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbexti_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbexti a0, a0, 5
+; RV32IB-NEXT:    bexti a0, a0, 5
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbexti_i32:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbexti a0, a0, 5
+; RV32IBS-NEXT:    bexti a0, a0, 5
 ; RV32IBS-NEXT:    ret
   %shr = lshr i32 %a, 5
   %and = and i32 %shr, 1
   ret i32 %and
 }
 
 define i64 @sbexti_i64(i64 %a) nounwind {
 ; RV32I-LABEL: sbexti_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a0, a0, 5
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbexti_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbexti a0, a0, 5
+; RV32IB-NEXT:    bexti a0, a0, 5
 ; RV32IB-NEXT:    mv a1, zero
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbexti_i64:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbexti a0, a0, 5
+; RV32IBS-NEXT:    bexti a0, a0, 5
 ; RV32IBS-NEXT:    mv a1, zero
 ; RV32IBS-NEXT:    ret
   %shr = lshr i64 %a, 5
   %and = and i64 %shr, 1
   ret i64 %and
 }
 
 define i32 @sbclri_i32_10(i32 %a) nounwind {

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1048575
 ; RV32I-NEXT:    addi a1, a1, 2047
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbclri_i32_11:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbclri a0, a0, 11
+; RV32IB-NEXT:    bclri a0, a0, 11
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclri_i32_11:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbclri a0, a0, 11
+; RV32IBS-NEXT:    bclri a0, a0, 11
 ; RV32IBS-NEXT:    ret
   %and = and i32 %a, -2049
   ret i32 %and
 }
 
 define i32 @sbclri_i32_30(i32 %a) nounwind {
 ; RV32I-LABEL: sbclri_i32_30:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 786432
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbclri_i32_30:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbclri a0, a0, 30
+; RV32IB-NEXT:    bclri a0, a0, 30
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclri_i32_30:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbclri a0, a0, 30
+; RV32IBS-NEXT:    bclri a0, a0, 30
 ; RV32IBS-NEXT:    ret
   %and = and i32 %a, -1073741825
   ret i32 %and
 }
 
 define i32 @sbclri_i32_31(i32 %a) nounwind {
 ; RV32I-LABEL: sbclri_i32_31:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbclri_i32_31:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbclri a0, a0, 31
+; RV32IB-NEXT:    bclri a0, a0, 31
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbclri_i32_31:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbclri a0, a0, 31
+; RV32IBS-NEXT:    bclri a0, a0, 31
 ; RV32IBS-NEXT:    ret
   %and = and i32 %a, -2147483649
   ret i32 %and
 }
 
 define i32 @sbseti_i32_10(i32 %a) nounwind {
 ; RV32I-LABEL: sbseti_i32_10:
 ; RV32I:       # %bb.0:

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, -2048
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbseti_i32_11:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbseti a0, a0, 11
+; RV32IB-NEXT:    bseti a0, a0, 11
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbseti_i32_11:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbseti a0, a0, 11
+; RV32IBS-NEXT:    bseti a0, a0, 11
 ; RV32IBS-NEXT:    ret
   %or = or i32 %a, 2048
   ret i32 %or
 }
 
 define i32 @sbseti_i32_30(i32 %a) nounwind {
 ; RV32I-LABEL: sbseti_i32_30:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 262144
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbseti_i32_30:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbseti a0, a0, 30
+; RV32IB-NEXT:    bseti a0, a0, 30
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbseti_i32_30:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbseti a0, a0, 30
+; RV32IBS-NEXT:    bseti a0, a0, 30
 ; RV32IBS-NEXT:    ret
   %or = or i32 %a, 1073741824
   ret i32 %or
 }
 
 define i32 @sbseti_i32_31(i32 %a) nounwind {
 ; RV32I-LABEL: sbseti_i32_31:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbseti_i32_31:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbseti a0, a0, 31
+; RV32IB-NEXT:    bseti a0, a0, 31
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbseti_i32_31:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbseti a0, a0, 31
+; RV32IBS-NEXT:    bseti a0, a0, 31
 ; RV32IBS-NEXT:    ret
   %or = or i32 %a, 2147483648
   ret i32 %or
 }
 
 define i32 @sbinvi_i32_10(i32 %a) nounwind {
 ; RV32I-LABEL: sbinvi_i32_10:
 ; RV32I:       # %bb.0:

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, -2048
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbinvi_i32_11:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbinvi a0, a0, 11
+; RV32IB-NEXT:    binvi a0, a0, 11
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbinvi_i32_11:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbinvi a0, a0, 11
+; RV32IBS-NEXT:    binvi a0, a0, 11
 ; RV32IBS-NEXT:    ret
   %xor = xor i32 %a, 2048
   ret i32 %xor
 }
 
 define i32 @sbinvi_i32_30(i32 %a) nounwind {
 ; RV32I-LABEL: sbinvi_i32_30:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 262144
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbinvi_i32_30:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbinvi a0, a0, 30
+; RV32IB-NEXT:    binvi a0, a0, 30
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbinvi_i32_30:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbinvi a0, a0, 30
+; RV32IBS-NEXT:    binvi a0, a0, 30
 ; RV32IBS-NEXT:    ret
   %xor = xor i32 %a, 1073741824
   ret i32 %xor
 }
 
 define i32 @sbinvi_i32_31(i32 %a) nounwind {
 ; RV32I-LABEL: sbinvi_i32_31:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 524288
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sbinvi_i32_31:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    sbinvi a0, a0, 31
+; RV32IB-NEXT:    binvi a0, a0, 31
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBS-LABEL: sbinvi_i32_31:
 ; RV32IBS:       # %bb.0:
-; RV32IBS-NEXT:    sbinvi a0, a0, 31
+; RV32IBS-NEXT:    binvi a0, a0, 31
 ; RV32IBS-NEXT:    ret
   %xor = xor i32 %a, 2147483648
   ret i32 %xor
 }

llvm/test/CodeGen/RISCV/rv32Zbt.ll

 ; RV32IB-NEXT:    andn t4, a5, a4
 ; RV32IB-NEXT:    addi a2, t4, -32
 ; RV32IB-NEXT:    srai a5, a2, 31
 ; RV32IB-NEXT:    and a5, a5, t1
 ; RV32IB-NEXT:    or a7, a5, a7
 ; RV32IB-NEXT:    fsri a1, a0, a1, 31
 ; RV32IB-NEXT:    sll a1, a1, t3
 ; RV32IB-NEXT:    sub a5, a6, t4
-; RV32IB-NEXT:    sbclri a0, a0, 31
+; RV32IB-NEXT:    bclri a0, a0, 31
 ; RV32IB-NEXT:    srl a0, a0, a5
 ; RV32IB-NEXT:    or a0, a1, a0
 ; RV32IB-NEXT:    sll a1, t0, a2
 ; RV32IB-NEXT:    slti a2, a2, 0
 ; RV32IB-NEXT:    cmov a0, a2, a1, a0
 ; RV32IB-NEXT:    srl a1, a3, a4
 ; RV32IB-NEXT:    srai a2, t2, 31
 ; RV32IB-NEXT:    and a1, a2, a1

llvm/test/CodeGen/RISCV/rv64Zbs.ll

 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclr_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbclrw a0, a0, a1
+; RV64IB-NEXT:    bclrw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclr_i32:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbclrw a0, a0, a1
+; RV64IBS-NEXT:    bclrw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %neg = xor i32 %shl, -1
   %and1 = and i32 %neg, %a
   ret i32 %and1
 }
 
 define signext i32 @sbclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbclr_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclr_i32_no_mask:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbclrw a0, a0, a1
+; RV64IB-NEXT:    bclrw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclr_i32_no_mask:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbclrw a0, a0, a1
+; RV64IBS-NEXT:    bclrw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %shl = shl i32 1, %b
   %neg = xor i32 %shl, -1
   %and1 = and i32 %neg, %a
   ret i32 %and1
 }
 
 define signext i32 @sbclr_i32_load(i32* %p, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbclr_i32_load:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclr_i32_load:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    lw a0, 0(a0)
-; RV64IB-NEXT:    sbclrw a0, a0, a1
+; RV64IB-NEXT:    bclrw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclr_i32_load:
 ; RV64IBS:       # %bb.0:
 ; RV64IBS-NEXT:    lw a0, 0(a0)
-; RV64IBS-NEXT:    sbclrw a0, a0, a1
+; RV64IBS-NEXT:    bclrw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %a = load i32, i32* %p
   %shl = shl i32 1, %b
   %neg = xor i32 %shl, -1
   %and1 = and i32 %neg, %a
   ret i32 %and1
 }
 
 define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sbclr_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclr_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbclr a0, a0, a1
+; RV64IB-NEXT:    bclr a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclr_i64:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbclr a0, a0, a1
+; RV64IBS-NEXT:    bclr a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %and = and i64 %b, 63
   %shl = shl nuw i64 1, %and
   %neg = xor i64 %shl, -1
   %and1 = and i64 %neg, %a
   ret i64 %and1
 }
 
 define i64 @sbclr_i64_no_mask(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sbclr_i64_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclr_i64_no_mask:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbclr a0, a0, a1
+; RV64IB-NEXT:    bclr a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclr_i64_no_mask:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbclr a0, a0, a1
+; RV64IBS-NEXT:    bclr a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %shl = shl i64 1, %b
   %neg = xor i64 %shl, -1
   %and1 = and i64 %neg, %a
   ret i64 %and1
 }
 
 define signext i32 @sbset_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbset_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbset_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbsetw a0, a0, a1
+; RV64IB-NEXT:    bsetw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbset_i32:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbsetw a0, a0, a1
+; RV64IBS-NEXT:    bsetw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %or = or i32 %shl, %a
   ret i32 %or
 }
 
 define signext i32 @sbset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbset_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbset_i32_no_mask:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbsetw a0, a0, a1
+; RV64IB-NEXT:    bsetw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbset_i32_no_mask:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbsetw a0, a0, a1
+; RV64IBS-NEXT:    bsetw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %shl = shl i32 1, %b
   %or = or i32 %shl, %a
   ret i32 %or
 }
 
 define signext i32 @sbset_i32_load(i32* %p, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbset_i32_load:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbset_i32_load:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    lw a0, 0(a0)
-; RV64IB-NEXT:    sbsetw a0, a0, a1
+; RV64IB-NEXT:    bsetw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbset_i32_load:
 ; RV64IBS:       # %bb.0:
 ; RV64IBS-NEXT:    lw a0, 0(a0)
-; RV64IBS-NEXT:    sbsetw a0, a0, a1
+; RV64IBS-NEXT:    bsetw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %a = load i32, i32* %p
   %shl = shl i32 1, %b
   %or = or i32 %shl, %a
   ret i32 %or
 }
 
 ; We can use sbsetw for 1 << x by setting the first source to zero.
 define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
 ; RV64I-LABEL: sbset_i32_zero:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    sllw a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbset_i32_zero:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbsetw a0, zero, a0
+; RV64IB-NEXT:    bsetw a0, zero, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbset_i32_zero:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbsetw a0, zero, a0
+; RV64IBS-NEXT:    bsetw a0, zero, a0
 ; RV64IBS-NEXT:    ret
   %shl = shl i32 1, %a
   ret i32 %shl
 }
 
 define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sbset_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbset_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbset a0, a0, a1
+; RV64IB-NEXT:    bset a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbset_i64:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbset a0, a0, a1
+; RV64IBS-NEXT:    bset a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %conv = and i64 %b, 63
   %shl = shl nuw i64 1, %conv
   %or = or i64 %shl, %a
   ret i64 %or
 }
 
 define i64 @sbset_i64_no_mask(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sbset_i64_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbset_i64_no_mask:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbset a0, a0, a1
+; RV64IB-NEXT:    bset a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbset_i64_no_mask:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbset a0, a0, a1
+; RV64IBS-NEXT:    bset a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %shl = shl i64 1, %b
   %or = or i64 %shl, %a
   ret i64 %or
 }
 
 ; We can use sbsetw for 1 << x by setting the first source to zero.
 define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
 ; RV64I-LABEL: sbset_i64_zero:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    sll a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbset_i64_zero:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbset a0, zero, a0
+; RV64IB-NEXT:    bset a0, zero, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbset_i64_zero:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbset a0, zero, a0
+; RV64IBS-NEXT:    bset a0, zero, a0
 ; RV64IBS-NEXT:    ret
   %shl = shl i64 1, %a
   ret i64 %shl
 }
 
 define signext i32 @sbinv_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbinv_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinv_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbinvw a0, a0, a1
+; RV64IB-NEXT:    binvw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinv_i32:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbinvw a0, a0, a1
+; RV64IBS-NEXT:    binvw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %and = and i32 %b, 31
   %shl = shl nuw i32 1, %and
   %xor = xor i32 %shl, %a
   ret i32 %xor
 }
 
 define signext i32 @sbinv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbinv_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinv_i32_no_mask:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbinvw a0, a0, a1
+; RV64IB-NEXT:    binvw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinv_i32_no_mask:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbinvw a0, a0, a1
+; RV64IBS-NEXT:    binvw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %shl = shl i32 1, %b
   %xor = xor i32 %shl, %a
   ret i32 %xor
 }
 
 define signext i32 @sbinv_i32_load(i32* %p, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbinv_i32_load:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sllw a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinv_i32_load:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    lw a0, 0(a0)
-; RV64IB-NEXT:    sbinvw a0, a0, a1
+; RV64IB-NEXT:    binvw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinv_i32_load:
 ; RV64IBS:       # %bb.0:
 ; RV64IBS-NEXT:    lw a0, 0(a0)
-; RV64IBS-NEXT:    sbinvw a0, a0, a1
+; RV64IBS-NEXT:    binvw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %a = load i32, i32* %p
   %shl = shl i32 1, %b
   %xor = xor i32 %shl, %a
   ret i32 %xor
 }
 
 define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sbinv_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinv_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbinv a0, a0, a1
+; RV64IB-NEXT:    binv a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinv_i64:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbinv a0, a0, a1
+; RV64IBS-NEXT:    binv a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %conv = and i64 %b, 63
   %shl = shl nuw i64 1, %conv
   %xor = xor i64 %shl, %a
   ret i64 %xor
 }
 
 define i64 @sbinv_i64_no_mask(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sbinv_i64_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    sll a1, a2, a1
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinv_i64_no_mask:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbinv a0, a0, a1
+; RV64IB-NEXT:    binv a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinv_i64_no_mask:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbinv a0, a0, a1
+; RV64IBS-NEXT:    binv a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %shl = shl nuw i64 1, %b
   %xor = xor i64 %shl, %a
   ret i64 %xor
 }
 
 define signext i32 @sbext_i32(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbext_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbext_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbextw a0, a0, a1
+; RV64IB-NEXT:    bextw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbext_i32:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbextw a0, a0, a1
+; RV64IBS-NEXT:    bextw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %and = and i32 %b, 31
   %shr = lshr i32 %a, %and
   %and1 = and i32 %shr, 1
   ret i32 %and1
 }
 
 define signext i32 @sbext_i32_no_mask(i32 signext %a, i32 signext %b) nounwind {
 ; RV64I-LABEL: sbext_i32_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbext_i32_no_mask:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbextw a0, a0, a1
+; RV64IB-NEXT:    bextw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbext_i32_no_mask:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbextw a0, a0, a1
+; RV64IBS-NEXT:    bextw a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %shr = lshr i32 %a, %b
   %and1 = and i32 %shr, 1
   ret i32 %and1
 }
 
 define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sbext_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbext_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbext a0, a0, a1
+; RV64IB-NEXT:    bext a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbext_i64:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbext a0, a0, a1
+; RV64IBS-NEXT:    bext a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %conv = and i64 %b, 63
   %shr = lshr i64 %a, %conv
   %and1 = and i64 %shr, 1
   ret i64 %and1
 }
 
 define i64 @sbext_i64_no_mask(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sbext_i64_no_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbext_i64_no_mask:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbext a0, a0, a1
+; RV64IB-NEXT:    bext a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbext_i64_no_mask:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbext a0, a0, a1
+; RV64IBS-NEXT:    bext a0, a0, a1
 ; RV64IBS-NEXT:    ret
   %shr = lshr i64 %a, %b
   %and1 = and i64 %shr, 1
   ret i64 %and1
 }
 
 define signext i32 @sbexti_i32(i32 signext %a) nounwind {
 ; RV64I-LABEL: sbexti_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a0, a0, 5
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbexti_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbexti a0, a0, 5
+; RV64IB-NEXT:    bexti a0, a0, 5
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbexti_i32:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbexti a0, a0, 5
+; RV64IBS-NEXT:    bexti a0, a0, 5
 ; RV64IBS-NEXT:    ret
   %shr = lshr i32 %a, 5
   %and = and i32 %shr, 1
   ret i32 %and
 }
 
 define i64 @sbexti_i64(i64 %a) nounwind {
 ; RV64I-LABEL: sbexti_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a0, a0, 5
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbexti_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbexti a0, a0, 5
+; RV64IB-NEXT:    bexti a0, a0, 5
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbexti_i64:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbexti a0, a0, 5
+; RV64IBS-NEXT:    bexti a0, a0, 5
 ; RV64IBS-NEXT:    ret
   %shr = lshr i64 %a, 5
   %and = and i64 %shr, 1
   ret i64 %and
 }
 
 define signext i32 @sbclri_i32_10(i32 signext %a) nounwind {
 ; RV64I-LABEL: sbclri_i32_10:

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1048575
 ; RV64I-NEXT:    addiw a1, a1, 2047
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclri_i64_11:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbclri a0, a0, 11
+; RV64IB-NEXT:    bclri a0, a0, 11
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclri_i64_11:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbclri a0, a0, 11
+; RV64IBS-NEXT:    bclri a0, a0, 11
 ; RV64IBS-NEXT:    ret
   %and = and i64 %a, -2049
   ret i64 %and
 }
 
 define i64 @sbclri_i64_30(i64 %a) nounwind {
 ; RV64I-LABEL: sbclri_i64_30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 786432
 ; RV64I-NEXT:    addiw a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclri_i64_30:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbclri a0, a0, 30
+; RV64IB-NEXT:    bclri a0, a0, 30
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclri_i64_30:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbclri a0, a0, 30
+; RV64IBS-NEXT:    bclri a0, a0, 30
 ; RV64IBS-NEXT:    ret
   %and = and i64 %a, -1073741825
   ret i64 %and
 }
 
 define i64 @sbclri_i64_31(i64 %a) nounwind {
 ; RV64I-LABEL: sbclri_i64_31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
 ; RV64I-NEXT:    slli a1, a1, 31
 ; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclri_i64_31:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbclri a0, a0, 31
+; RV64IB-NEXT:    bclri a0, a0, 31
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclri_i64_31:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbclri a0, a0, 31
+; RV64IBS-NEXT:    bclri a0, a0, 31
 ; RV64IBS-NEXT:    ret
   %and = and i64 %a, -2147483649
   ret i64 %and
 }
 
 define i64 @sbclri_i64_62(i64 %a) nounwind {
 ; RV64I-LABEL: sbclri_i64_62:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
 ; RV64I-NEXT:    slli a1, a1, 62
 ; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclri_i64_62:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbclri a0, a0, 62
+; RV64IB-NEXT:    bclri a0, a0, 62
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclri_i64_62:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbclri a0, a0, 62
+; RV64IBS-NEXT:    bclri a0, a0, 62
 ; RV64IBS-NEXT:    ret
   %and = and i64 %a, -4611686018427387905
   ret i64 %and
 }
 
 define i64 @sbclri_i64_63(i64 %a) nounwind {
 ; RV64I-LABEL: sbclri_i64_63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
 ; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclri_i64_63:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbclri a0, a0, 63
+; RV64IB-NEXT:    bclri a0, a0, 63
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbclri_i64_63:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbclri a0, a0, 63
+; RV64IBS-NEXT:    bclri a0, a0, 63
 ; RV64IBS-NEXT:    ret
   %and = and i64 %a, -9223372036854775809
   ret i64 %and
 }
 
 define signext i32 @sbseti_i32_10(i32 signext %a) nounwind {
 ; RV64I-LABEL: sbseti_i32_10:
 ; RV64I:       # %bb.0:

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, -2048
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbseti_i64_11:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbseti a0, a0, 11
+; RV64IB-NEXT:    bseti a0, a0, 11
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbseti_i64_11:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbseti a0, a0, 11
+; RV64IBS-NEXT:    bseti a0, a0, 11
 ; RV64IBS-NEXT:    ret
   %or = or i64 %a, 2048
   ret i64 %or
 }
 
 define i64 @sbseti_i64_30(i64 %a) nounwind {
 ; RV64I-LABEL: sbseti_i64_30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 262144
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbseti_i64_30:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbseti a0, a0, 30
+; RV64IB-NEXT:    bseti a0, a0, 30
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbseti_i64_30:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbseti a0, a0, 30
+; RV64IBS-NEXT:    bseti a0, a0, 30
 ; RV64IBS-NEXT:    ret
   %or = or i64 %a, 1073741824
   ret i64 %or
 }
 
 define i64 @sbseti_i64_31(i64 %a) nounwind {
 ; RV64I-LABEL: sbseti_i64_31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    slli a1, a1, 31
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbseti_i64_31:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbseti a0, a0, 31
+; RV64IB-NEXT:    bseti a0, a0, 31
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbseti_i64_31:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbseti a0, a0, 31
+; RV64IBS-NEXT:    bseti a0, a0, 31
 ; RV64IBS-NEXT:    ret
   %or = or i64 %a, 2147483648
   ret i64 %or
 }
 
 define i64 @sbseti_i64_62(i64 %a) nounwind {
 ; RV64I-LABEL: sbseti_i64_62:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    slli a1, a1, 62
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbseti_i64_62:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbseti a0, a0, 62
+; RV64IB-NEXT:    bseti a0, a0, 62
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbseti_i64_62:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbseti a0, a0, 62
+; RV64IBS-NEXT:    bseti a0, a0, 62
 ; RV64IBS-NEXT:    ret
   %or = or i64 %a, 4611686018427387904
   ret i64 %or
 }
 
 define i64 @sbseti_i64_63(i64 %a) nounwind {
 ; RV64I-LABEL: sbseti_i64_63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
 ; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbseti_i64_63:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbseti a0, a0, 63
+; RV64IB-NEXT:    bseti a0, a0, 63
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbseti_i64_63:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbseti a0, a0, 63
+; RV64IBS-NEXT:    bseti a0, a0, 63
 ; RV64IBS-NEXT:    ret
   %or = or i64 %a, 9223372036854775808
   ret i64 %or
 }
 
 define signext i32 @sbinvi_i32_10(i32 signext %a) nounwind {
 ; RV64I-LABEL: sbinvi_i32_10:
 ; RV64I:       # %bb.0:

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, -2048
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinvi_i64_11:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbinvi a0, a0, 11
+; RV64IB-NEXT:    binvi a0, a0, 11
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinvi_i64_11:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbinvi a0, a0, 11
+; RV64IBS-NEXT:    binvi a0, a0, 11
 ; RV64IBS-NEXT:    ret
   %xor = xor i64 %a, 2048
   ret i64 %xor
 }
 
 define i64 @sbinvi_i64_30(i64 %a) nounwind {
 ; RV64I-LABEL: sbinvi_i64_30:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 262144
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinvi_i64_30:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbinvi a0, a0, 30
+; RV64IB-NEXT:    binvi a0, a0, 30
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinvi_i64_30:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbinvi a0, a0, 30
+; RV64IBS-NEXT:    binvi a0, a0, 30
 ; RV64IBS-NEXT:    ret
   %xor = xor i64 %a, 1073741824
   ret i64 %xor
 }
 
 define i64 @sbinvi_i64_31(i64 %a) nounwind {
 ; RV64I-LABEL: sbinvi_i64_31:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    slli a1, a1, 31
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinvi_i64_31:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbinvi a0, a0, 31
+; RV64IB-NEXT:    binvi a0, a0, 31
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinvi_i64_31:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbinvi a0, a0, 31
+; RV64IBS-NEXT:    binvi a0, a0, 31
 ; RV64IBS-NEXT:    ret
   %xor = xor i64 %a, 2147483648
   ret i64 %xor
 }
 
 define i64 @sbinvi_i64_62(i64 %a) nounwind {
 ; RV64I-LABEL: sbinvi_i64_62:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    slli a1, a1, 62
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinvi_i64_62:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbinvi a0, a0, 62
+; RV64IB-NEXT:    binvi a0, a0, 62
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinvi_i64_62:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbinvi a0, a0, 62
+; RV64IBS-NEXT:    binvi a0, a0, 62
 ; RV64IBS-NEXT:    ret
   %xor = xor i64 %a, 4611686018427387904
   ret i64 %xor
 }
 
 define i64 @sbinvi_i64_63(i64 %a) nounwind {
 ; RV64I-LABEL: sbinvi_i64_63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
 ; RV64I-NEXT:    slli a1, a1, 63
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbinvi_i64_63:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    sbinvi a0, a0, 63
+; RV64IB-NEXT:    binvi a0, a0, 63
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBS-LABEL: sbinvi_i64_63:
 ; RV64IBS:       # %bb.0:
-; RV64IBS-NEXT:    sbinvi a0, a0, 63
+; RV64IBS-NEXT:    binvi a0, a0, 63
 ; RV64IBS-NEXT:    ret
   %xor = xor i64 %a, 9223372036854775808
   ret i64 %xor
 }

llvm/test/MC/RISCV/rv32zbe-invalid.s

 # RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s
 
 # Too few operands
-bdep t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-bext t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bcompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32zbe-valid.s

 # With B extension:
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # With Bitmanip extract/deposit extension:
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbe -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbe < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-zbe -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: bdep t0, t1, t2
+# CHECK-ASM-AND-OBJ: bdecompress t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x62,0x73,0x48]
-bdep t0, t1, t2
-# CHECK-ASM-AND-OBJ: bext t0, t1, t2
+bdecompress t0, t1, t2
+# CHECK-ASM-AND-OBJ: bcompress t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x62,0x73,0x08]
-bext t0, t1, t2
+bcompress t0, t1, t2

llvm/test/MC/RISCV/rv32zbs-invalid.s

 # RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbs < %s 2>&1 | FileCheck %s
 
 # Too few operands
-sbclr t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bclr t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-sbset t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bset t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-sbinv t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+binv t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-sbext t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bext t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-sbclri t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bclri t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
-sbclri t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
-sbclri t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+bclri t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
+bclri t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
 # Too few operands
-sbseti t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bseti t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
-sbseti t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
-sbseti t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+bseti t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
+bseti t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
 # Too few operands
-sbinvi t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+binvi t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
-sbinvi t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
-sbinvi t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+binvi t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
+binvi t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
 # Too few operands
-sbexti t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bexti t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
-sbexti t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
-sbexti t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+bexti t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
+bexti t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv32zbs-valid.s

 # With B extension:
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-b -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-b < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # With Bitmanip single bit extension:
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbs < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-zbs -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: sbclr t0, t1, t2
+# CHECK-ASM-AND-OBJ: bclr t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x12,0x73,0x48]
-sbclr t0, t1, t2
-# CHECK-ASM-AND-OBJ: sbset t0, t1, t2
+bclr t0, t1, t2
+# CHECK-ASM-AND-OBJ: bset t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x12,0x73,0x28]
-sbset t0, t1, t2
-# CHECK-ASM-AND-OBJ: sbinv t0, t1, t2
+bset t0, t1, t2
+# CHECK-ASM-AND-OBJ: binv t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x12,0x73,0x68]
-sbinv t0, t1, t2
-# CHECK-ASM-AND-OBJ: sbext t0, t1, t2
+binv t0, t1, t2
+# CHECK-ASM-AND-OBJ: bext t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x52,0x73,0x48]
-sbext t0, t1, t2
-# CHECK-ASM-AND-OBJ: sbclri t0, t1, 1
+bext t0, t1, t2
+# CHECK-ASM-AND-OBJ: bclri t0, t1, 1
 # CHECK-ASM: encoding: [0x93,0x12,0x13,0x48]
-sbclri t0, t1, 1
-# CHECK-ASM-AND-OBJ: sbseti t0, t1, 1
+bclri t0, t1, 1
+# CHECK-ASM-AND-OBJ: bseti t0, t1, 1
 # CHECK-ASM: encoding: [0x93,0x12,0x13,0x28]
-sbseti t0, t1, 1
-# CHECK-ASM-AND-OBJ: sbinvi t0, t1, 1
+bseti t0, t1, 1
+# CHECK-ASM-AND-OBJ: binvi t0, t1, 1
 # CHECK-ASM: encoding: [0x93,0x12,0x13,0x68]
-sbinvi t0, t1, 1
-# CHECK-ASM-AND-OBJ: sbexti t0, t1, 1
+binvi t0, t1, 1
+# CHECK-ASM-AND-OBJ: bexti t0, t1, 1
 # CHECK-ASM: encoding: [0x93,0x52,0x13,0x48]
-sbexti t0, t1, 1
+bexti t0, t1, 1

llvm/test/MC/RISCV/rv64zbe-invalid.s

 # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s
 
 # Too few operands
-bdepw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bdecompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-bextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bcompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zbe-valid.s

 # With B extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # With Bitmanip extract/deposit extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbe -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbe < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-zbe -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: bdepw t0, t1, t2
+# CHECK-ASM-AND-OBJ: bdecompressw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x62,0x73,0x48]
-bdepw t0, t1, t2
-# CHECK-ASM-AND-OBJ: bextw t0, t1, t2
+bdecompressw t0, t1, t2
+# CHECK-ASM-AND-OBJ: bcompressw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x62,0x73,0x08]
-bextw t0, t1, t2
+bcompressw t0, t1, t2

llvm/test/MC/RISCV/rv64zbs-invalid.s

 # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbs < %s 2>&1 | FileCheck %s
 
 # Too few operands
-sbclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-sbsetw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bsetw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-sbinvw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+binvw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-sbextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-sbclriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bclriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
-sbclriw t0, t1, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
-sbclriw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+bclriw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+bclriw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
 # Too few operands
-sbsetiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+bsetiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
-sbsetiw t0, t1, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
-sbsetiw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+bsetiw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+bsetiw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
 # Too few operands
-sbinviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+binviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
-sbinviw t0, t1, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
-sbinviw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
+binviw t0, t1, 32 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+binviw t0, t1, -1 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv64zbs-valid.s

 # With B extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # With Bitmanip single bit extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbs < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-zbs -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: sbclrw t0, t1, t2
+# CHECK-ASM-AND-OBJ: bclrw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48]
-sbclrw t0, t1, t2
-# CHECK-ASM-AND-OBJ: sbsetw t0, t1, t2
+bclrw t0, t1, t2
+# CHECK-ASM-AND-OBJ: bsetw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x12,0x73,0x28]
-sbsetw t0, t1, t2
-# CHECK-ASM-AND-OBJ: sbinvw t0, t1, t2
+bsetw t0, t1, t2
+# CHECK-ASM-AND-OBJ: binvw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x12,0x73,0x68]
-sbinvw t0, t1, t2
-# CHECK-ASM-AND-OBJ: sbextw t0, t1, t2
+binvw t0, t1, t2
+# CHECK-ASM-AND-OBJ: bextw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x52,0x73,0x48]
-sbextw t0, t1, t2
-# CHECK-ASM-AND-OBJ: sbclriw  t0, t1, 0
+bextw t0, t1, t2
+# CHECK-ASM-AND-OBJ: bclriw  t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x48]
-sbclriw t0, t1, 0
-# CHECK-ASM-AND-OBJ: sbsetiw  t0, t1, 0
+bclriw  t0, t1, 0
+# CHECK-ASM-AND-OBJ: bsetiw  t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x28]
-sbsetiw t0, t1, 0
-# CHECK-ASM-AND-OBJ: sbinviw  t0, t1, 0
+bsetiw  t0, t1, 0
+# CHECK-ASM-AND-OBJ: binviw  t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x68]
-sbinviw t0, t1, 0
+binviw  t0, t1, 0