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Differential D94580

[RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec.
ClosedPublic

Authored by craig.topper on Jan 12 2021, 8:20 PM.

Details

Reviewers
asb
luismarques
frasercrmck
kito-cheng
simoncook
PaoloS
lewis-revill
lenary
Commits
rGd985c7321f0b: [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 12 2021, 8:20 PM
Herald added subscribers: NickHung, evandro, apazos and 22 others. · View Herald TranscriptJan 12 2021, 8:20 PM
craig.topper requested review of this revision.Jan 12 2021, 8:20 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 12 2021, 8:20 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B84969: Diff 316313.Jan 12 2021, 8:57 PM
lenary resigned from this revision.Jan 14 2021, 9:25 AM
craig.topper added reviewers: simoncook, PaoloS, lewis-revill.Jan 14 2021, 12:59 PM
craig.topper added a parent revision: D94577: [RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0.93 bitmanip spec..Jan 14 2021, 1:04 PM
craig.topper added a child revision: D94582: [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec..
frasercrmck accepted this revision.Jan 15 2021, 7:24 AM

LGTM

This revision is now accepted and ready to land.Jan 15 2021, 7:24 AM
craig.topper updated this revision to Diff 318028.Jan 20 2021, 3:09 PM

Rebase

Harbormaster completed remote builds in B85986: Diff 318028.Jan 20 2021, 6:47 PM
asb accepted this revision.Jan 21 2021, 7:13 AM
Closed by commit rGd985c7321f0b: [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec. (authored by craig.topper). · Explain WhyJan 22 2021, 12:51 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGd985c7321f0b: [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
4 lines
test/
MC/
RISCV/
8 lines

Diff 318028

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

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let Predicates = [HasStdExtZbc] in { let Predicates = [HasStdExtZbc] in {
def CLMUL : ALU_rr<0b0000101, 0b001, "clmul">, Sched<[]>; def CLMUL : ALU_rr<0b0000101, 0b001, "clmul">, Sched<[]>;
def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">, Sched<[]>; def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">, Sched<[]>;
def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>; def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>;
} // Predicates = [HasStdExtZbc] } // Predicates = [HasStdExtZbc]
let Predicates = [HasStdExtZbb] in { let Predicates = [HasStdExtZbb] in {
def MIN : ALU_rr<0b0000101, 0b100, "min">, Sched<[]>; def MIN : ALU_rr<0b0000101, 0b100, "min">, Sched<[]>;
def MAX : ALU_rr<0b0000101, 0b101, "max">, Sched<[]>; def MINU : ALU_rr<0b0000101, 0b101, "minu">, Sched<[]>;
def MINU : ALU_rr<0b0000101, 0b110, "minu">, Sched<[]>; def MAX : ALU_rr<0b0000101, 0b110, "max">, Sched<[]>;
def MAXU : ALU_rr<0b0000101, 0b111, "maxu">, Sched<[]>; def MAXU : ALU_rr<0b0000101, 0b111, "maxu">, Sched<[]>;
} // Predicates = [HasStdExtZbb] } // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbp] in { let Predicates = [HasStdExtZbp] in {
def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>; def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>; def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
} // Predicates = [HasStdExtZbp] } // Predicates = [HasStdExtZbp]
▲ Show 20 Lines • Show All 579 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/rv32zbb-valid.s

Show All 36 Lines
# CHECK-ASM: encoding: [0x93,0x12,0x43,0x60] # CHECK-ASM: encoding: [0x93,0x12,0x43,0x60]
sext.b t0, t1 sext.b t0, t1
# CHECK-ASM-AND-OBJ: sext.h t0, t1 # CHECK-ASM-AND-OBJ: sext.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60] # CHECK-ASM: encoding: [0x93,0x12,0x53,0x60]
sext.h t0, t1 sext.h t0, t1
# CHECK-ASM-AND-OBJ: min t0, t1, t2 # CHECK-ASM-AND-OBJ: min t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a] # CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
min t0, t1, t2 min t0, t1, t2
# CHECK-ASM-AND-OBJ: max t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
max t0, t1, t2
# CHECK-ASM-AND-OBJ: minu t0, t1, t2 # CHECK-ASM-AND-OBJ: minu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a] # CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
minu t0, t1, t2 minu t0, t1, t2
# CHECK-ASM-AND-OBJ: max t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
max t0, t1, t2
# CHECK-ASM-AND-OBJ: maxu t0, t1, t2 # CHECK-ASM-AND-OBJ: maxu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a] # CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a]
maxu t0, t1, t2 maxu t0, t1, t2