[RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0.93 bitmanip spec.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

378

Hard for me to say for sure as I'm just browsing the code, but it looks to me like RVBALUW_ri is now unused.

[craig.topper]

Remove unused class

[frasercrmck]

LGTM

[craig.topper]

Rebase

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 class RVBUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3,
                RISCVOpcode opcode, string opcodestr>
     : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
               opcodestr, "$rd, $rs1"> {
   let Inst{24-20} = funct5;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBALUW_ri<bits<3> funct3, string opcodestr>
-    : RVInstI<funct3, OPC_OP_IMM_32, (outs GPR:$rd),
-              (ins GPR:$rs1, simm12:$imm12), opcodestr, "$rd, $rs1, $imm12">;
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVBShift_ri<bits<5> funct5, bits<3> funct3, RISCVOpcode opcode,
                   string opcodestr>
     : RVInstI<funct3, opcode, (outs GPR:$rd),
               (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
               "$rd, $rs1, $shamt"> {
   bits<6> shamt;
 
   let Inst{31-27} = funct5;

 def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
 
 let Predicates = [HasStdExtZbp] in {
 def SHFLI   : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
 def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
-def ADDIWU : RVBALUW_ri<0b100, "addiwu">, Sched<[]>;
 def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">, Sched<[]>;
-def ADDWU : ALUW_rr<0b0000101, 0b000, "addwu">, Sched<[]>;
-def SUBWU : ALUW_rr<0b0100101, 0b000, "subwu">, Sched<[]>;
 def ADDUW : ALUW_rr<0b0000100, 0b000, "addu.w">, Sched<[]>;
-def SUBUW : ALUW_rr<0b0100100, 0b000, "subu.w">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def SLOW   : ALUW_rr<0b0010000, 0b001, "slow">, Sched<[]>;
 def SROW   : ALUW_rr<0b0010000, 0b101, "srow">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {

 def CLZW   : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0011011>,
                       "clzw">, Sched<[]>;
 def CTZW   : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0011011>,
                       "ctzw">, Sched<[]>;
 def CPOPW  : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>,
                       "cpopw">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
-let Predicates = [HasStdExtZbc, IsRV64] in {
-def CLMULW  : ALUW_rr<0b0000101, 0b001, "clmulw">, Sched<[]>;
-def CLMULRW : ALUW_rr<0b0000101, 0b010, "clmulrw">, Sched<[]>;
-def CLMULHW : ALUW_rr<0b0000101, 0b011, "clmulhw">, Sched<[]>;
-} // Predicates = [HasStdExtZbc, IsRV64]
-
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def SHFLW   : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
 def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbe, IsRV64] in {
 def BDEPW : ALUW_rr<0b0100100, 0b110, "bdepw">, Sched<[]>;
 def BEXTW : ALUW_rr<0b0000100, 0b110, "bextw">, Sched<[]>;
def : Pat<(or (or (and (shl GPR:$rs1, (i64 2)), (i64 0x3030303030303030)),
           (SHFLI GPR:$rs1, (i64 2))>;
 def : Pat<(or (or (and (shl GPR:$rs1, (i64 1)), (i64 0x4444444444444444)),
                   (and GPR:$rs1, (i64 0x9999999999999999))),
               (and (srl GPR:$rs1, (i64 1)), (i64 0x2222222222222222))),
           (SHFLI GPR:$rs1, (i64 1))>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
-def : Pat<(and (add GPR:$rs, simm12:$simm12), (i64 0xFFFFFFFF)),
-          (ADDIWU GPR:$rs, simm12:$simm12)>;
 def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
 def : Pat<(shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt),
           (SLLIUW GPR:$rs1, uimm5:$shamt)>;
-def : Pat<(and (add GPR:$rs1, GPR:$rs2), (i64 0xFFFFFFFF)),
-          (ADDWU GPR:$rs1, GPR:$rs2)>;
-def : Pat<(and (sub GPR:$rs1, GPR:$rs2), (i64 0xFFFFFFFF)),
-          (SUBWU GPR:$rs1, GPR:$rs2)>;
 def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
           (ADDUW GPR:$rs1, GPR:$rs2)>;
-def : Pat<(sub GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
-          (SUBUW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)),
           (SLOW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(not (riscv_srlw (not GPR:$rs1), GPR:$rs2)),
           (SROW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
 def : Pat<(riscv_rolw GPR:$rs1, GPR:$rs2),

llvm/test/CodeGen/RISCV/rv64Zbb.ll

 ; RV64IBB:       # %bb.0:
 ; RV64IBB-NEXT:    neg a1, a0
 ; RV64IBB-NEXT:    max a0, a0, a1
 ; RV64IBB-NEXT:    ret
   %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
   ret i64 %abs
 }
 
-; We select a i32 addi that zero-extends the result on RV64 as addiwu
-
-define zeroext i32 @zext_add_to_addiwu(i32 signext %a) nounwind {
-; RV64I-LABEL: zext_add_to_addiwu:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: zext_add_to_addiwu:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addiwu a0, a0, 1
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: zext_add_to_addiwu:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    addiwu a0, a0, 1
-; RV64IBB-NEXT:    ret
-  %add = add i32 %a, 1
-  ret i32 %add
-}
-
-define i64 @addiwu(i64 %a) nounwind {
-; RV64I-LABEL: addiwu:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: addiwu:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addiwu a0, a0, 1
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: addiwu:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    addiwu a0, a0, 1
-; RV64IBB-NEXT:    ret
-  %conv = add i64 %a, 1
-  %conv1 = and i64 %conv, 4294967295
-  ret i64 %conv1
-}
-
 define i64 @slliuw(i64 %a) nounwind {
 ; RV64I-LABEL: slliuw:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    addi a1, zero, 1
 ; RV64I-NEXT:    slli a1, a1, 33
 ; RV64I-NEXT:    addi a1, a1, -2
 ; RV64I-NEXT:    and a0, a0, a1

 ; RV64IBB-NEXT:    ld a1, 8(a1)
 ; RV64IBB-NEXT:    ret
   %3 = zext i32 %0 to i64
   %4 = getelementptr inbounds i128, i128* %1, i64 %3
   %5 = load i128, i128* %4
   ret i128 %5
 }
 
-; We select a i32 add that zero-extends the result on RV64 as addwu
-
-define zeroext i32 @zext_add_to_addwu(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: zext_add_to_addwu:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    add a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: zext_add_to_addwu:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addwu a0, a0, a1
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: zext_add_to_addwu:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    addwu a0, a0, a1
-; RV64IBB-NEXT:    ret
-  %add = add i32 %a, %b
-  ret i32 %add
-}
-
-define i64 @addwu(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: addwu:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    add a0, a1, a0
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: addwu:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addwu a0, a1, a0
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: addwu:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    addwu a0, a1, a0
-; RV64IBB-NEXT:    ret
-  %add = add i64 %b, %a
-  %conv1 = and i64 %add, 4294967295
-  ret i64 %conv1
-}
-
-; We select a i32 sub that zero-extends the result on RV64 as subwu
-
-define zeroext i32 @zext_sub_to_subwu(i32 signext %a, i32 signext %b) nounwind {
-; RV64I-LABEL: zext_sub_to_subwu:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: zext_sub_to_subwu:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    subwu a0, a0, a1
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: zext_sub_to_subwu:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    subwu a0, a0, a1
-; RV64IBB-NEXT:    ret
-  %sub = sub i32 %a, %b
-  ret i32 %sub
-}
-
-define i64 @subwu(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: subwu:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: subwu:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    subwu a0, a0, a1
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: subwu:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    subwu a0, a0, a1
-; RV64IBB-NEXT:    ret
-  %sub = sub i64 %a, %b
-  %conv1 = and i64 %sub, 4294967295
-  ret i64 %conv1
-}
-
 define i64 @adduw(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: adduw:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    ret
 ;

 ; RV64IBB-NEXT:    addu.w a0, a1, a0
 ; RV64IBB-NEXT:    lb a0, 0(a0)
 ; RV64IBB-NEXT:    ret
   %3 = zext i32 %0 to i64
   %4 = getelementptr inbounds i8, i8* %1, i64 %3
   %5 = load i8, i8* %4
   ret i8 %5
 }
-
-define i64 @subuw(i64 %a, i64 %b) nounwind {
-; RV64I-LABEL: subuw:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
-; RV64I-NEXT:    sub a0, a0, a1
-; RV64I-NEXT:    ret
-;
-; RV64IB-LABEL: subuw:
-; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    subu.w a0, a0, a1
-; RV64IB-NEXT:    ret
-;
-; RV64IBB-LABEL: subuw:
-; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    subu.w a0, a0, a1
-; RV64IBB-NEXT:    ret
-  %and = and i64 %b, 4294967295
-  %sub = sub i64 %a, %and
-  ret i64 %sub
-}

llvm/test/MC/RISCV/rv64zbb-invalid.s

 # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbb < %s 2>&1 | FileCheck %s
 
 # Too few operands
-addiwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Immediate operand out of range
-addiwu t0, t1, 2048 # CHECK: :[[@LINE]]:16: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
-addiwu t0, t1, -2049 # CHECK: :[[@LINE]]:16: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
-# Too few operands
 slliu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
 slliu.w t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
 slliu.w t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
 # Too few operands
-addwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
-subwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
 addu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
-subu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
 slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 srow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 sloiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
 sloiw t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
 sloiw t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv64zbb-valid.s

 # With B extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
 # With Bitmanip base extension:
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-zbb -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: addiwu t0, t1, 0
-# CHECK-ASM: encoding: [0x9b,0x42,0x03,0x00]
-addiwu t0, t1, 0
 # CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
 slliu.w t0, t1, 0
-# CHECK-ASM-AND-OBJ: addwu t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x0a]
-addwu t0, t1, t2
-# CHECK-ASM-AND-OBJ: subwu t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x4a]
-subwu t0, t1, t2
 # CHECK-ASM-AND-OBJ: addu.w t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
 addu.w t0, t1, t2
-# CHECK-ASM-AND-OBJ: subu.w t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x48]
-subu.w t0, t1, t2
 # CHECK-ASM-AND-OBJ: slow t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
 slow t0, t1, t2
 # CHECK-ASM-AND-OBJ: srow t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x52,0x73,0x20]
 srow t0, t1, t2
 # CHECK-ASM-AND-OBJ: sloiw t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x20]

llvm/test/MC/RISCV/rv64zbc-invalid.s

-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbc < %s 2>&1 | FileCheck %s
-
-# Too few operands
-clmulw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
-clmulrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
-# Too few operands
-clmulhw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zbc-valid.s

-# With B extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-b -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-# With Bitmanip carry-less multiply extension:
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbc -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbc < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-zbc -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-# CHECK-ASM-AND-OBJ: clmulw t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x0a]
-clmulw t0, t1, t2
-# CHECK-ASM-AND-OBJ: clmulrw t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x22,0x73,0x0a]
-clmulrw t0, t1, t2
-# CHECK-ASM-AND-OBJ: clmulhw t0, t1, t2
-# CHECK-ASM: encoding: [0xbb,0x32,0x73,0x0a]
-clmulhw t0, t1, t2