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Differential D94577

[RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0.93 bitmanip spec.
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Authored by craig.topper on Jan 12 2021, 6:42 PM.

Details

Reviewers
asb
luismarques
frasercrmck
lewis-revill
PaoloS
simoncook
lenary
Commits
rGb2f859500f19: [RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 12 2021, 6:42 PM
Herald added subscribers: NickHung, evandro, apazos and 23 others. · View Herald TranscriptJan 12 2021, 6:42 PM
craig.topper requested review of this revision.Jan 12 2021, 6:42 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 12 2021, 6:42 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B84965: Diff 316304.Jan 12 2021, 6:45 PM
lenary resigned from this revision.Jan 14 2021, 9:25 AM
craig.topper added reviewers: lewis-revill, PaoloS, simoncook.Jan 14 2021, 12:59 PM
craig.topper added a parent revision: D94568: [RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec..Jan 14 2021, 1:04 PM
craig.topper added a child revision: D94580: [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec..
frasercrmck added inline comments.Jan 15 2021, 7:23 AM
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
378

Hard for me to say for sure as I'm just browsing the code, but it looks to me like RVBALUW_ri is now unused.

craig.topper updated this revision to Diff 317034.Jan 15 2021, 11:36 AM

Remove unused class

Harbormaster completed remote builds in B85399: Diff 317034.Jan 15 2021, 12:17 PM
frasercrmck accepted this revision.Jan 18 2021, 7:24 AM

LGTM

This revision is now accepted and ready to land.Jan 18 2021, 7:24 AM
craig.topper updated this revision to Diff 318027.Jan 20 2021, 3:07 PM

Rebase

Harbormaster completed remote builds in B85985: Diff 318027.Jan 20 2021, 6:38 PM
asb accepted this revision.Jan 21 2021, 7:11 AM
Closed by commit rGb2f859500f19: [RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0. (authored by craig.topper). · Explain WhyJan 22 2021, 12:50 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGb2f859500f19: [RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
18 lines
test/
CodeGen/
RISCV/
157 lines
MC/
RISCV/
11 lines
12 lines

Diff 316304

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

Show First 20 Lines • Show All 369 Lines • ▼ Show 20 Lines
def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>; def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
let Predicates = [HasStdExtZbp] in { let Predicates = [HasStdExtZbp] in {
def SHFLI : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>; def SHFLI : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>; def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
} // Predicates = [HasStdExtZbp] } // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZbb, IsRV64] in { let Predicates = [HasStdExtZbb, IsRV64] in {
def ADDIWU : RVBALUW_ri<0b100, "addiwu">, Sched<[]>;
frasercrmckUnsubmitted
Not Done
ReplyInline Actions

Hard for me to say for sure as I'm just browsing the code, but it looks to me like RVBALUW_ri is now unused.

frasercrmck: Hard for me to say for sure as I'm just browsing the code, but it looks to me like `RVBALUW_ri`…
def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">, Sched<[]>; def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">, Sched<[]>;
def ADDWU : ALUW_rr<0b0000101, 0b000, "addwu">, Sched<[]>;
def SUBWU : ALUW_rr<0b0100101, 0b000, "subwu">, Sched<[]>;
def ADDUW : ALUW_rr<0b0000100, 0b000, "addu.w">, Sched<[]>; def ADDUW : ALUW_rr<0b0000100, 0b000, "addu.w">, Sched<[]>;
def SUBUW : ALUW_rr<0b0100100, 0b000, "subu.w">, Sched<[]>;
} // Predicates = [HasStdExtZbb, IsRV64] } // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbb, IsRV64] in { let Predicates = [HasStdExtZbb, IsRV64] in {
def SLOW : ALUW_rr<0b0010000, 0b001, "slow">, Sched<[]>; def SLOW : ALUW_rr<0b0010000, 0b001, "slow">, Sched<[]>;
def SROW : ALUW_rr<0b0010000, 0b101, "srow">, Sched<[]>; def SROW : ALUW_rr<0b0010000, 0b101, "srow">, Sched<[]>;
} // Predicates = [HasStdExtZbb, IsRV64] } // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0011011>, def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0011011>,
"clzw">, Sched<[]>; "clzw">, Sched<[]>;
def CTZW : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0011011>, def CTZW : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0011011>,
"ctzw">, Sched<[]>; "ctzw">, Sched<[]>;
def CPOPW : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>, def CPOPW : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>,
"cpopw">, Sched<[]>; "cpopw">, Sched<[]>;
} // Predicates = [HasStdExtZbb, IsRV64] } // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbc, IsRV64] in {
def CLMULW : ALUW_rr<0b0000101, 0b001, "clmulw">, Sched<[]>;
def CLMULRW : ALUW_rr<0b0000101, 0b010, "clmulrw">, Sched<[]>;
def CLMULHW : ALUW_rr<0b0000101, 0b011, "clmulhw">, Sched<[]>;
} // Predicates = [HasStdExtZbc, IsRV64]
let Predicates = [HasStdExtZbp, IsRV64] in { let Predicates = [HasStdExtZbp, IsRV64] in {
def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>; def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>; def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
} // Predicates = [HasStdExtZbp, IsRV64] } // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbe, IsRV64] in { let Predicates = [HasStdExtZbe, IsRV64] in {
def BDEPW : ALUW_rr<0b0100100, 0b110, "bdepw">, Sched<[]>; def BDEPW : ALUW_rr<0b0100100, 0b110, "bdepw">, Sched<[]>;
def BEXTW : ALUW_rr<0b0000100, 0b110, "bextw">, Sched<[]>; def BEXTW : ALUW_rr<0b0000100, 0b110, "bextw">, Sched<[]>;
▲ Show 20 Lines • Show All 467 Lines • ▼ Show 20 Linesdef : Pat<(or (or (and (shl GPR:$rs1, (i64 2)), (i64 0x3030303030303030)),
(SHFLI GPR:$rs1, (i64 2))>; (SHFLI GPR:$rs1, (i64 2))>;
def : Pat<(or (or (and (shl GPR:$rs1, (i64 1)), (i64 0x4444444444444444)), def : Pat<(or (or (and (shl GPR:$rs1, (i64 1)), (i64 0x4444444444444444)),
(and GPR:$rs1, (i64 0x9999999999999999))), (and GPR:$rs1, (i64 0x9999999999999999))),
(and (srl GPR:$rs1, (i64 1)), (i64 0x2222222222222222))), (and (srl GPR:$rs1, (i64 1)), (i64 0x2222222222222222))),
(SHFLI GPR:$rs1, (i64 1))>; (SHFLI GPR:$rs1, (i64 1))>;
} // Predicates = [HasStdExtZbp, IsRV64] } // Predicates = [HasStdExtZbp, IsRV64]
let Predicates = [HasStdExtZbb, IsRV64] in { let Predicates = [HasStdExtZbb, IsRV64] in {
def : Pat<(and (add GPR:$rs, simm12:$simm12), (i64 0xFFFFFFFF)),
(ADDIWU GPR:$rs, simm12:$simm12)>;
def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt), def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
(SLLIUW GPR:$rs1, uimm5:$shamt)>; (SLLIUW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(and (add GPR:$rs1, GPR:$rs2), (i64 0xFFFFFFFF)),
(ADDWU GPR:$rs1, GPR:$rs2)>;
def : Pat<(and (sub GPR:$rs1, GPR:$rs2), (i64 0xFFFFFFFF)),
(SUBWU GPR:$rs1, GPR:$rs2)>;
def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))), def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
(ADDUW GPR:$rs1, GPR:$rs2)>; (ADDUW GPR:$rs1, GPR:$rs2)>;
def : Pat<(sub GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
(SUBUW GPR:$rs1, GPR:$rs2)>;
def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)), def : Pat<(not (riscv_sllw (not GPR:$rs1), GPR:$rs2)),
(SLOW GPR:$rs1, GPR:$rs2)>; (SLOW GPR:$rs1, GPR:$rs2)>;
def : Pat<(not (riscv_srlw (not GPR:$rs1), GPR:$rs2)), def : Pat<(not (riscv_srlw (not GPR:$rs1), GPR:$rs2)),
(SROW GPR:$rs1, GPR:$rs2)>; (SROW GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbb, IsRV64] } // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
def : Pat<(riscv_rolw GPR:$rs1, GPR:$rs2), def : Pat<(riscv_rolw GPR:$rs1, GPR:$rs2),
▲ Show 20 Lines • Show All 85 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64Zbb.ll

Show First 20 Lines • Show All 982 Lines • ▼ Show 20 Lines
; RV64IBB: # %bb.0: ; RV64IBB: # %bb.0:
; RV64IBB-NEXT: neg a1, a0 ; RV64IBB-NEXT: neg a1, a0
; RV64IBB-NEXT: max a0, a0, a1 ; RV64IBB-NEXT: max a0, a0, a1
; RV64IBB-NEXT: ret ; RV64IBB-NEXT: ret
%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
ret i64 %abs ret i64 %abs
} }
; We select a i32 addi that zero-extends the result on RV64 as addiwu
define zeroext i32 @zext_add_to_addiwu(i32 signext %a) nounwind {
; RV64I-LABEL: zext_add_to_addiwu:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64IB-LABEL: zext_add_to_addiwu:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addiwu a0, a0, 1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: zext_add_to_addiwu:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: addiwu a0, a0, 1
; RV64IBB-NEXT: ret
%add = add i32 %a, 1
ret i32 %add
}
define i64 @addiwu(i64 %a) nounwind {
; RV64I-LABEL: addiwu:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64IB-LABEL: addiwu:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addiwu a0, a0, 1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: addiwu:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: addiwu a0, a0, 1
; RV64IBB-NEXT: ret
%conv = add i64 %a, 1
%conv1 = and i64 %conv, 4294967295
ret i64 %conv1
}
define i64 @slliuw(i64 %a) nounwind { define i64 @slliuw(i64 %a) nounwind {
; RV64I-LABEL: slliuw: ; RV64I-LABEL: slliuw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: addi a1, zero, 1 ; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 33 ; RV64I-NEXT: slli a1, a1, 33
; RV64I-NEXT: addi a1, a1, -2 ; RV64I-NEXT: addi a1, a1, -2
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: slliuw: ; RV64IB-LABEL: slliuw:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: slliu.w a0, a0, 1 ; RV64IB-NEXT: slliu.w a0, a0, 1
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBB-LABEL: slliuw: ; RV64IBB-LABEL: slliuw:
; RV64IBB: # %bb.0: ; RV64IBB: # %bb.0:
; RV64IBB-NEXT: slliu.w a0, a0, 1 ; RV64IBB-NEXT: slliu.w a0, a0, 1
; RV64IBB-NEXT: ret ; RV64IBB-NEXT: ret
%conv1 = shl i64 %a, 1 %conv1 = shl i64 %a, 1
%shl = and i64 %conv1, 8589934590 %shl = and i64 %conv1, 8589934590
ret i64 %shl ret i64 %shl
} }
; We select a i32 add that zero-extends the result on RV64 as addwu
define zeroext i32 @zext_add_to_addwu(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_add_to_addwu:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64IB-LABEL: zext_add_to_addwu:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addwu a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: zext_add_to_addwu:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: addwu a0, a0, a1
; RV64IBB-NEXT: ret
%add = add i32 %a, %b
ret i32 %add
}
define i64 @addwu(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: addwu:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64IB-LABEL: addwu:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addwu a0, a1, a0
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: addwu:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: addwu a0, a1, a0
; RV64IBB-NEXT: ret
%add = add i64 %b, %a
%conv1 = and i64 %add, 4294967295
ret i64 %conv1
}
; We select a i32 sub that zero-extends the result on RV64 as subwu
define zeroext i32 @zext_sub_to_subwu(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: zext_sub_to_subwu:
; RV64I: # %bb.0:
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64IB-LABEL: zext_sub_to_subwu:
; RV64IB: # %bb.0:
; RV64IB-NEXT: subwu a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: zext_sub_to_subwu:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: subwu a0, a0, a1
; RV64IBB-NEXT: ret
%sub = sub i32 %a, %b
ret i32 %sub
}
define i64 @subwu(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: subwu:
; RV64I: # %bb.0:
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
;
; RV64IB-LABEL: subwu:
; RV64IB: # %bb.0:
; RV64IB-NEXT: subwu a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: subwu:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: subwu a0, a0, a1
; RV64IBB-NEXT: ret
%sub = sub i64 %a, %b
%conv1 = and i64 %sub, 4294967295
ret i64 %conv1
}
define i64 @adduw(i64 %a, i64 %b) nounwind { define i64 @adduw(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: adduw: ; RV64I-LABEL: adduw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: adduw: ; RV64IB-LABEL: adduw:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: addu.w a0, a0, a1 ; RV64IB-NEXT: addu.w a0, a0, a1
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBB-LABEL: adduw: ; RV64IBB-LABEL: adduw:
; RV64IBB: # %bb.0: ; RV64IBB: # %bb.0:
; RV64IBB-NEXT: addu.w a0, a0, a1 ; RV64IBB-NEXT: addu.w a0, a0, a1
; RV64IBB-NEXT: ret ; RV64IBB-NEXT: ret
%and = and i64 %b, 4294967295 %and = and i64 %b, 4294967295
%add = add i64 %and, %a %add = add i64 %and, %a
ret i64 %add ret i64 %add
} }
define i64 @subuw(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: subuw:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: subuw:
; RV64IB: # %bb.0:
; RV64IB-NEXT: subu.w a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: subuw:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: subu.w a0, a0, a1
; RV64IBB-NEXT: ret
%and = and i64 %b, 4294967295
%sub = sub i64 %a, %and
ret i64 %sub
}

llvm/test/MC/RISCV/rv64zbb-invalid.s

# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbb < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbb < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
addiwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range
addiwu t0, t1, 2048 # CHECK: :[[@LINE]]:16: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
addiwu t0, t1, -2049 # CHECK: :[[@LINE]]:16: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
# Too few operands
slliu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction slliu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range # Immediate operand out of range
slliu.w t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63] slliu.w t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
slliu.w t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63] slliu.w t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
# Too few operands # Too few operands
addwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
subwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
addu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction addu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands # Too few operands
subu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands # Too few operands
srow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction srow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands # Too few operands
sloiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction sloiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Immediate operand out of range # Immediate operand out of range
sloiw t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] sloiw t0, t1, 32 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
sloiw t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] sloiw t0, t1, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31]
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llvm/test/MC/RISCV/rv64zbb-valid.s

# With B extension: # With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip base extension: # With Bitmanip base extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \ # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbb -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbb < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbb -d -r - \ # RUN: | llvm-objdump --mattr=+experimental-zbb -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: addiwu t0, t1, 0
# CHECK-ASM: encoding: [0x9b,0x42,0x03,0x00]
addiwu t0, t1, 0
# CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0 # CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08] # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
slliu.w t0, t1, 0 slliu.w t0, t1, 0
# CHECK-ASM-AND-OBJ: addwu t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x0a]
addwu t0, t1, t2
# CHECK-ASM-AND-OBJ: subwu t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x4a]
subwu t0, t1, t2
# CHECK-ASM-AND-OBJ: addu.w t0, t1, t2 # CHECK-ASM-AND-OBJ: addu.w t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08] # CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
addu.w t0, t1, t2 addu.w t0, t1, t2
# CHECK-ASM-AND-OBJ: subu.w t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x48]
subu.w t0, t1, t2
# CHECK-ASM-AND-OBJ: slow t0, t1, t2 # CHECK-ASM-AND-OBJ: slow t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20] # CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
slow t0, t1, t2 slow t0, t1, t2
# CHECK-ASM-AND-OBJ: srow t0, t1, t2 # CHECK-ASM-AND-OBJ: srow t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x20] # CHECK-ASM: encoding: [0xbb,0x52,0x73,0x20]
srow t0, t1, t2 srow t0, t1, t2
# CHECK-ASM-AND-OBJ: sloiw t0, t1, 0 # CHECK-ASM-AND-OBJ: sloiw t0, t1, 0
# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x20] # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x20]
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llvm/test/MC/RISCV/rv64zbc-invalid.s

  • This file was deleted.
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbc < %s 2>&1 | FileCheck %s
# Too few operands
clmulw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
clmulrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Too few operands
clmulhw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64zbc-valid.s

  • This file was deleted.
# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# With Bitmanip carry-less multiply extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbc -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbc < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbc -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: clmulw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x0a]
clmulw t0, t1, t2
# CHECK-ASM-AND-OBJ: clmulrw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x22,0x73,0x0a]
clmulrw t0, t1, t2
# CHECK-ASM-AND-OBJ: clmulhw t0, t1, t2
# CHECK-ASM: encoding: [0xbb,0x32,0x73,0x0a]
clmulhw t0, t1, t2
llvm/test/MC/RISCV/rv64zbb-valid.s