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[RISCV] Define vsext/vzext intrinsics.
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Authored by khchen on Dec 29 2020, 2:21 AM.

Details

Summary

Define vsext/vzext intrinsics.and lower to V instructions.
Define new fraction register class fields in LMULInfo and a
NoReg to present invalid LMUL register classes.

Authored-by: ShihPo Hung <shihpo.hung@sifive.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Diff Detail

Event Timeline

khchen created this revision.Dec 29 2020, 2:21 AM
khchen requested review of this revision.Dec 29 2020, 2:21 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 29 2020, 2:21 AM
craig.topper added inline comments.Dec 29 2020, 2:46 AM
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
456 ↗(On Diff #313950)

Is this really needed? It was already introduced once and removed in a later patch. If it’s never going to be used can we just use an existing register class?

khchen updated this revision to Diff 313963.Dec 29 2020, 5:11 AM

Replace NoVReg with VR and add comment to indicate which is NoVReg.

This revision is now accepted and ready to land.Dec 29 2020, 11:04 AM
This revision was automatically updated to reflect the committed changes.