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[RISCV] Add intrinsics for vcompress instruction
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Authored by arcbbb on Dec 25 2020, 12:31 AM.

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Summary

This patch defines vcompress intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

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Event Timeline

arcbbb created this revision.Dec 25 2020, 12:31 AM
arcbbb requested review of this revision.Dec 25 2020, 12:31 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 25 2020, 12:31 AM
craig.topper added inline comments.Dec 27 2020, 8:43 PM
llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
14

Based on the way this intrinsic is defined, this can't be tail agnostic can it?

arcbbb added inline comments.Dec 28 2020, 1:38 AM
llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
14

Yes, for all intrinsics which maskedoff operand is not Undef, it makes sense to be tail undisturbed.
Since the default vtype is changed to "ta,mu" in D93080,
maybe we can check whether MI.getOperand(MergeOpIndex) is undef or not, and set vtype to corresponding value?

craig.topper accepted this revision.Dec 29 2020, 10:41 AM

LGTM. I've committed 79cbb003c53009e5ca35b804bb7655dba97776e7 which should give a tail undisturbed policy for this intrinsics. Please rebase this patch before commit.

This revision is now accepted and ready to land.Dec 29 2020, 10:41 AM
This revision was automatically updated to reflect the committed changes.