[RISCV] Add support for Zihintpause extention

[mundaym]

Summary

Add support for the 'pause' hint instruction as an alias for
'fence w, 0'. To do this allow the 'fence' operands pred and succ
to be set to 0 (the empty set). This will also allow future hints
to be encoded as 'fence 0, <x>' and 'fence <x>, 0'.

[lenary]

LGTM! Let's wait for the spec to be merged before merging this though.

[luojia]

Hello! I noticed that the pause hint instruction is merged into spec (https://github.com/riscv/riscv-isa-manual/pull/398) and got ratified (https://github.com/riscv/riscv-isa-manual/commit/7a58119dad5bd43e2171a26b56ef60f9591a1c9c).

Should this patch be merged? :) This patch LGTM.

[asb]

In D93019#3166382, @luojia wrote:

Hello! I noticed that the pause hint instruction is merged into spec (https://github.com/riscv/riscv-isa-manual/pull/398) and got ratified (https://github.com/riscv/riscv-isa-manual/commit/7a58119dad5bd43e2171a26b56ef60f9591a1c9c).

Should this patch be merged? :) This patch LGTM.

It just needs to be appropriately gated by a zihintpause attribute.

[achieveartificialintelligence]

Add support for Zihintpause extention

[achieveartificialintelligence]

Since this commit hasn't been updated for a year, I updated it. @mundaym

[achieveartificialintelligence]

Can we land now?@asb @luismarques @lenary

[achieveartificialintelligence]

This patch is accepted a year ago. Could this patch land now?

[asb]

This LGTM.

[mundaym]

@achieveartificialintelligence would you mind creating your revised change as a new patch? I'm going to abandon this. Feel free to include any of my original code.

Once you have done that ping @asb and he can do a quick check and approve again.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

public:
 
   bool isVTypeI() const { return isVType(); }
 
   /// Return true if the operand is a valid for the fence instruction e.g.
   /// ('iorw').
   bool isFenceArg() const {
     if (!isImm())
       return false;
-    const MCExpr *Val = getImm();
-    auto *SVal = dyn_cast<MCSymbolRefExpr>(Val);
+
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (evaluateConstantImm(getImm(), Imm, VK)) {
+      // Only accept 0 as a constant immediate.
+      return VK == RISCVMCExpr::VK_RISCV_None && Imm == 0;
+    }
+
+    auto *SVal = dyn_cast<MCSymbolRefExpr>(getImm());
     if (!SVal || SVal->getKind() != MCSymbolRefExpr::VK_None)
       return false;
 
     StringRef Str = SVal->getSymbol().getName();
     // Letters must be unique, taken from 'iorw', and in ascending order. This
     // holds as long as each individual character is one of 'iorw' and is
     // greater than the previous character.
     char Prev = '\0';
void addSImm5Plus1Operands(MCInst &Inst, unsigned N) const {
     bool IsConstant = evaluateConstantImm(getImm(), Imm, VK);
     assert(IsConstant && "Expect constant value!");
     (void)IsConstant;
     Inst.addOperand(MCOperand::createImm(Imm - 1));
   }
 
   void addFenceArgOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
+
+    int64_t Constant = 0;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (evaluateConstantImm(getImm(), Constant, VK)) {
+      if (Constant == 0) {
+        Inst.addOperand(MCOperand::createImm(Constant));
+        return;
+      }
+      llvm_unreachable("FenceArg must contain only [iorw] or be 0");
+    }
+
     // isFenceArg has validated the operand, meaning this cast is safe
     auto SE = cast<MCSymbolRefExpr>(getImm());
-
     unsigned Imm = 0;
     for (char c : SE->getSymbol().getName()) {
       switch (c) {
       default:
-        llvm_unreachable("FenceArg must contain only [iorw]");
+        llvm_unreachable("FenceArg must contain only [iorw] or be 0");
       case 'i': Imm |= RISCVFenceField::I; break;
       case 'o': Imm |= RISCVFenceField::O; break;
       case 'r': Imm |= RISCVFenceField::R; break;
       case 'w': Imm |= RISCVFenceField::W; break;
       }
     }
     Inst.addOperand(MCOperand::createImm(Imm));
   }
return generateImmOutOfRangeError(
         "immediate must be a multiple of 2 bytes in the range");
   case Match_InvalidCSRSystemRegister: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 12) - 1,
                                       "operand must be a valid system register "
                                       "name or an integer in the range");
   }
   case Match_InvalidFenceArg: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
-    return Error(
-        ErrorLoc,
-        "operand must be formed of letters selected in-order from 'iorw'");
+    return Error(ErrorLoc, "operand must be formed of letters selected "
+                           "in-order from 'iorw' or be 0");
   }
   case Match_InvalidFRMArg: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(
         ErrorLoc,
         "operand must be a valid floating point rounding mode mnemonic");
   }
   case Match_InvalidBareSymbol: {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

if ((FenceArg & RISCVFenceField::I) != 0)
     O << 'i';
   if ((FenceArg & RISCVFenceField::O) != 0)
     O << 'o';
   if ((FenceArg & RISCVFenceField::R) != 0)
     O << 'r';
   if ((FenceArg & RISCVFenceField::W) != 0)
     O << 'w';
   if (FenceArg == 0)
-    O << "unknown";
+    O << '0';
 }
 
 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
                                    const MCSubtargetInfo &STI, raw_ostream &O) {
   auto FRMArg =
       static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
   O << RISCVFPRndMode::roundingModeToString(FRMArg);
 }

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 // Non-canonical forms for jump targets also accepted by the assembler.
 def : InstAlias<"jr $rs, $offset",        (JALR      X0, GPR:$rs, simm12:$offset), 0>;
 def : InstAlias<"jalr $rs, $offset",      (JALR      X1, GPR:$rs, simm12:$offset), 0>;
 def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>;
 
 def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw
 
+def : InstAlias<"pause", (FENCE 0x1, 0x0)>; // 0x1 == w
+
 def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, INSTRET.Encoding, X0)>;
 def : InstAlias<"rdcycle $rd",   (CSRRS GPR:$rd, CYCLE.Encoding, X0)>;
 def : InstAlias<"rdtime $rd",    (CSRRS GPR:$rd, TIME.Encoding, X0)>;
 
 let Predicates = [IsRV32] in {
 def : InstAlias<"rdinstreth $rd", (CSRRS GPR:$rd, INSTRETH.Encoding, X0)>;
 def : InstAlias<"rdcycleh $rd",   (CSRRS GPR:$rd, CYCLEH.Encoding, X0)>;
 def : InstAlias<"rdtimeh $rd",    (CSRRS GPR:$rd, TIMEH.Encoding, X0)>;

llvm/test/MC/RISCV/rv32i-invalid.s

 # RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
 
 # Out of range immediates
 ## fencearg
-fence iorw, iore # CHECK: :[[@LINE]]:13: error: operand must be formed of letters selected in-order from 'iorw'
-fence wr, wr # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
-fence rw, rr # CHECK: :[[@LINE]]:11: error: operand must be formed of letters selected in-order from 'iorw'
-fence 1, rw # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
-fence unknown, unknown # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
+fence iorw, iore # CHECK: :[[@LINE]]:13: error: operand must be formed of letters selected in-order from 'iorw' or be 0
+fence wr, wr # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' or be 0
+fence rw, rr # CHECK: :[[@LINE]]:11: error: operand must be formed of letters selected in-order from 'iorw' or be 0
+fence 1, rw # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' or be 0
+fence unknown, unknown # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' or be 0
 
 ## uimm5
 slli a0, a0, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
 srli a0, a0, -1 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
 srai a0, a0, -19 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
 csrrwi a1, 0x1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
 csrrsi t1, 999, 32 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31]
 csrrci x0, 43, -90 # CHECK: :[[@LINE]]:16: error: immediate must be an integer in the range [0, 31]

llvm/test/MC/RISCV/rv32i-valid.s

 # CHECK-ASM: encoding: [0x0f,0x00,0x30,0x0c]
 fence io, rw
 # CHECK-ASM-AND-OBJ: fence r, w
 # CHECK-ASM: encoding: [0x0f,0x00,0x10,0x02]
 fence r,w
 # CHECK-ASM-AND-OBJ: fence w, ir
 # CHECK-ASM: encoding: [0x0f,0x00,0xa0,0x01]
 fence w,ir
+# CHECK-ASM-AND-OBJ: fence w, 0
+# CHECK-ASM: encoding: [0x0f,0x00,0x00,0x01]
+fence w,0
+# CHECK-ASM-AND-OBJ: fence 0, w
+# CHECK-ASM: encoding: [0x0f,0x00,0x10,0x00]
+fence 0,w
+# CHECK-ASM-AND-OBJ: fence 0, 0
+# CHECK-ASM: encoding: [0x0f,0x00,0x00,0x00]
+fence 0,0
 # CHECK-ASM-AND-OBJ: fence.tso
 # CHECK-ASM: encoding: [0x0f,0x00,0x30,0x83]
 fence.tso
 
 # CHECK-ASM-AND-OBJ: fence.i
 # CHECK-ASM: encoding: [0x0f,0x10,0x00,0x00]
 fence.i
 

llvm/test/MC/RISCV/rvi-aliases-valid.s

 ret
 # TODO call
 # TODO tail
 
 # CHECK-S-OBJ-NOALIAS: fence iorw, iorw
 # CHECK-S-OBJ: fence
 fence
 
+# CHECK-S-OBJ-NOALIAS: fence w, 0
+# CHECK-S-OBJ: pause
+pause
+
 # CHECK-S-OBJ-NOALIAS: csrrs s10, instret, zero
 # CHECK-S-OBJ: rdinstret s10
 rdinstret x26
 # CHECK-S-OBJ-NOALIAS: csrrs s8, cycle, zero
 # CHECK-S-OBJ: rdcycle s8
 rdcycle x24
 # CHECK-S-OBJ-NOALIAS: csrrs s9, time, zero
 # CHECK-S-OBJ: rdtime s9