[RISCV] Only combine (or (GREVI x, shamt), x) -> GORCI if shamt is a power of 2.

[craig.topper]

Summary

GORCI performs an OR between each stage. So we need to ensure only
one stage is active before doing this combine.

Initial attempts at finding a test case for this failed due to
the order things get combined. It's most likely that we'll form
one stage of GREVI then combine to GORCI before the two stages of
GREVI are able to be formed and combined with each other to form
a multi stage GREVI.

[frasercrmck]

Good catch, thanks. LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (LHS && RHS && LHS->formsPairWith(*RHS)) {
           RISCVISD::GREVI, DL, VT, LHS->Op,
           DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT()));
     }
   }
   return SDValue();
 }
 
 // Matches any the following pattern as a GORCI(W) operation
-// 1.  (or (GREVI x, shamt), x)
-// 2.  (or x, (GREVI x, shamt))
+// 1.  (or (GREVI x, shamt), x) if shamt is a power of 2
+// 2.  (or x, (GREVI x, shamt)) if shamt is a power of 2
 // 3.  (or (or (BITMANIP_SHL x), x), (BITMANIP_SRL x))
 // Note that with the variant of 3.,
 //     (or (or (BITMANIP_SHL x), (BITMANIP_SRL x)), x)
 // the inner pattern will first be matched as GREVI and then the outer
 // pattern will be matched to GORC via the first rule above.
 static SDValue combineORToGORC(SDValue Op, SelectionDAG &DAG,
                                const RISCVSubtarget &Subtarget) {
   EVT VT = Op.getValueType();
 
   if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) {
     SDLoc DL(Op);
     SDValue Op0 = Op.getOperand(0);
     SDValue Op1 = Op.getOperand(1);
 
     // Check for either commutable permutation of (or (GREVI x, shamt), x)
     for (const auto &OpPair :
          {std::make_pair(Op0, Op1), std::make_pair(Op1, Op0)}) {
       if (OpPair.first.getOpcode() == RISCVISD::GREVI &&
-          OpPair.first.getOperand(0) == OpPair.second)
+          OpPair.first.getOperand(0) == OpPair.second &&
+          isPowerOf2_32(OpPair.first.getConstantOperandVal(1)))
         return DAG.getNode(RISCVISD::GORCI, DL, VT, OpPair.second,
                            OpPair.first.getOperand(1));
     }
 
     // OR is commutable so canonicalize its OR operand to the left
     if (Op0.getOpcode() != ISD::OR && Op1.getOpcode() == ISD::OR)
       std::swap(Op0, Op1);
     if (Op0.getOpcode() != ISD::OR)