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[RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X).
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Authored by craig.topper on Nov 29 2020, 1:49 PM.

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frasercrmck
asb
lenary
luismarques
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rG5c819eb38935: [RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X).
Summary

A rotate by half the bitwidth swaps the bottom and top half which is the same as one of the MSB GREVI stage.

We have to do this as a special combine because we prefer to keep (rotl/rotr X, BitWidth/2) as a rotate rather than a single stage GREVI.

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Event Timeline

craig.topper created this revision.Nov 29 2020, 1:49 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 29 2020, 1:49 PM
Herald added subscribers: NickHung, evandro, apazos and 23 others. · View Herald Transcript
craig.topper requested review of this revision.Nov 29 2020, 1:49 PM
Herald added a subscriber: MaskRay. · View Herald TranscriptNov 29 2020, 1:49 PM
Harbormaster completed remote builds in B80462: Diff 308229.Nov 29 2020, 2:21 PM
frasercrmck added a comment.Nov 30 2020, 2:13 AM

It might be worth mentioning somewhere (the commit message?) why this isn't done by matching (rotl/rotr X, Bitwidth/2) as GREVI and then matching GORCI through that. Presumably we'd like to match GREVI of rotl/rotr too, for instance?

craig.topper updated this revision to Diff 308388.Nov 30 2020, 8:56 AM
craig.topper edited the summary of this revision. (Show Details)

Rebase

craig.topper added a comment.Dec 5 2020, 2:21 PM

Ping

frasercrmck accepted this revision.Dec 7 2020, 8:49 AM

LGTM

This revision is now accepted and ready to land.Dec 7 2020, 8:49 AM
Closed by commit rG5c819eb38935: [RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X). (authored by craig.topper). · Explain WhyDec 7 2020, 10:31 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG5c819eb38935: [RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X)..

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Changeset List

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llvm/
lib/
Target/
RISCV/
31 lines
test/
CodeGen/
RISCV/
46 lines
92 lines

Diff 309949

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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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llvm/test/CodeGen/RISCV/rv32Zbp.ll

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llvm/test/CodeGen/RISCV/rv64Zbp.ll

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