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Differential D91987

[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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Authored by craig.topper on Nov 23 2020, 11:51 AM.

Details

Reviewers
asb
luismarques
lenary
frasercrmck
evandro
HsiangKai
Commits
rGed95cafbc5fa: [RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
Summary

Start with an assumption that FMA is faster than Fmul+FAdd. If thats not true on some particular implementation we can add a tuning parameter in the future.

I've update the fmuladd test cases and added new test cases for fast math flag based contraction.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 23 2020, 11:51 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 23 2020, 11:51 AM
Herald added subscribers: NickHung, evandro, apazos and 22 others. · View Herald Transcript
craig.topper requested review of this revision.Nov 23 2020, 11:51 AM
Herald added a subscriber: MaskRay. · View Herald TranscriptNov 23 2020, 11:51 AM
craig.topper added reviewers: evandro, HsiangKai.Nov 23 2020, 5:11 PM
evandro accepted this revision.Nov 25 2020, 2:36 PM
This revision is now accepted and ready to land.Nov 25 2020, 2:36 PM
Closed by commit rGed95cafbc5fa: [RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd (authored by craig.topper). · Explain WhyNov 25 2020, 3:22 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGed95cafbc5fa: [RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd.
Herald added a subscriber: jrtc27. · View Herald TranscriptNov 25 2020, 3:22 PM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
3 lines
19 lines
test/
CodeGen/
RISCV/
157 lines
7 lines
117 lines
7 lines

Diff 307721

llvm/lib/Target/RISCV/RISCVISelLowering.h

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Linespublic:
bool shouldInsertFencesForAtomic(const Instruction *I) const override { bool shouldInsertFencesForAtomic(const Instruction *I) const override {
return isa<LoadInst>(I) || isa<StoreInst>(I); return isa<LoadInst>(I) || isa<StoreInst>(I);
} }
Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
AtomicOrdering Ord) const override; AtomicOrdering Ord) const override;
Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
AtomicOrdering Ord) const override; AtomicOrdering Ord) const override;
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
EVT VT) const override;
ISD::NodeType getExtendForAtomicOps() const override { ISD::NodeType getExtendForAtomicOps() const override {
return ISD::SIGN_EXTEND; return ISD::SIGN_EXTEND;
} }
ISD::NodeType getExtendForAtomicCmpSwapArg() const override { ISD::NodeType getExtendForAtomicCmpSwapArg() const override {
return ISD::SIGN_EXTEND; return ISD::SIGN_EXTEND;
} }
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Show First 20 Lines • Show All 3,359 Lines • ▼ Show 20 Lines Function *MaskedCmpXchg =
Intrinsic::getDeclaration(CI->getModule(), CmpXchgIntrID, Tys); Intrinsic::getDeclaration(CI->getModule(), CmpXchgIntrID, Tys);
Value *Result = Builder.CreateCall( Value *Result = Builder.CreateCall(
MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering}); MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});
if (XLen == 64) if (XLen == 64)
Result = Builder.CreateTrunc(Result, Builder.getInt32Ty()); Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
return Result; return Result;
} }
bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
EVT VT) const {
VT = VT.getScalarType();
if (!VT.isSimple())
return false;
switch (VT.getSimpleVT().SimpleTy) {
case MVT::f32:
return Subtarget.hasStdExtF();
case MVT::f64:
return Subtarget.hasStdExtD();
default:
break;
}
return false;
}
Register RISCVTargetLowering::getExceptionPointerRegister( Register RISCVTargetLowering::getExceptionPointerRegister(
const Constant *PersonalityFn) const { const Constant *PersonalityFn) const {
return RISCV::X10; return RISCV::X10;
} }
Register RISCVTargetLowering::getExceptionSelectorRegister( Register RISCVTargetLowering::getExceptionSelectorRegister(
const Constant *PersonalityFn) const { const Constant *PersonalityFn) const {
return RISCV::X11; return RISCV::X11;
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-arith.ll

Show First 20 Lines • Show All 638 Lines • ▼ Show 20 Lines
; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0 ; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%b_ = fadd double 0.0, %b %b_ = fadd double 0.0, %b
%negb = fsub double -0.0, %b_ %negb = fsub double -0.0, %b_
%1 = call double @llvm.fma.f64(double %a, double %negb, double %c) %1 = call double @llvm.fma.f64(double %a, double %negb, double %c)
ret double %1 ret double %1
} }
define double @fmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fmadd_d_contract:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmadd_d_contract:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = fmul contract double %a, %b
%2 = fadd contract double %1, %c
ret double %2
}
define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fmsub_d_contract:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: fcvt.d.w ft3, zero
; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
; RV32IFD-NEXT: fmsub.d ft0, ft1, ft0, ft2
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fmsub_d_contract:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fmv.d.x ft2, a2
; RV64IFD-NEXT: fmv.d.x ft3, zero
; RV64IFD-NEXT: fadd.d ft2, ft2, ft3
; RV64IFD-NEXT: fmsub.d ft0, ft1, ft0, ft2
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%c_ = fadd double 0.0, %c ; avoid negation using xor
%1 = fmul contract double %a, %b
%2 = fsub contract double %1, %c_
ret double %2
}
define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_d_contract:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: fcvt.d.w ft3, zero
; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
; RV32IFD-NEXT: fadd.d ft1, ft1, ft3
; RV32IFD-NEXT: fadd.d ft0, ft0, ft3
; RV32IFD-NEXT: fnmadd.d ft0, ft2, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmadd_d_contract:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmv.d.x ft3, zero
; RV64IFD-NEXT: fadd.d ft2, ft2, ft3
; RV64IFD-NEXT: fadd.d ft1, ft1, ft3
; RV64IFD-NEXT: fadd.d ft0, ft0, ft3
; RV64IFD-NEXT: fnmadd.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%a_ = fadd double 0.0, %a ; avoid negation using xor
%b_ = fadd double 0.0, %b ; avoid negation using xor
%c_ = fadd double 0.0, %c ; avoid negation using xor
%1 = fmul contract double %a_, %b_
%2 = fneg double %1
%3 = fsub contract double %2, %c_
ret double %3
}
define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmsub_d_contract:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: fcvt.d.w ft3, zero
; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
; RV32IFD-NEXT: fadd.d ft1, ft1, ft3
; RV32IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmsub_d_contract:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmv.d.x ft3, zero
; RV64IFD-NEXT: fadd.d ft2, ft2, ft3
; RV64IFD-NEXT: fadd.d ft1, ft1, ft3
; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%a_ = fadd double 0.0, %a ; avoid negation using xor
%b_ = fadd double 0.0, %b ; avoid negation using xor
%1 = fmul contract double %a_, %b_
%2 = fsub contract double %c, %1
ret double %2
}

llvm/test/CodeGen/RISCV/double-intrinsics.ll

Show First 20 Lines • Show All 335 Lines • ▼ Show 20 Lines
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.fma.f64(double %a, double %b, double %c) %1 = call double @llvm.fma.f64(double %a, double %b, double %c)
ret double %1 ret double %1
} }
declare double @llvm.fmuladd.f64(double, double, double) declare double @llvm.fmuladd.f64(double, double, double)
define double @fmuladd_f64(double %a, double %b, double %c) nounwind { define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
; Use of fmadd depends on TargetLowering::isFMAFasterthanFMulAndFAdd
; RV32IFD-LABEL: fmuladd_f64: ; RV32IFD-LABEL: fmuladd_f64:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a4, 8(sp) ; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp) ; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft2, 8(sp) ; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: fmul.d ft1, ft2, ft1 ; RV32IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fmuladd_f64: ; RV64IFD-LABEL: fmuladd_f64:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2 ; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a0 ; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmul.d ft1, ft2, ft1 ; RV64IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c) %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
ret double %1 ret double %1
} }
declare double @llvm.fabs.f64(double) declare double @llvm.fabs.f64(double)
▲ Show 20 Lines • Show All 269 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-arith.ll

Show First 20 Lines • Show All 477 Lines • ▼ Show 20 Lines
; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0 ; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%b_ = fadd float 0.0, %b %b_ = fadd float 0.0, %b
%negb = fsub float -0.0, %b_ %negb = fsub float -0.0, %b_
%1 = call float @llvm.fma.f32(float %a, float %negb, float %c) %1 = call float @llvm.fma.f32(float %a, float %negb, float %c)
ret float %1 ret float %1
} }
define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fmadd_s_contract:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft2, a0
; RV32IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmadd_s_contract:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft2, a0
; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = fmul contract float %a, %b
%2 = fadd contract float %1, %c
ret float %2
}
define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fmsub_s_contract:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fmv.w.x ft2, a2
; RV32IF-NEXT: fmv.w.x ft3, zero
; RV32IF-NEXT: fadd.s ft2, ft2, ft3
; RV32IF-NEXT: fmsub.s ft0, ft1, ft0, ft2
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmsub_s_contract:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fmv.w.x ft2, a2
; RV64IF-NEXT: fmv.w.x ft3, zero
; RV64IF-NEXT: fadd.s ft2, ft2, ft3
; RV64IF-NEXT: fmsub.s ft0, ft1, ft0, ft2
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor
%1 = fmul contract float %a, %b
%2 = fsub contract float %1, %c_
ret float %2
}
define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s_contract:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft2, a0
; RV32IF-NEXT: fmv.w.x ft3, zero
; RV32IF-NEXT: fadd.s ft2, ft2, ft3
; RV32IF-NEXT: fadd.s ft1, ft1, ft3
; RV32IF-NEXT: fadd.s ft0, ft0, ft3
; RV32IF-NEXT: fnmadd.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmadd_s_contract:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft2, a0
; RV64IF-NEXT: fmv.w.x ft3, zero
; RV64IF-NEXT: fadd.s ft2, ft2, ft3
; RV64IF-NEXT: fadd.s ft1, ft1, ft3
; RV64IF-NEXT: fadd.s ft0, ft0, ft3
; RV64IF-NEXT: fnmadd.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%a_ = fadd float 0.0, %a ; avoid negation using xor
%b_ = fadd float 0.0, %b ; avoid negation using xor
%c_ = fadd float 0.0, %c ; avoid negation using xor
%1 = fmul contract float %a_, %b_
%2 = fneg float %1
%3 = fsub contract float %2, %c_
ret float %3
}
define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s_contract:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft2, a0
; RV32IF-NEXT: fmv.w.x ft3, zero
; RV32IF-NEXT: fadd.s ft2, ft2, ft3
; RV32IF-NEXT: fadd.s ft1, ft1, ft3
; RV32IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmsub_s_contract:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft2, a0
; RV64IF-NEXT: fmv.w.x ft3, zero
; RV64IF-NEXT: fadd.s ft2, ft2, ft3
; RV64IF-NEXT: fadd.s ft1, ft1, ft3
; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%a_ = fadd float 0.0, %a ; avoid negation using xor
%b_ = fadd float 0.0, %b ; avoid negation using xor
%1 = fmul contract float %a_, %b_
%2 = fsub contract float %c, %1
ret float %2
}

llvm/test/CodeGen/RISCV/float-intrinsics.ll

Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Lines
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.fma.f32(float %a, float %b, float %c) %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %1 ret float %1
} }
declare float @llvm.fmuladd.f32(float, float, float) declare float @llvm.fmuladd.f32(float, float, float)
define float @fmuladd_f32(float %a, float %b, float %c) nounwind { define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
; Use of fmadd depends on TargetLowering::isFMAFasterthanFMulAndFAdd
; RV32IF-LABEL: fmuladd_f32: ; RV32IF-LABEL: fmuladd_f32:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2 ; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft2, a0 ; RV32IF-NEXT: fmv.w.x ft2, a0
; RV32IF-NEXT: fmul.s ft1, ft2, ft1 ; RV32IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fmuladd_f32: ; RV64IF-LABEL: fmuladd_f32:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2 ; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft2, a0 ; RV64IF-NEXT: fmv.w.x ft2, a0
; RV64IF-NEXT: fmul.s ft1, ft2, ft1 ; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
ret float %1 ret float %1
} }
declare float @llvm.fabs.f32(float) declare float @llvm.fabs.f32(float)
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