[AArch64] Add SubtargetFeatures for v8.7-A options

[pratlucas]

Summary

This adds subtarget features for v8.7-A's limited-tlb-maintenance nXS
instruction qualifiers, for the WFET/WFIT instructions and for the
HCRX_EL2 system register, allowing each to be conditional on their own
SubtargetFeature instead of being conditional on the base "v8.7a" feature.

Based on patches written by Simon Tatham.

[ostannard]

llvm/lib/Target/AArch64/AArch64.td

406

Why is this FeatureHCX, and not FeatureHCRX for consistency with the register name?

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

2928

Why does this need a special case? Would it not be better to add these extensions to ExtensionMap above?

3019

Could we represent these operand variants in the tablegen, to avoid needing to special-case them here. We could make the TLBI tablegen class a multiclass which expands to the regular and nXS variants, with the appropriate feature requirements set.

[simon_tatham]

llvm/lib/Target/AArch64/AArch64.td

406

"HCX" is the name of the field in ID_AA64MMFR_1 that indicates the presence of that register.

[ostannard]

llvm/lib/Target/AArch64/AArch64.td

406

Ok, that's fine then.

[pratlucas]

As suggested, the contents of this revision were squashed into D91772.

llvm/lib/Target/AArch64/AArch64.td

def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
     "true", "Enable Matrix Multiply Int8 Extension">;
 
 def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
     "true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;
 
 def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
     "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
 
+def FeatureXS : SubtargetFeature<"xs", "HasXS",
+    "true", "Enable Armv8.7-A limited-TLB-maintenance instruction">;
+
+def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
+    "true", "Enable Armv8.7-A WFET and WFIT instruction">;
+
+def FeatureHCX : SubtargetFeature<
+    "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
+
 def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
     "true", "Enable fine grained virtualization traps extension">;
 
 def FeatureEnhancedCounterVirtualization :
       SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
       "true", "Enable enhanced counter virtualization extension">;
 
 //===----------------------------------------------------------------------===//

 
 def HasV8_6aOps : SubtargetFeature<
   "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
   [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
    FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
 
 def HasV8_7aOps : SubtargetFeature<
   "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
-  [HasV8_6aOps]>;
+  [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
 
 def HasV8_0rOps : SubtargetFeature<
   "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
   [//v8.1
   FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2,
   //v8.2
   FeaturePerfMon, FeatureRAS, FeaturePsUAO, FeatureSM4,
   FeatureSHA3, FeatureCCPP, FeatureFullFP16, FeaturePAN_RWV,

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def HasBF16          : Predicate<"Subtarget->hasBF16()">,
                        AssemblerPredicate<(all_of FeatureBF16), "bf16">;
 def HasMatMulInt8    : Predicate<"Subtarget->hasMatMulInt8()">,
                        AssemblerPredicate<(all_of FeatureMatMulInt8), "i8mm">;
 def HasMatMulFP32    : Predicate<"Subtarget->hasMatMulFP32()">,
                        AssemblerPredicate<(all_of FeatureMatMulFP32), "f32mm">;
 def HasMatMulFP64    : Predicate<"Subtarget->hasMatMulFP64()">,
                        AssemblerPredicate<(all_of FeatureMatMulFP64), "f64mm">;
+def HasXS            : Predicate<"Subtarget->hasXS()">,
+                       AssemblerPredicate<(all_of FeatureXS), "xs">;
+def HasWFxT          : Predicate<"Subtarget->hasWFxT()">,
+                       AssemblerPredicate<(all_of FeatureWFxT), "wfxt">;
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
 def IsWindows        : Predicate<"Subtarget->isTargetWindows()">;
 def UseExperimentalZeroingPseudos
     : Predicate<"Subtarget->useExperimentalZeroingPseudos()">;
 def UseAlternateSExtLoadCVTF32
     : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
 
def ISB   : CRmSystemI<barrier_op, 0b110, "isb",
                        [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
 
 def TSB   : CRmSystemI<barrier_op, 0b010, "tsb", []> {
   let CRm        = 0b0010;
   let Inst{12}   = 0;
   let Predicates = [HasTRACEV8_4];
 }
 
-let Predicates = [HasV8_7a] in {
 def DSBnXS  : CRmSystemI<barrier_nxs_op, 0b001, "dsb"> {
   let CRm{1-0}   = 0b11;
   let Inst{9-8}  = 0b10;
+  let Predicates = [HasXS];
 }
+
+let Predicates = [HasWFxT] in {
 def WFET : RegInputSystemI<0b0000, 0b000, "wfet">;
 def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">;
 }
 
 }
 
 // ARMv8.2-A Dot Product
 let Predicates = [HasDotProd] in {

llvm/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasBF16 = false;
   bool HasMatMulInt8 = false;
   bool HasMatMulFP32 = false;
   bool HasMatMulFP64 = false;
   bool HasAMVS = false;
   bool HasFineGrainedTraps = false;
   bool HasEnhancedCounterVirtualization = false;
 
+  // Armv8.7-A Extensions
+  bool HasXS = false;
+  bool HasWFxT = false;
+  bool HasHCX = false;
+
   // Arm SVE2 extensions
   bool HasSVE2 = false;
   bool HasSVE2AES = false;
   bool HasSVE2SM4 = false;
   bool HasSVE2SHA3 = false;
   bool HasSVE2BitPerm = false;
 
   // Future architecture extensions.
public:
   bool hasComplxNum() const { return HasComplxNum; }
 
   bool hasNV() const { return HasNV; }
   bool hasMPAM() const { return HasMPAM; }
   bool hasDIT() const { return HasDIT; }
   bool hasTRACEV8_4() const { return HasTRACEV8_4; }
   bool hasAM() const { return HasAM; }
   bool hasAMVS() const { return HasAMVS; }
+  bool hasXS() const { return HasXS; }
+  bool hasWFxT() const { return HasWFxT; }
+  bool hasHCX() const { return HasHCX; }
   bool hasSEL2() const { return HasSEL2; }
   bool hasPMU() const { return HasPMU; }
   bool hasTLB_RMI() const { return HasTLB_RMI; }
   bool hasFMI() const { return HasFMI; }
   bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
 
   bool addrSinkUsingGEPs() const override {
     // Keeping GEPs inbounds is important for exploiting AArch64

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : RWSysReg<"SCTLR_EL1",          0b11, 0b000, 0b0001, 0b0000, 0b000>;
 def : RWSysReg<"SCTLR_EL2",          0b11, 0b100, 0b0001, 0b0000, 0b000>;
 def : RWSysReg<"SCTLR_EL3",          0b11, 0b110, 0b0001, 0b0000, 0b000>;
 def : RWSysReg<"ACTLR_EL1",          0b11, 0b000, 0b0001, 0b0000, 0b001>;
 def : RWSysReg<"ACTLR_EL2",          0b11, 0b100, 0b0001, 0b0000, 0b001>;
 def : RWSysReg<"ACTLR_EL3",          0b11, 0b110, 0b0001, 0b0000, 0b001>;
 def : RWSysReg<"HCR_EL2",            0b11, 0b100, 0b0001, 0b0001, 0b000>;
 def : RWSysReg<"HCRX_EL2",           0b11, 0b100, 0b0001, 0b0010, 0b010> {
-  let Requires = [{ {AArch64::HasV8_7aOps} }];
+  let Requires = [{ {AArch64::FeatureHCX} }];
 }
 def : RWSysReg<"SCR_EL3",            0b11, 0b110, 0b0001, 0b0001, 0b000>;
 def : RWSysReg<"MDCR_EL2",           0b11, 0b100, 0b0001, 0b0001, 0b001>;
 def : RWSysReg<"SDER32_EL3",         0b11, 0b110, 0b0001, 0b0001, 0b001>;
 def : RWSysReg<"CPTR_EL2",           0b11, 0b100, 0b0001, 0b0001, 0b010>;
 def : RWSysReg<"CPTR_EL3",           0b11, 0b110, 0b0001, 0b0001, 0b010>;
 def : RWSysReg<"HSTR_EL2",           0b11, 0b100, 0b0001, 0b0001, 0b011>;
 def : RWSysReg<"HACR_EL2",           0b11, 0b100, 0b0001, 0b0001, 0b111>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
   else if (FBS[AArch64::HasV8_3aOps])
     Str += "ARMv8.3a";
   else if (FBS[AArch64::HasV8_4aOps])
     Str += "ARMv8.4a";
   else if (FBS[AArch64::HasV8_5aOps])
     Str += "ARMv8.5a";
   else if (FBS[AArch64::HasV8_6aOps])
     Str += "ARMv8.6a";
-  else if (FBS[AArch64::HasV8_7aOps])
+  else if (FBS[AArch64::HasV8_7aOps] || FBS[AArch64::FeatureXS])
     Str += "ARMv8.7a";
   else {
     auto ext = std::find_if(std::begin(ExtensionMap),
       std::end(ExtensionMap),
       [&](const Extension& e)
       // Use & in case multiple features are enabled
       { return (FBS & e.Features) != FeatureBitset(); }
     );
if (HasnXSQualifier) {
       Op = Op.drop_back(3);
     }
     const AArch64TLBI::TLBI *TLBIorig = AArch64TLBI::lookupTLBIByName(Op);
     if (!TLBIorig)
       return TokError("invalid operand for TLBI instruction");
     const AArch64TLBI::TLBI TLBI(
         TLBIorig->Name, TLBIorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
         TLBIorig->NeedsReg,
-        TLBIorig->FeaturesRequired);
+        HasnXSQualifier
+            ? TLBIorig->FeaturesRequired | FeatureBitset({AArch64::FeatureXS})
+            : TLBIorig->FeaturesRequired);
     if (!TLBI.haveFeatures(getSTI().getFeatureBits())) {
       std::string Name =
           std::string(TLBI.Name) + (HasnXSQualifier ? "nXS" : "");
       std::string Str("TLBI " + Name + " requires ");
       setRequiredFeatureString(TLBI.getRequiredFeatures(), Str);
       return TokError(Str.c_str());
     }
     createSysAlias(TLBI.Encoding, Operands, S);

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

case 8: case 9: {
       Ins = "at\t";
       Name = std::string(AT->Name);
     }
     break;
     }
   } else if (CnVal == 8 || CnVal == 9) {
     // TLBI aliases
     if (CnVal == 9) {
+      if (!STI.hasFeature(AArch64::FeatureXS))
+        return false;
       Encoding &= ~(1 << 7);
     }
 
     const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
     if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
       return false;
 
     NeedsReg = TLBI->NeedsReg;

llvm/test/MC/AArch64/armv8.7a-general.s

-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s 2>%t | FileCheck %s
-// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-V87-ERR %s < %t
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-NO-V87-ERR %s < %t
-
-  mrs x2, HCRX_EL2
-// CHECK: mrs x2, HCRX_EL2              // encoding: [0x42,0x12,0x3c,0xd5]
-// CHECK-NO-V87-ERR: [[@LINE-2]]:11: error: expected readable system register
-
-  msr HCRX_EL2, x3
-// CHECK: msr HCRX_EL2, x3              // encoding: [0x43,0x12,0x1c,0xd5]
-// CHECK-NO-V87-ERR: [[@LINE-2]]:7: error: expected writable system register
-
-  dsb #16
-  dsb #20
-  dsb #24
-  dsb #28
-  dsb oshnxs
-  dsb nshnxs
-  dsb ishnxs
-  dsb synxs
-// CHECK: dsb oshnxs                      // encoding: [0x3f,0x32,0x03,0xd5]
-// CHECK: dsb nshnxs                      // encoding: [0x3f,0x36,0x03,0xd5]
-// CHECK: dsb ishnxs                      // encoding: [0x3f,0x3a,0x03,0xd5]
-// CHECK: dsb synxs                       // encoding: [0x3f,0x3e,0x03,0xd5]
-// CHECK: dsb oshnxs                      // encoding: [0x3f,0x32,0x03,0xd5]
-// CHECK: dsb nshnxs                      // encoding: [0x3f,0x36,0x03,0xd5]
-// CHECK: dsb ishnxs                      // encoding: [0x3f,0x3a,0x03,0xd5]
-// CHECK: dsb synxs                       // encoding: [0x3f,0x3e,0x03,0xd5]
-// CHECK-NO-V87-ERR: [[@LINE-16]]:3: error: instruction requires: armv8.7a
-// CHECK-NO-V87-ERR: [[@LINE-16]]:3: error: instruction requires: armv8.7a
-// CHECK-NO-V87-ERR: [[@LINE-16]]:3: error: instruction requires: armv8.7a
-// CHECK-NO-V87-ERR: [[@LINE-16]]:3: error: instruction requires: armv8.7a
-// CHECK-NO-V87-ERR: [[@LINE-16]]:3: error: instruction requires: armv8.7a
-// CHECK-NO-V87-ERR: [[@LINE-16]]:3: error: instruction requires: armv8.7a
-// CHECK-NO-V87-ERR: [[@LINE-16]]:3: error: instruction requires: armv8.7a
-// CHECK-NO-V87-ERR: [[@LINE-16]]:3: error: instruction requires: armv8.7a
-
-  dsb #17
-  dsb nshstnxs
-// CHECK-ERR: [[@LINE-2]]:8: error: barrier operand out of range
-// CHECK-ERR: [[@LINE-2]]:7: error: invalid barrier option for DSBnXS instruction
-
-  wfet x17
-// CHECK: wfet x17                      // encoding: [0x11,0x10,0x03,0xd5]
-// CHECK-NO-V87-ERR: [[@LINE-2]]:3: error: instruction requires: armv8.7a

llvm/test/MC/AArch64/armv8.7a-hcx.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+hcx < %s 2>%t | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s 2>%t | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-HCX-ERR %s < %t
+
+  mrs x2, HCRX_EL2
+// CHECK: mrs x2, HCRX_EL2              // encoding: [0x42,0x12,0x3c,0xd5]
+// CHECK-NO-HCX-ERR: [[@LINE-2]]:11: error: expected readable system register
+
+  msr HCRX_EL2, x3
+// CHECK: msr HCRX_EL2, x3              // encoding: [0x43,0x12,0x1c,0xd5]
+// CHECK-NO-HCX-ERR: [[@LINE-2]]:7: error: expected writable system register

llvm/test/MC/AArch64/armv8.7a-wfxt.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+wfxt < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-NO-WFxT-ERR %s < %t
+
+  wfet x17
+// CHECK: wfet x17                      // encoding: [0x11,0x10,0x03,0xd5]
+// CHECK-NO-WFxT-ERR: [[@LINE-2]]:3: error: instruction requires: wfxt
+
+  wfit x3
+// CHECK: wfit x3                       // encoding: [0x23,0x10,0x03,0xd5]
+// CHECK-NO-WFxT-ERR: [[@LINE-2]]:3: error: instruction requires: wfxt

llvm/test/MC/AArch64/armv8.7a-xs.s

+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,+xs < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-XS-ERR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.7a < %s 2>%t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-XS-ERR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-NO-XS-ERR %s < %t
+
+  dsb #16
+  dsb #20
+  dsb #24
+  dsb #28
+  dsb oshnxs
+  dsb nshnxs
+  dsb ishnxs
+  dsb synxs
+// CHECK: dsb oshnxs                   // encoding: [0x3f,0x32,0x03,0xd5]
+// CHECK: dsb nshnxs                   // encoding: [0x3f,0x36,0x03,0xd5]
+// CHECK: dsb ishnxs                   // encoding: [0x3f,0x3a,0x03,0xd5]
+// CHECK: dsb synxs                    // encoding: [0x3f,0x3e,0x03,0xd5]
+// CHECK: dsb oshnxs                   // encoding: [0x3f,0x32,0x03,0xd5]
+// CHECK: dsb nshnxs                   // encoding: [0x3f,0x36,0x03,0xd5]
+// CHECK: dsb ishnxs                   // encoding: [0x3f,0x3a,0x03,0xd5]
+// CHECK: dsb synxs                    // encoding: [0x3f,0x3e,0x03,0xd5]
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+// CHECK-NO-XS-ERR: [[@LINE-16]]:3: error: instruction requires: xs
+
+  dsb #17
+  dsb nshstnxs
+// CHECK-ERR: [[@LINE-2]]:8: error: barrier operand out of range
+// CHECK-ERR: [[@LINE-2]]:7: error: invalid barrier option for DSBnXS instruction
+
+  tlbi vmalle1osnxs
+  tlbi ipas2e1isnxs, x1
+// CHECK: tlbi vmalle1osnxs             // encoding: [0x1f,0x91,0x08,0xd5]
+// CHECK: tlbi ipas2e1isnxs, x1         // encoding: [0x21,0x90,0x0c,0xd5]
+// CHECK-NO-XS-ERR: [[@LINE-4]]:8: error: TLBI VMALLE1OSnXS requires ARMv8.7a
+// CHECK-NO-XS-ERR: [[@LINE-4]]:8: error: TLBI IPAS2E1ISnXS requires ARMv8.7a

llvm/test/MC/Disassembler/AArch64/armv8.7a-general.txt

-# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck --check-prefix=CHECK-NO-V87 %s
-
-[0x42,0x12,0x3c,0xd5]
-# CHECK: mrs x2, HCRX_EL2
-# CHECK-NO-V87: mrs x2, S3_4_C1_C2_2
-
-[0x43,0x12,0x1c,0xd5]
-# CHECK: msr HCRX_EL2, x3
-# CHECK-NO-V87: msr S3_4_C1_C2_2, x3
-
-[0x3f,0x32,0x03,0xd5]
-[0x3f,0x36,0x03,0xd5]
-[0x3f,0x3a,0x03,0xd5]
-[0x3f,0x3e,0x03,0xd5]
-# CHECK: dsb oshnxs
-# CHECK: dsb nshnxs
-# CHECK: dsb ishnxs
-# CHECK: dsb synxs
-# CHECK-NO-V87: msr S0_3_C3_C2_1, xzr
-# CHECK-NO-V87: msr S0_3_C3_C6_1, xzr
-# CHECK-NO-V87: msr S0_3_C3_C10_1, xzr
-# CHECK-NO-V87: msr S0_3_C3_C14_1, xzr
-
-[0x3f,0x30,0x03,0xd5]
-[0x3f,0x35,0x03,0xd5]
-[0x3f,0x3f,0x03,0xd5]
-# CHECK: msr S0_3_C3_C0_1, xzr
-# CHECK: msr S0_3_C3_C5_1, xzr
-# CHECK: msr S0_3_C3_C15_1, xzr
-# CHECK-NO-V87: msr S0_3_C3_C0_1, xzr
-# CHECK-NO-V87: msr S0_3_C3_C5_1, xzr
-# CHECK-NO-V87: msr S0_3_C3_C15_1, xzr
-
-[0x11,0x10,0x03,0xd5]
-# CHECK: wfet x17
-# CHECK-NO-V87: msr S0_3_C1_C0_0, x17

llvm/test/MC/Disassembler/AArch64/armv8.7a-hcx.txt

+# RUN: llvm-mc -triple=aarch64 -mattr=+hcx -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck --check-prefix=CHECK-NO-HCX %s
+
+[0x42,0x12,0x3c,0xd5]
+# CHECK: mrs x2, HCRX_EL2
+# CHECK-NO-HCX: mrs x2, S3_4_C1_C2_2
+
+[0x43,0x12,0x1c,0xd5]
+# CHECK: msr HCRX_EL2, x3
+# CHECK-NO-HCX: msr S3_4_C1_C2_2, x3

llvm/test/MC/Disassembler/AArch64/armv8.7a-wfxt.txt

+# RUN: llvm-mc -triple=aarch64 -mattr=+wfxt -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck --check-prefix=CHECK-NO-WFxT %s
+
+[0x11,0x10,0x03,0xd5]
+# CHECK: wfet x17
+# CHECK-NO-WFxT: msr S0_3_C1_C0_0, x17
+
+[0x23,0x10,0x03,0xd5]
+# CHECK: wfit x3
+# CHECK-NO-WFxT: msr S0_3_C1_C0_1, x3

llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt

+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.4a,+xs -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.7a -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.4a -disassemble %s | FileCheck --check-prefix=CHECK-NO-XS %s
+
+[0x3f,0x32,0x03,0xd5]
+[0x3f,0x36,0x03,0xd5]
+[0x3f,0x3a,0x03,0xd5]
+[0x3f,0x3e,0x03,0xd5]
+# CHECK: dsb oshnxs
+# CHECK: dsb nshnxs
+# CHECK: dsb ishnxs
+# CHECK: dsb synxs
+# CHECK-NO-XS: msr S0_3_C3_C2_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C6_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C10_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C14_1, xzr
+
+[0x3f,0x30,0x03,0xd5]
+[0x3f,0x35,0x03,0xd5]
+[0x3f,0x3f,0x03,0xd5]
+# CHECK: msr S0_3_C3_C0_1, xzr
+# CHECK: msr S0_3_C3_C5_1, xzr
+# CHECK: msr S0_3_C3_C15_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C0_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C5_1, xzr
+# CHECK-NO-XS: msr S0_3_C3_C15_1, xzr
+
+[0x1f,0x91,0x08,0xd5]
+[0x21,0x90,0x0c,0xd5]
+# CHECK: tlbi vmalle1osnxs
+# CHECK: tlbi ipas2e1isnxs, x1
+# CHECK-NO-XS: sys #0, c9, c1, #0
+# CHECK-NO-XS: sys #4, c9, c0, #1, x1