[DAGCombiner] Enhance (zext(setcc))

[lkail]

Summary

Current v:t = zext(setcc x,y,cc) will be transformed to select x, y, 1:t, 0:t, cc. It misses some opportunities if x's type size is less than t's size. This patch enhances the above transformation.

[xbolva00]

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

312–313

Adjust comment?

[spatel]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

10551

Use 'DAG.getBoolConstant' ?

EVT N0VT = N0.getValueType();
EVT N00VT = N0.getOperand(0).getValueType();
if (SDValue SCC = SimplifySelectCC(
        DL, N0.getOperand(0), N0.getOperand(1),
        DAG.getBoolConstant(true, DL, N0VT, N00VT),
        DAG.getBoolConstant(false, DL, N0VT, N00VT),
        cast<CondCodeSDNode>(N0.getOperand(2))->get(), true))
  return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SCC);

10556

I think you can delete the existing transform as a special-case - the ZERO_EXTEND node will not be created if VT == N0VT.

[lkail]

Per @spatel 's comments.

[lkail]

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

312–313

Hmmm, interesting, the function name also indicates it's negative.

[spatel]

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

312–313

Yes, please update comment.
https://alive2.llvm.org/ce/z/AEzNaw
Side note: in IR, -instcombine doesn't get this, but -sccp does.

[spatel]

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

312–313

"negative" in this context means the test was trying to show that the icmp transform that applies to other tests in this file is not applicable to this test.

[lkail]

Adjust comments, leave function name unchanged.

[lkail]

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

312–313

Ok, I see. Looks my latest revision doesn't catch your point. I'll update it.

[lkail]

Updated comments again.

[spatel]

LGTM

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

       EVT MatchingVectorType = N00VT.changeVectorElementTypeToInteger();
       SDValue VsetCC =
           DAG.getNode(ISD::SETCC, DL, MatchingVectorType, N0.getOperand(0),
                       N0.getOperand(1), N0.getOperand(2));
       return DAG.getZeroExtendInReg(DAG.getAnyExtOrTrunc(VsetCC, DL, VT), DL,
                                     N0.getValueType());
     }
 
-    // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
+    // zext(setcc x,y,cc) -> zext(select x, y, true, false, cc)
     SDLoc DL(N);
+    EVT N0VT = N0.getValueType();
+    EVT N00VT = N0.getOperand(0).getValueType();
     if (SDValue SCC = SimplifySelectCC(
-            DL, N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, DL, VT),
-            DAG.getConstant(0, DL, VT),
+            DL, N0.getOperand(0), N0.getOperand(1),
+            DAG.getBoolConstant(true, DL, N0VT, N00VT),
+            DAG.getBoolConstant(false, DL, N0VT, N00VT),
             cast<CondCodeSDNode>(N0.getOperand(2))->get(), true))
-      return SCC;
+      return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SCC);
   }
 
   // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
   if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
       isa<ConstantSDNode>(N0.getOperand(1)) &&
       N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
       N0.hasOneUse()) {
     SDValue ShAmt = N0.getOperand(1);
     if (N0.getOpcode() == ISD::SHL) {
       SDValue InnerZExt = N0.getOperand(0);
       // If the original shl may be shifting out bits, do not perform this
       // transformation.
       unsigned KnownZeroBits = InnerZExt.getValueSizeInBits() -
         InnerZExt.getOperand(0).getValueSizeInBits();
       if (cast<ConstantSDNode>(ShAmt)->getAPIntValue().ugt(KnownZeroBits))
         return SDValue();

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

 ; CHECK-NEXT:    cmp w8, #0 // =0
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %t0 = lshr i32 1, %y
   %t1 = and i32 %t0, 2857740885
   %res = icmp eq i32 %t1, 0
   ret i1 %res
 }
 
-;------------------------------------------------------------------------------;
-; A few negative tests
-;------------------------------------------------------------------------------;
-
-define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
-; CHECK-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
+; CHECK-LABEL: scalar_i8_bitsinmiddle_slt:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #24
-; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
-; CHECK-NEXT:    lsr w8, w8, w1
-; CHECK-NEXT:    tst w8, w0
-; CHECK-NEXT:    cset w0, lt
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %t0 = lshr i8 24, %y
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
   %t0 = shl i32 1, %y
   %t1 = and i32 %t0, 2857740885
   %res = icmp eq i32 %t1, 0
   ret i1 %res
 }
 
-;------------------------------------------------------------------------------;
-; A few negative tests
-;------------------------------------------------------------------------------;
-
-define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
-; CHECK-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
+; CHECK-LABEL: scalar_i8_bitsinmiddle_slt:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #24
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    and w8, w8, w0
-; CHECK-NEXT:    sxtb w8, w8
-; CHECK-NEXT:    cmp w8, #0 // =0
-; CHECK-NEXT:    cset w0, lt
+; CHECK-NEXT:    ubfx w0, w8, #7, #1
 ; CHECK-NEXT:    ret
   %t0 = shl i8 24, %y
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {

llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll

 define i32 @fcmp_olt_f128(fp128 %a, fp128 %b) #0 {
 ; P8-LABEL: fcmp_olt_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __ltkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_olt_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpuqp cr0, v2, v3
 ; P9-NEXT:    li r3, 0
 ; P9-NEXT:    li r4, 1
 ; P9-NEXT:    isellt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_olt_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 define i32 @fcmp_oge_f128(fp128 %a, fp128 %b) #0 {
 ; P8-LABEL: fcmp_oge_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __gekf2
 ; P8-NEXT:    nop
-; P8-NEXT:    not r3, r3
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
+; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_oge_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpuqp cr0, v2, v3
 ; P9-NEXT:    xscmpuqp cr1, v2, v3
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
 ; P9-NEXT:    crnor 4*cr5+gt, lt, 4*cr1+lt
 ; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_oge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    not r3, r3
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
+; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 define i32 @fcmp_ult_f128(fp128 %a, fp128 %b) #0 {
 ; P8-LABEL: fcmp_ult_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __gekf2
 ; P8-NEXT:    nop
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_ult_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpuqp cr0, v2, v3
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, lt, un
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_ult_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 define i32 @fcmp_uge_f128(fp128 %a, fp128 %b) #0 {
 ; P8-LABEL: fcmp_uge_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __ltkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    not r3, r3
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
+; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmp_uge_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpuqp cr0, v2, v3
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    isellt r3, 0, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmp_uge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    not r3, r3
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
+; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 define i32 @fcmps_olt_f128(fp128 %a, fp128 %b) #0 {
 ; P8-LABEL: fcmps_olt_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __ltkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_olt_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpoqp cr0, v2, v3
 ; P9-NEXT:    li r3, 0
 ; P9-NEXT:    li r4, 1
 ; P9-NEXT:    isellt r3, r4, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_olt_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"olt", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 define i32 @fcmps_oge_f128(fp128 %a, fp128 %b) #0 {
 ; P8-LABEL: fcmps_oge_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __gekf2
 ; P8-NEXT:    nop
-; P8-NEXT:    not r3, r3
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
+; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_oge_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpoqp cr0, v2, v3
 ; P9-NEXT:    xscmpoqp cr1, v2, v3
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, un, 4*cr1+un
 ; P9-NEXT:    crnor 4*cr5+gt, lt, 4*cr1+lt
 ; P9-NEXT:    crnand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_oge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    not r3, r3
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
+; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"oge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 define i32 @fcmps_ult_f128(fp128 %a, fp128 %b) #0 {
 ; P8-LABEL: fcmps_ult_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __gekf2
 ; P8-NEXT:    nop
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_ult_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpoqp cr0, v2, v3
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    crnor 4*cr5+lt, lt, un
 ; P9-NEXT:    isel r3, 0, r3, 4*cr5+lt
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_ult_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"ult", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

 define i32 @fcmps_uge_f128(fp128 %a, fp128 %b) #0 {
 ; P8-LABEL: fcmps_uge_f128:
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    std r0, 16(r1)
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __ltkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    not r3, r3
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
+; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fcmps_uge_f128:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xscmpoqp cr0, v2, v3
 ; P9-NEXT:    li r3, 1
 ; P9-NEXT:    isellt r3, 0, r3
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: fcmps_uge_f128:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    std r0, 16(r1)
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    not r3, r3
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
+; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
   %cmp = call i1 @llvm.experimental.constrained.fcmps.f128(fp128 %a, fp128 %b, metadata !"uge", metadata !"fpexcept.strict") #0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }

llvm/test/CodeGen/PowerPC/setcc-logic.ll

; CHECK-NEXT:    blr
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @all_bits_set(i32 %P, i32 %Q)  {
; CHECK-NEXT:    blr
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_set:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
 ; CHECK-NEXT:    blr
   %a = icmp slt i32 %P, 0
   %b = icmp slt i32 %Q, 0
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_bits_set(i32 %P, i32 %Q)  {
; CHECK-NEXT:    blr
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_set:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
 ; CHECK-NEXT:    blr
   %a = icmp slt i32 %P, 0
   %b = icmp slt i32 %Q, 0
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_bits_clear(i32 %P, i32 %Q)  {
; CHECK-NEXT:    blr
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 ; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0

llvm/test/CodeGen/PowerPC/signbit-shift.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
 
 ; If positive...
 
 define i32 @zext_ifpos(i32 %x) {
 ; CHECK-LABEL: zext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_zext_ifpos(i32 %x) {
 ; CHECK-LABEL: add_zext_ifpos:
; CHECK-NEXT:    blr
   %e = zext <4 x i1> %c to <4 x i32>
   %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
   ret <4 x i32> %r
 }
 
 define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 41
-; CHECK-NEXT:    cmpwi 3, -1
-; CHECK-NEXT:    li 3, 42
-; CHECK-NEXT:    iselgt 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
+; CHECK-NEXT:    addi 3, 3, 41
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 42, i32 41
   ret i32 %r
 }
 
 define i32 @sext_ifpos(i32 %x) {
 ; CHECK-LABEL: sext_ifpos:
; CHECK-NEXT:    blr
   %e = sext <4 x i1> %c to <4 x i32>
   %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
 }
 
 define i32 @sel_ifpos_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_fval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 42
-; CHECK-NEXT:    cmpwi 3, -1
-; CHECK-NEXT:    li 3, 41
-; CHECK-NEXT:    iselgt 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
+; CHECK-NEXT:    subfic 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 41, i32 42
   ret i32 %r
 }
 
 ; If negative...
 
 define i32 @zext_ifneg(i32 %x) {
 ; CHECK-LABEL: zext_ifneg:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = zext i1 %c to i32
   ret i32 %r
 }
 
 define i32 @add_zext_ifneg(i32 %x) {
 ; CHECK-LABEL: add_zext_ifneg:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    addi 3, 3, 41
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %e = zext i1 %c to i32
   %r = add i32 %e, 41
   ret i32 %r
 }
 
 define i32 @sel_ifneg_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifneg_tval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 41
-; CHECK-NEXT:    cmpwi 3, 0
-; CHECK-NEXT:    li 3, 42
-; CHECK-NEXT:    isellt 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    addi 3, 3, 41
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 42, i32 41
   ret i32 %r
 }
 
 define i32 @sext_ifneg(i32 %x) {
 ; CHECK-LABEL: sext_ifneg:
; CHECK-NEXT:    blr
   %e = sext i1 %c to i32
   %r = add i32 %e, 42
   ret i32 %r
 }
 
 define i32 @sel_ifneg_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifneg_fval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 42
-; CHECK-NEXT:    cmpwi 3, 0
-; CHECK-NEXT:    li 3, 41
-; CHECK-NEXT:    isellt 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    subfic 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 41, i32 42
   ret i32 %r
 }
 
 define i32 @add_lshr_not(i32 %x) {
 ; CHECK-LABEL: add_lshr_not: