[Power9] Add a specific heuristic to schedule the addi before the load

[NFC][PowerPC] Add a test to verify if the scheduler schedule the addi before…

[NFC][PowerPC] Add test for store combine optimization.

[CodeGenPrepare] Don't split the store if it is volatile

[NFC] Add a static function to do the endian check

[NFC][PowerPC] Custom PowerPC specific machine-scheduler

[NFC] Declare the member data of class PostGenericScheduler as "protected"…

[Power9] Enable the Out-of-Order scheduling model for P9 hw

[PowerPC] Remove the implicit use of the register if it is replaced by Imm

[NFC] Add new test to cover the lhs scheduling issue for P9.

[NFC] fix test case issue that with wrong label check.

[NFC] [PowerPC] add an routine in PPCTargetLowering to determine if a global is…

[PowerPC] Fix the assert of ISD::SIGN_EXTEND_INREG when type is v2i16 and v2i8

[PowerPC] [Clang] Add vector int128 pack/unpack builtins

[PowerPC] [Clang] Add vector int128 pack/unpack builtins

[PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1

[PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8

[PowerPC][NFC] Add a mulld testcase for scheduling check.

[PowerPC] Combine ADD to ADDZE

[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8

[PowerPC] Add a peephole post RA to transform the inst that fed by add

[PowerPC] Don't make it as pre-inc candidate if displacement isn't 4's multiple…

If the arch is P9, we will select the DFLOADf32/DFLOADf64 pseudo instruction…

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