[LLDB][RISCV] Add RISC-V ArchSpec and rv32/rv64 variant detection

[luismarques]

Summary

Adds the RISC-V ArchSpec bits contributed by @simoncook as part of D62732, plus logic to distinguish between riscv32 and riscv64 based on ELF class.

The patch follows the implementation approach previously used for MIPS. It defines RISC-V architecture subtypes and inspects the ELF header, namely the ELF class, to detect the right subtype. At the moment this is slightly silly, as the subtypes coincide with the architecture types (rv32 vs rv64), but given how the existing code was structured this seemed like a straightforward and future-proof solution.

[clayborg]

Patch looks good. Just need to test 32 bit RISC as well with a "lldb/test/Shell/ObjectFile/ELF/riscv32-arch.yaml" to verify 32 bit is working.

lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml

1–11 ↗

(On Diff #286815)

We should test 32 bit as well right? Or do we already have one?

[luismarques]

Add riscv32 test.

[jrtc27]

Not so silly; gdb (well, the names are inherited from bfd) has set architecture riscv:rv32/set architecture riscv:rv64 :)

[luismarques]

In D86292#2237143, @jrtc27 wrote:

Not so silly; gdb (well, the names are inherited from bfd) has set architecture riscv:rv32/set architecture riscv:rv64 :)

Ha! We're in good company then. Thanks for sharing, Jessica.

[luismarques]

Moved some of the ArchSpec/core bits from D62732 to here, per @labath's suggestion.

[labath]

This looks fine.

lldb/test/Shell/ObjectFile/ELF/riscv64-arch.yaml

1 ↗

(On Diff #302190)

Consider using yaml2obj's --docnum functionality to merge these tests into one.

[luismarques]

Merge tests, using --docnum.

lldb/include/lldb/Utility/ArchSpec.h

public:
   };
 
   // ARM specific e_flags
   enum ARMeflags {
     eARM_abi_soft_float = 0x00000200,
     eARM_abi_hard_float = 0x00000400
   };
 
+  enum RISCVSubType {
+    eRISCVSubType_unknown,
+    eRISCVSubType_riscv32,
+    eRISCVSubType_riscv64,
+  };
+
   enum Core {
     eCore_arm_generic,
     eCore_arm_armv4,
     eCore_arm_armv4t,
     eCore_arm_armv5,
     eCore_arm_armv5e,
     eCore_arm_armv5t,
     eCore_arm_armv6,
enum Core {
     eCore_x86_32_i686,
 
     eCore_x86_64_x86_64,
     eCore_x86_64_x86_64h, // Haswell enabled x86_64
     eCore_hexagon_generic,
     eCore_hexagon_hexagonv4,
     eCore_hexagon_hexagonv5,
 
+    eCore_riscv32,
+    eCore_riscv64,
+
     eCore_uknownMach32,
     eCore_uknownMach64,
 
     eCore_arc, // little endian ARC
 
     eCore_avr,
 
     eCore_wasm32,

lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

return (endian == ELFDATA2LSB) ? ArchSpec::eMIPSSubType_mips64r6el
                                    : ArchSpec::eMIPSSubType_mips64r6;
   default:
     break;
   }
 
   return arch_variant;
 }
 
+static uint32_t riscvVariantFromElfFlags(const elf::ELFHeader &header) {
+  uint32_t fileclass = header.e_ident[EI_CLASS];
+  switch (fileclass) {
+  case llvm::ELF::ELFCLASS32:
+    return ArchSpec::eRISCVSubType_riscv32;
+  case llvm::ELF::ELFCLASS64:
+    return ArchSpec::eRISCVSubType_riscv64;
+  default:
+    return ArchSpec::eRISCVSubType_unknown;
+  }
+}
+
 static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
   if (header.e_machine == llvm::ELF::EM_MIPS)
     return mipsVariantFromElfFlags(header);
+  else if (header.e_machine == llvm::ELF::EM_RISCV)
+    return riscvVariantFromElfFlags(header);
 
   return LLDB_INVALID_CPUTYPE;
 }
 
 char ObjectFileELF::ID;
 
 // Arbitrary constant used as UUID prefix for core files.
 const uint32_t ObjectFileELF::g_core_uuid_magic(0xE210C);

lldb/source/Utility/ArchSpec.cpp

static const CoreDefinition g_core_definitions[] = {
      ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
     {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
      ArchSpec::eCore_hexagon_generic, "hexagon"},
     {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
      ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
     {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
      ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
 
+    {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
+     "riscv32"},
+    {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
+     "riscv64"},
+
     {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
      ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
     {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
      ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
 
     {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
 
static const ArchDefinitionEntry g_elf_arch_entries[] = {
     {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
      ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
     {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
      LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
     {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
      0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
     {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
      0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR
+    {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
+     ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
+    {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
+     ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
     eArchTypeELF,
     llvm::array_lengthof(g_elf_arch_entries),
     g_elf_arch_entries,
     "elf",
 };

lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml

+# RUN: yaml2obj --docnum=1 %s > %t32
+# RUN: yaml2obj --docnum=2 %s > %t64
+# RUN: lldb-test object-file %t32 | FileCheck --check-prefix=CHECK-RV32 %s
+# RUN: lldb-test object-file %t64 | FileCheck --check-prefix=CHECK-RV64 %s
+
+# CHECK-RV32: Architecture: riscv32--
+
+--- !ELF
+FileHeader:
+  Class:           ELFCLASS32
+  Data:            ELFDATA2LSB
+  Type:            ET_EXEC
+  Machine:         EM_RISCV
+...
+
+# CHECK-RV64: Architecture: riscv64--
+
+--- !ELF
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_EXEC
+  Machine:         EM_RISCV
+...