This is an archive of the discontinued LLVM Phabricator instance.

Differential D86269

[RFC][Target] Add a new backend target called CSKY
AbandonedPublic

Authored by zixuan-wu on Aug 20 2020, 1:25 AM.

Details

Reviewers
jfb
craig.topper
tstellar
dsanders
efriedma
arsenm
lattner
Summary

C-SKY processor is a 32-bit high-performance and low-power embedded processor designed for embedded system or SoC environment. It adopts independently design of architecture and micro architecture with extensible instruction set, which owns great features, e.g. configurable hardware, re-synthesis, easily integration etc. Additionally, it is excellent in power management. It adopts several strategies to reduce power consumption including statically designed and dynamic power supply management, low voltage supply, entering low power mode and closing internal function modules.

Now, C-SKY CPU instruction system has two versions: C-SKY V1 and C-SKY V2. You must note that the C-SKY V2.0 instruction sets are not freely exchangeable with V1.0. Conversely, available function provided by V2.0 is identical to V1.0 for most of applications. So that we strongly recommend that you should make sure you are aware of the generated result of specified application when you use them simultaneously. The two instruction sets differ in how instructions are encoded.

Basically, we can develop C-SKY V2 as prefer, and the ISA doc and ABI doc can be referred at following links. (The links are not stable, and the address can be changed)

ISA: https://github.com/c-sky/csky-doc/blob/master/CSKY%20Architecture%20user_guide.pdf
ABI: https://github.com/c-sky/csky-doc/blob/master/C-SKY_V2_CPU_Applications_Binary_Interface_Standards_Manual.pdf

This is the first patch to introduce the CSKY target and of course it's experimental now. Here is the RFC proposal mail: http://lists.llvm.org/pipermail/llvm-dev/2020-August/144481.html

Diff Detail

Event Timeline

zixuan-wu created this revision.Aug 20 2020, 1:25 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 20 2020, 1:25 AM
Herald added subscribers: llvm-commits, jfb, dexonsmith and 3 others. · View Herald Transcript
zixuan-wu requested review of this revision.Aug 20 2020, 1:25 AM
Herald added a subscriber: jdoerfert. · View Herald TranscriptAug 20 2020, 1:25 AM
zixuan-wu added reviewers: jfb, craig.topper, tstellar, dsanders.Aug 20 2020, 2:24 AM
Harbormaster completed remote builds in B68990: Diff 286730.Aug 20 2020, 2:30 AM
zixuan-wu edited the summary of this revision. (Show Details)Aug 20 2020, 7:19 PM
zixuan-wu added reviewers: efriedma, arsenm.
Herald added a subscriber: wdng. · View Herald TranscriptAug 20 2020, 7:19 PM
glaubitz added a subscriber: glaubitz.Aug 21 2020, 6:35 AM
arsenm added inline comments.Aug 21 2020, 6:52 AM
llvm/include/llvm/ADT/Triple.h
59 ↗(On Diff #286730)

Usually the triple patch is split into a separate patch

llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
83

Grammatically weird error throughout

llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h
36

I'm trying to remove the dependency on machine function state in the constructor in D80249

llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp
74

Can do just MI->getOpcode()

79

Register

150

Constant if

llvm/lib/Target/CSKY/CSKYSubtarget.cpp
46–48

No reason to use std:: string here

llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
99–117

We should move this logic into the base implementation with a template argument for the subtarget class; I think every target reproduces approximately the same thing

SouraVX added a subscriber: SouraVX.Aug 22 2020, 9:37 AM
nickdesaulniers added a subscriber: nickdesaulniers.Aug 23 2020, 4:38 PM
zixuan-wu added a comment.Aug 24 2020, 8:08 PM

Thank you for your review, arsenm!

llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h
36

D80249 has not been committed yet. I think I can rebase and catch up D80249 if it's committed before I commit this patch. If not, I would keep machine function state as original.

llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
99–117

Yes, it's too much housekeeping work. But it's another orthogonal issue and should be handled together with other targets in other patch.

zixuan-wu mentioned this in D86505: [RFC][Target] Add a new triple called Triple::csky.Aug 24 2020, 8:36 PM
zixuan-wu added a child revision: D86505: [RFC][Target] Add a new triple called Triple::csky.
zixuan-wu marked 5 inline comments as done.Aug 24 2020, 9:15 PM
zixuan-wu added inline comments.
llvm/include/llvm/ADT/Triple.h
59 ↗(On Diff #286730)

split to https://reviews.llvm.org/D86505

zixuan-wu updated this revision to Diff 287553.EditedAug 24 2020, 9:22 PM

Address comments. Split triple work as separate part https://reviews.llvm.org/D86505.

MaskRay added a subscriber: MaskRay.Aug 24 2020, 11:05 PM
zixuan-wu mentioned this in D86610: [ELF] Add a new e_machine value EM_CSKY and add some CSKY relocation types.Aug 26 2020, 4:30 AM
zixuan-wu added a child revision: D86610: [ELF] Add a new e_machine value EM_CSKY and add some CSKY relocation types.
zixuan-wu updated this revision to Diff 287923.EditedAug 26 2020, 4:39 AM

take apart ELF related logics into separate patch, D86610.

zixuan-wu mentioned this in rGb21ddded8f04: [RFC][Target] Add a new triple called Triple::csky.Sep 1 2020, 9:47 PM
zixuan-wu added a comment.Sep 3 2020, 7:23 PM

gentle ping...

zixuan-wu mentioned this in rG69f2c79f2ad2: [ELF] Add a new e_machine value EM_CSKY and add some CSKY relocation types.Sep 6 2020, 8:03 PM
zixuan-wu added a comment.Sep 8 2020, 7:17 PM

gentle ping...

HLJ2009 added a subscriber: HLJ2009.Sep 8 2020, 11:45 PM
craig.topper added inline comments.Sep 13 2020, 12:49 PM
llvm/include/llvm/IR/CMakeLists.txt
18

I believe this list is in alphabetical order. So CSKY should be between BBF and Hexagon

llvm/include/llvm/IR/IntrinsicsCSKY.td
2

Is this line longer than 80 characters? It looks longer than line 8 which I assume is 80 characters.

llvm/lib/Target/CSKY/CSKYAsmPrinter.h
2

Can we shorten this line to avoid wrapping?

I think the -*- C++ -*- part needs to stay together.

llvm/lib/Target/CSKY/CSKYCallingConv.h
2

Avoid wrapping this

llvm/lib/Target/CSKY/CSKYConstantPoolValue.cpp
2

Pad to 80 columns

llvm/lib/Target/CSKY/CSKYConstantPoolValue.h
2

Pad to 80 columns

llvm/lib/Target/CSKY/CSKYFrameLowering.cpp
28

Capitalize variable name

llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp
95

I believe LLVM style would prefer "auto *SDIVREM" over "auto SDIVREM" so it;s clear to the read it is a pointer. This applies to other places in this file.

llvm/lib/Target/CSKY/CSKYISelLowering.cpp
30

Use MCPhysReg instead of uint16_t.

159

Stray semicolon?

242

Is this commented out code needed?

388

Is this code needed?

490

Is this code needed?

llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td
2

80 columns

llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
2

Pad to 80 columns

llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
102

Replace this with

std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;

Same for FSAttr. This change made was to all targets in tree a few weeks ago.

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCExpr.cpp
59

Is this code needed?

zixuan-wu updated this revision to Diff 294236.Sep 25 2020, 12:22 AM

Address comments.

zixuan-wu marked 17 inline comments as done.Sep 25 2020, 12:54 AM

Thank you so much @craig.topper for your detail review comments.

zixuan-wu updated this revision to Diff 294251.Sep 25 2020, 1:53 AM
zixuan-wu added a comment.EditedSep 28 2020, 2:09 AM

Ping... :)

nickdesaulniers added a comment.Sep 28 2020, 11:11 AM

This is a massive code drop; I don't think it will be possible for any one person to review.

llvm/lib/Target/CSKY/CSKY.h
28

Give the parameter a name? Looks like it's used.

llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
85–86

Do you plan to add more cases or can this just be a simple if statement for now?

llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp
284

name param

384

?

545

would a range-for work better here? (similar to what's used on L552)

616

I see MI.getOperand(Op) subexpression repeated. I think we have a range-for over operands that might help here?

zixuan-wu mentioned this in D88466: [CSKY 1/n] Add basic stub or infra of csky backend.Sep 28 2020, 9:52 PM
zixuan-wu added a comment.Sep 28 2020, 10:06 PM

This patch is too big to review. I will imitate the RISCV upstream process like D23560 to split this patch.

First one is https://reviews.llvm.org/D88466

lattner resigned from this revision.Sep 28 2020, 10:32 PM
ZhangKang added a subscriber: ZhangKang.Oct 14 2020, 7:06 PM
Herald added a subscriber: pengfei. · View Herald TranscriptOct 14 2020, 7:06 PM
Cooper-Qu added a subscriber: Cooper-Qu.Oct 15 2020, 7:06 PM
dongAxis1944 added a subscriber: dongAxis1944.Nov 26 2020, 7:40 PM
zixuan-wu mentioned this in D93798: [CSKY 4/n] Add basic CSKYAsmParser and CSKYInstPrinter.Dec 28 2020, 6:28 PM
zixuan-wu added a child revision: D95029: [CSKY 6/n] Add support branch and symbol series instruction.Jan 20 2021, 2:46 AM
zixuan-wu added a child revision: D95030: [CSKY 9/n] Initial codegen support for ALU operations.Jan 20 2021, 2:50 AM
zixuan-wu added a child revision: D94007: [CSKY 5/n] Add support for all CSKY basic integer instructions except for branch series.
zixuan-wu added a child revision: D93798: [CSKY 4/n] Add basic CSKYAsmParser and CSKYInstPrinter.
arsenm requested changes to this revision.Mar 30 2021, 6:12 PM

Can this be abandoned now?

This revision now requires changes to proceed.Mar 30 2021, 6:12 PM
dexonsmith removed a subscriber: dexonsmith.Mar 31 2021, 4:09 PM
zixuan-wu abandoned this revision.Apr 1 2021, 8:08 PM

Large Diff

This large diff affects 129 files. Files without inline comments have been collapsed. Expand All Files

Revision Contents

PathSize
llvm/
4 lines
include/
llvm/
IR/
1 line
1 line
38 lines
lib/
Target/
CSKY/
AsmParser/
3 lines
7 lines
22 lines
32 lines
32 lines
101 lines
58 lines
202 lines
69 lines
25 lines
88 lines
1504 lines
244 lines
376 lines
58 lines
268 lines
194 lines
130 lines
885 lines
507 lines
226 lines
169 lines
92 lines
495 lines
611 lines
295 lines
361 lines
35 lines
124 lines
65 lines
11 lines
60 lines
158 lines
195 lines
102 lines
63 lines
43 lines
155 lines
23 lines
18 lines
Disassembler/
3 lines
11 lines
23 lines
32 lines
MCTargetDesc/
12 lines
40 lines
241 lines
96 lines
63 lines
42 lines
56 lines
27 lines
17 lines
66 lines
165 lines
70 lines
82 lines
44 lines
111 lines
23 lines
11 lines
23 lines
11 lines
23 lines
11 lines
22 lines
20 lines
TargetInfo/
3 lines
20 lines
23 lines
22 lines
Utils/
3 lines
62 lines
18 lines
21 lines
1 line
test/
CodeGen/
CSKY/
120 lines
115 lines
123 lines
3329 lines
5371 lines
4059 lines
3551 lines
120 lines
120 lines
292 lines
4986 lines
292 lines
292 lines
188 lines
105 lines
890 lines
1222 lines
97 lines
438 lines
288 lines
1457 lines
92 lines
511 lines
144 lines
301 lines
2 lines
124 lines
125 lines
30 lines
114 lines
234 lines
132 lines
10181 lines
3125 lines
216 lines
119 lines
930 lines
149 lines
182 lines
322 lines
121 lines
125 lines
198 lines
130 lines
930 lines
145 lines
115 lines
215 lines
utils/
UpdateTestChecks/
19 lines

Diff 294251

llvm/CODE_OWNERS.TXT

llvm/include/llvm/IR/CMakeLists.txt

set(LLVM_TARGET_DEFINITIONS Attributes.td) set(LLVM_TARGET_DEFINITIONS Attributes.td)
tablegen(LLVM Attributes.inc -gen-attrs) tablegen(LLVM Attributes.inc -gen-attrs)
set(LLVM_TARGET_DEFINITIONS Intrinsics.td) set(LLVM_TARGET_DEFINITIONS Intrinsics.td)
tablegen(LLVM IntrinsicImpl.inc -gen-intrinsic-impl) tablegen(LLVM IntrinsicImpl.inc -gen-intrinsic-impl)
tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums) tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums)
tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64) tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64)
tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn) tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn)
tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm) tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm)
tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf) tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf)
tablegen(LLVM IntrinsicsCSKY.h -gen-intrinsic-enums -intrinsic-prefix=csky)
tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon) tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon)
tablegen(LLVM IntrinsicsMips.h -gen-intrinsic-enums -intrinsic-prefix=mips) tablegen(LLVM IntrinsicsMips.h -gen-intrinsic-enums -intrinsic-prefix=mips)
tablegen(LLVM IntrinsicsNVPTX.h -gen-intrinsic-enums -intrinsic-prefix=nvvm) tablegen(LLVM IntrinsicsNVPTX.h -gen-intrinsic-enums -intrinsic-prefix=nvvm)
tablegen(LLVM IntrinsicsPowerPC.h -gen-intrinsic-enums -intrinsic-prefix=ppc) tablegen(LLVM IntrinsicsPowerPC.h -gen-intrinsic-enums -intrinsic-prefix=ppc)
tablegen(LLVM IntrinsicsR600.h -gen-intrinsic-enums -intrinsic-prefix=r600) tablegen(LLVM IntrinsicsR600.h -gen-intrinsic-enums -intrinsic-prefix=r600)
tablegen(LLVM IntrinsicsRISCV.h -gen-intrinsic-enums -intrinsic-prefix=riscv) tablegen(LLVM IntrinsicsRISCV.h -gen-intrinsic-enums -intrinsic-prefix=riscv)
tablegen(LLVM IntrinsicsS390.h -gen-intrinsic-enums -intrinsic-prefix=s390) tablegen(LLVM IntrinsicsS390.h -gen-intrinsic-enums -intrinsic-prefix=s390)
craig.topperUnsubmitted
Done
ReplyInline Actions

I believe this list is in alphabetical order. So CSKY should be between BBF and Hexagon

craig.topper: I believe this list is in alphabetical order. So CSKY should be between BBF and Hexagon
tablegen(LLVM IntrinsicsWebAssembly.h -gen-intrinsic-enums -intrinsic-prefix=wasm) tablegen(LLVM IntrinsicsWebAssembly.h -gen-intrinsic-enums -intrinsic-prefix=wasm)
tablegen(LLVM IntrinsicsX86.h -gen-intrinsic-enums -intrinsic-prefix=x86) tablegen(LLVM IntrinsicsX86.h -gen-intrinsic-enums -intrinsic-prefix=x86)
tablegen(LLVM IntrinsicsXCore.h -gen-intrinsic-enums -intrinsic-prefix=xcore) tablegen(LLVM IntrinsicsXCore.h -gen-intrinsic-enums -intrinsic-prefix=xcore)
add_public_tablegen_target(intrinsics_gen) add_public_tablegen_target(intrinsics_gen)

llvm/include/llvm/IR/Intrinsics.td

llvm/include/llvm/IR/IntrinsicsCSKY.td

  • This file was added.
//===- IntrinsicsCSKY.td - Defines CSKY intrinsics ---------*- tablegen -*-===//
//
craig.topperUnsubmitted
Done
ReplyInline Actions

Is this line longer than 80 characters? It looks longer than line 8 which I assume is 80 characters.

craig.topper: Is this line longer than 80 characters? It looks longer than line 8 which I assume is 80…
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines all of the CSKY-specific intrinsics.
//
//===----------------------------------------------------------------------===//
let TargetPrefix = "csky" in { // All intrinsics start with "llvm.csky.".
/// CSKY_Intrinsic - Base class for the majority of CSKY intrinsics.
class CSKY_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
list<LLVMType> param_types,
list<IntrinsicProperty> properties>
: GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
Intrinsic<ret_types, param_types, properties>;
/// CSKY_NonGCC_Intrinsic - Base class for bitcode convertible CSKY
/// intrinsics.
class CSKY_NonGCC_Intrinsic<list<LLVMType> ret_types,
list<LLVMType> param_types,
list<IntrinsicProperty> properties>
: Intrinsic<ret_types, param_types, properties>;
// Mark locked loads as read/write to prevent any accidental reordering.
def int_csky_ldex_w :
CSKY_NonGCC_Intrinsic<[llvm_i32_ty], [llvm_ptr32_ty],
[IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
def int_csky_stex_w :
CSKY_NonGCC_Intrinsic<[llvm_i32_ty],
[llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
} // end TargetPrefix

llvm/lib/Target/CSKY/AsmParser/CMakeLists.txt

llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

llvm/lib/Target/CSKY/AsmParser/LLVMBuild.txt

llvm/lib/Target/CSKY/CMakeLists.txt

llvm/lib/Target/CSKY/CSKY.h

  • This file was added.
//===-- CSKY.h - Top-level interface for CSKY--------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
// CSKY back-end.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_CSKY_CSKY_H
#define LLVM_LIB_TARGET_CSKY_CSKY_H
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class CSKYTargetMachine;
class FunctionPass;
FunctionPass *createCSKYISelDag(CSKYTargetMachine &TM);
FunctionPass *createCSKYConstantIslandPass();
FunctionPass *createCSKYShrinkInstPass();
FunctionPass *createCSKYConstantIslandPass();
void initializeCSKYConstantIslandsPass(PassRegistry &);
nickdesaulniersUnsubmitted
Not Done
ReplyInline Actions

Give the parameter a name? Looks like it's used.

nickdesaulniers: Give the parameter a name? Looks like it's used.
} // namespace llvm
#endif // LLVM_LIB_TARGET_CSKY_CSKY_H

llvm/lib/Target/CSKY/CSKY.td

llvm/lib/Target/CSKY/CSKYAsmPrinter.h

  • This file was added.
//===-- CSKYAsmPrinter.h - CSKY implementation of AsmPrinter ----*- C++ -*-===//
//
craig.topperUnsubmitted
Done
ReplyInline Actions

Can we shorten this line to avoid wrapping?

I think the -*- C++ -*- part needs to stay together.

craig.topper: Can we shorten this line to avoid wrapping? I think the -*- C++ -*- part needs to stay…
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_CSKY_CSKYASMPRINTER_H
#define LLVM_LIB_TARGET_CSKY_CSKYASMPRINTER_H
#include "CSKYMCInstLower.h"
#include "CSKYMachineFunctionInfo.h"
#include "CSKYSubtarget.h"
#include "llvm/CodeGen/AsmPrinter.h"
namespace llvm {
class LLVM_LIBRARY_VISIBILITY CSKYAsmPrinter : public AsmPrinter {
CSKYMCInstLower MCInstLowering;
/// Subtarget - Keep a pointer to the CSKYSubtarget around so that we can
/// make the right decision when printing asm code for different targets.
const CSKYSubtarget *Subtarget;
/// CFI - Keep a pointer to CSKYTargetMachine for the current
/// MachineFunction.
CSKYMachineFunctionInfo *CFI;
/// MCP - Keep a pointer to constantpool entries of the current
/// MachineFunction.
const MachineConstantPool *MCP;
/// InConstantPool - Maintain state when emitting a sequence of constant
/// pool entries so we can properly mark them as data regions.
bool InConstantPool;
public:
explicit CSKYAsmPrinter(TargetMachine &TM,
std::unique_ptr<MCStreamer> Streamer);
/// tblgen'erated driver function for lowering simple MI->MC
/// pseudo instructions.
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
const MachineInstr *MI);
void emitInstruction(const MachineInstr *MI) override;
void emitFunctionBodyEnd() override;
void emitFunctionEntryLabel() override;
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
void emitConstantPool() override {
// we emit constant pools customly!
}
bool runOnMachineFunction(MachineFunction &MF) override;
};
} // end namespace llvm
#endif // LLVM_LIB_TARGET_CSKY_CSKYASMPRINTER_H

llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp

  • This file was added.
//===-- CSKYAsmPrinter.cpp - CSKY LLVM assembly writer --------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
// of machine-dependent LLVM code to the CSKY assembly language.
//
//===----------------------------------------------------------------------===//
#include "CSKYAsmPrinter.h"
#include "CSKY.h"
#include "CSKYConstantPoolValue.h"
#include "MCTargetDesc/CSKYInstPrinter.h"
#include "MCTargetDesc/CSKYMCExpr.h"
#include "TargetInfo/CSKYTargetInfo.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
CSKYAsmPrinter::CSKYAsmPrinter(llvm::TargetMachine &TM,
std::unique_ptr<llvm::MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
InConstantPool(false) {}
bool CSKYAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
CFI = MF.getInfo<CSKYMachineFunctionInfo>();
MCP = MF.getConstantPool();
Subtarget = &MF.getSubtarget<CSKYSubtarget>();
return AsmPrinter::runOnMachineFunction(MF);
}
// Simple pseudo-instructions have their lowering (with expansion to real
// instructions) auto-generated.
#include "CSKYGenMCPseudoLowering.inc"
void CSKYAsmPrinter::emitInstruction(const MachineInstr *MI) {
// Do any auto-generated pseudo lowerings.
if (emitPseudoExpansionLowering(*OutStreamer, MI))
return;
// Check for manual lowerings.
unsigned Opc = MI->getOpcode();
// If we just ended a constant pool, mark it as such.
if (InConstantPool && Opc != CSKY::CONSTPOOL_ENTRY) {
OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
InConstantPool = false;
}
if (Opc == CSKY::CONSTPOOL_ENTRY) {
// CONSTPOOL_ENTRY - This instruction represents a floating
// constant pool in the function. The first operand is the ID#
// for this instruction, the second is the index into the
// MachineConstantPool that this is, the third is the size in
// bytes of this constant pool entry.
// The required alignment is specified on the basic block holding this MI.
//
unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
// If this is the first entry of the pool, mark it.
if (!InConstantPool) {
OutStreamer->emitDataRegion(MCDR_DataRegion);
InConstantPool = true;
}
OutStreamer->emitLabel(GetCPISymbol(LabelId));
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
if (MCPE.isMachineConstantPoolEntry())
emitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
else
emitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal);
return;
}
switch (Opc) {
case CSKY::LRWJT32: {
nickdesaulniersUnsubmitted
Not Done
ReplyInline Actions

Do you plan to add more cases or can this just be a simple if statement for now?

nickdesaulniers: Do you plan to add more `case`s or can this just be a simple `if` statement for now?
MCInst TmpInst;
TmpInst.setOpcode(CSKY::LRW32);
const MCSymbol *Label = GetCPISymbol(MI->getOperand(2).getIndex());
const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
Register Dest = MI->getOperand(0).getReg();
TmpInst.addOperand(MCOperand::createReg(Dest));
TmpInst.addOperand(MCOperand::createExpr(SymbolExpr));
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
}
MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst);
EmitToStreamer(*OutStreamer, TmpInst);
}
static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
unsigned LabelId, MCContext &Ctx) {
MCSymbol *Label = Ctx.getOrCreateSymbol(
Twine(Prefix) + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
return Label;
}
// Convert a CSKY-specific constant pool modifier into the associated
// MCSymbolRefExpr variant kind.
static CSKYMCExpr::VariantKind
getModifierVariantKind(CSKYCP::CSKYCPModifier Modifier) {
switch (Modifier) {
case CSKYCP::no_modifier:
return CSKYMCExpr::VK_CSKY_None;
case CSKYCP::TLSGD:
return CSKYMCExpr::VK_CSKY_TLSGD;
case CSKYCP::TPOFF:
return CSKYMCExpr::VK_CSKY_TPOFF;
case CSKYCP::GOTTPOFF:
return CSKYMCExpr::VK_CSKY_GOTTPOFF;
case CSKYCP::GOT:
return CSKYMCExpr::VK_CSKY_GOT;
case CSKYCP::GOTOFF:
return CSKYMCExpr::VK_CSKY_GOTOFF;
}
llvm_unreachable("Invalid CSKYCPModifier!");
}
void CSKYAsmPrinter::emitFunctionBodyEnd() {
// Make sure to terminate any constant pools that were at the end
// of the function.
if (!InConstantPool)
return;
InConstantPool = false;
OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
}
void CSKYAsmPrinter::emitFunctionEntryLabel() {
OutStreamer->emitLabel(CurrentFnSym);
}
void CSKYAsmPrinter::emitMachineConstantPoolValue(
MachineConstantPoolValue *MCPV) {
int Size = getDataLayout().getTypeAllocSize(MCPV->getType());
CSKYConstantPoolValue *CCPV = static_cast<CSKYConstantPoolValue *>(MCPV);
MCSymbol *MCSym;
if (CCPV->isLSDA()) {
SmallString<128> Str;
raw_svector_ostream OS(Str);
OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
MCSym = OutContext.getOrCreateSymbol(OS.str());
} else if (CCPV->isBlockAddress()) {
const BlockAddress *BA =
cast<CSKYConstantPoolConstant>(CCPV)->getBlockAddress();
MCSym = GetBlockAddressSymbol(BA);
} else if (CCPV->isGlobalValue()) {
const GlobalValue *GV = cast<CSKYConstantPoolConstant>(CCPV)->getGV();
MCSym = getSymbol(GV);
} else if (CCPV->isMachineBasicBlock()) {
const MachineBasicBlock *MBB = cast<CSKYConstantPoolMBB>(CCPV)->getMBB();
MCSym = MBB->getSymbol();
} else if (CCPV->isJT()) {
signed JTI = cast<CSKYConstantPoolJT>(CCPV)->getJTI();
MCSym = GetJTISymbol(JTI);
} else {
assert(CCPV->isExtSymbol() && "unrecognized constant pool value");
const char *Sym = cast<CSKYConstantPoolSymbol>(CCPV)->getSymbol();
MCSym = GetExternalSymbolSymbol(Sym);
}
// Create an MCSymbol for the reference.
const MCExpr *Expr =
MCSymbolRefExpr::create(MCSym, MCSymbolRefExpr::VK_None, OutContext);
Expr = CSKYMCExpr::create(Expr, getModifierVariantKind(CCPV->getModifier()),
OutContext);
if (CCPV->getPCAdjustment()) {
MCSymbol *PCLabel =
getPICLabel(MAI->getPrivateGlobalPrefix(), getFunctionNumber(),
CCPV->getLabelId(), OutContext);
const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
if (CCPV->mustAddCurrentAddress()) {
// We want "(<expr> - .)", but MC doesn't have a concept of the '.'
// label, so just emit a local label end reference that instead.
MCSymbol *DotSym = OutContext.createTempSymbol();
OutStreamer->emitLabel(DotSym);
const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
}
Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
}
OutStreamer->emitValue(Expr, Size);
}
extern "C" void LLVMInitializeCSKYAsmPrinter() {
RegisterAsmPrinter<CSKYAsmPrinter> X(getTheCSKYTarget());
}

llvm/lib/Target/CSKY/CSKYBasicBlockInfo.h

llvm/lib/Target/CSKY/CSKYCallingConv.h

  • This file was added.
//=== CSKYCallingConv.h - CSKY Custom Calling Convention Routines -*-C++-*-===//
//
craig.topperUnsubmitted
Done
ReplyInline Actions

Avoid wrapping this

craig.topper: Avoid wrapping this
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the custom routines for the CSKY Calling Convention that
// aren't done by tablegen.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_CSKY_CSKYCALLINGCONV_H
#define LLVM_LIB_TARGET_CSKY_CSKYCALLINGCONV_H
#include "CSKY.h"
#include "CSKYSubtarget.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/CallingConv.h"
namespace llvm {} // namespace llvm
#endif

llvm/lib/Target/CSKY/CSKYCallingConv.td

llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp

  • This file was added.
//===- CSKYConstantIslandPass.cpp - Emit PC Relative loads ----------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
//
// Loading constants inline is expensive on CSKY and it's in general better
// to place the constant nearby in code space and then it can be loaded with a
// simple 16/32 bit load instruction like lrw.
//
// The constants can be not just numbers but addresses of functions and labels.
// This can be particularly helpful in static relocation mode for embedded
// non-linux targets.
//
//===----------------------------------------------------------------------===//
#include "CSKY.h"
#include "CSKYMachineFunctionInfo.h"
#include "CSKYSubtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Config/llvm-config.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <vector>
using namespace llvm;
#define DEBUG_TYPE "CSKY-constant-islands"
STATISTIC(NumCPEs, "Number of constpool entries");
STATISTIC(NumSplit, "Number of uncond branches inserted");
STATISTIC(NumCBrFixed, "Number of cond branches fixed");
STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
// FIXME: This option should be removed once it has received sufficient testing.
static cl::opt<bool>
AlignConstantIslands("CSKY-align-constant-islands", cl::Hidden,
cl::init(true),
cl::desc("Align constant islands in code"));
// Rather than do make check tests with huge amounts of code, we force
// the test to use this amount.
static cl::opt<int> ConstantIslandsSmallOffset(
"CSKY-constant-islands-small-offset", cl::init(0),
cl::desc("Make small offsets be this amount for testing purposes"),
cl::Hidden);
// For testing purposes we tell it to not use relaxed load forms so that it
// will split blocks.
static cl::opt<bool> NoLoadRelaxation(
"CSKY-constant-islands-no-load-relaxation", cl::init(false),
cl::desc("Don't relax loads to long loads - for testing purposes"),
cl::Hidden);
static unsigned int longformBranchOpcode(unsigned int Opcode) {
// TODO: Add support for 16bit instr.
return Opcode;
}
// FIXME: need to go through this whole constant islands port and check
// the math for branch ranges and clean this up and make some functions
// to calculate things that are done many times identically.
// Need to refactor some of the code to call this routine.
static unsigned int branchMaxOffsets(unsigned int Opcode) {
unsigned Bits, Scale;
// TODO: Add support for 16bit instr.
Bits = 16;
Scale = 2;
unsigned MaxOffs = ((1 << (Bits - 1)) - 1) * Scale;
return MaxOffs;
}
namespace {
using Iter = MachineBasicBlock::iterator;
using ReverseIter = MachineBasicBlock::reverse_iterator;
/// CSKYConstantIslands - Due to limited PC-relative displacements, CSKY
/// requires constant pool entries to be scattered among the instructions
/// inside a function. To do this, it completely ignores the normal LLVM
/// constant pool; instead, it places constants wherever it feels like with
/// special instructions.
///
/// The terminology used in this pass includes:
/// Islands - Clumps of constants placed in the function.
/// Water - Potential places where an island could be formed.
/// CPE - A constant pool entry that has been placed somewhere, which
/// tracks a list of users.
class CSKYConstantIslands : public MachineFunctionPass {
/// BasicBlockInfo - Information about the offset and size of a single
/// basic block.
struct BasicBlockInfo {
/// Offset - Distance from the beginning of the function to the beginning
/// of this basic block.
///
/// Offsets are computed assuming worst case padding before an aligned
/// block. This means that subtracting basic block offsets always gives a
/// conservative estimate of the real distance which may be smaller.
///
/// Because worst case padding is used, the computed offset of an aligned
/// block may not actually be aligned.
unsigned Offset = 0;
/// Size - Size of the basic block in bytes. If the block contains
/// inline assembly, this is a worst case estimate.
///
/// The size does not include any alignment padding whether from the
/// beginning of the block, or from an aligned jump table at the end.
unsigned Size = 0;
BasicBlockInfo() = default;
unsigned postOffset() const { return Offset + Size; }
};
std::vector<BasicBlockInfo> BBInfo;
/// WaterList - A sorted list of basic blocks where islands could be placed
/// (i.e. blocks that don't fall through to the following block, due
/// to a return, unreachable, or unconditional branch).
std::vector<MachineBasicBlock *> WaterList;
/// NewWaterList - The subset of WaterList that was created since the
/// previous iteration by inserting unconditional branches.
SmallSet<MachineBasicBlock *, 4> NewWaterList;
using water_iterator = std::vector<MachineBasicBlock *>::iterator;
/// CPUser - One user of a constant pool, keeping the machine instruction
/// pointer, the constant pool being referenced, and the max displacement
/// allowed from the instruction to the CP. The HighWaterMark records the
/// highest basic block where a new CPEntry can be placed. To ensure this
/// pass terminates, the CP entries are initially placed at the end of the
/// function and then move monotonically to lower addresses. The
/// exception to this rule is when the current CP entry for a particular
/// CPUser is out of range, but there is another CP entry for the same
/// constant value in range. We want to use the existing in-range CP
/// entry, but if it later moves out of range, the search for new water
/// should resume where it left off. The HighWaterMark is used to record
/// that point.
struct CPUser {
MachineInstr *MI;
MachineInstr *CPEMI;
MachineBasicBlock *HighWaterMark;
private:
unsigned MaxDisp;
unsigned LongFormMaxDisp; // CSKY16 has 16/32 bit instructions
// with different displacements
unsigned LongFormOpcode;
public:
bool NegOk;
CPUser(MachineInstr *Mi, MachineInstr *Cpemi, unsigned Maxdisp, bool Neg,
unsigned Longformmaxdisp, unsigned Longformopcode)
: MI(Mi), CPEMI(Cpemi), MaxDisp(Maxdisp),
LongFormMaxDisp(Longformmaxdisp), LongFormOpcode(Longformopcode),
NegOk(Neg) {
HighWaterMark = CPEMI->getParent();
}
/// getMaxDisp - Returns the maximum displacement supported by MI.
unsigned getMaxDisp() const {
unsigned XMaxDisp =
ConstantIslandsSmallOffset ? ConstantIslandsSmallOffset : MaxDisp;
return XMaxDisp;
}
void setMaxDisp(unsigned Val) { MaxDisp = Val; }
unsigned getLongFormMaxDisp() const { return LongFormMaxDisp; }
unsigned getLongFormOpcode() const { return LongFormOpcode; }
};
/// CPUsers - Keep track of all of the machine instructions that use various
/// constant pools and their max displacement.
std::vector<CPUser> CPUsers;
/// CPEntry - One per constant pool entry, keeping the machine instruction
/// pointer, the constpool index, and the number of CPUser's which
/// reference this entry.
struct CPEntry {
MachineInstr *CPEMI;
unsigned CPI;
unsigned RefCount;
CPEntry(MachineInstr *Cpemi, unsigned Cpi, unsigned Rc = 0)
: CPEMI(Cpemi), CPI(Cpi), RefCount(Rc) {}
};
/// CPEntries - Keep track of all of the constant pool entry machine
/// instructions. For each original constpool index (i.e. those that
/// existed upon entry to this pass), it keeps a vector of entries.
/// Original elements are cloned as we go along; the clones are
/// put in the vector of the original element, but have distinct CPIs.
std::vector<std::vector<CPEntry>> CPEntries;
/// ImmBranch - One per immediate branch, keeping the machine instruction
/// pointer, conditional or unconditional, the max displacement,
/// and (if isCond is true) the corresponding unconditional branch
/// opcode.
struct ImmBranch {
MachineInstr *MI;
unsigned MaxDisp : 31;
bool IsCond : 1;
int UncondBr;
ImmBranch(MachineInstr *Mi, unsigned Maxdisp, bool Cond, int Ubr)
: MI(Mi), MaxDisp(Maxdisp), IsCond(Cond), UncondBr(Ubr) {}
};
/// ImmBranches - Keep track of all the immediate branch instructions.
///
std::vector<ImmBranch> ImmBranches;
/// HasFarJump - True if any far jump instruction has been emitted during
/// the branch fix up pass.
bool HasFarJump;
const CSKYSubtarget *STI = nullptr;
const CSKYInstrInfo *TII;
CSKYMachineFunctionInfo *MFI;
MachineFunction *MF = nullptr;
MachineConstantPool *MCP = nullptr;
public:
static char ID;
CSKYConstantIslands() : MachineFunctionPass(ID) {}
StringRef getPassName() const override { return "CSKY Constant Islands"; }
bool runOnMachineFunction(MachineFunction &F) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineDominatorTree>();
MachineFunctionPass::getAnalysisUsage(AU);
}
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoVRegs);
}
void doInitialPlacement(std::vector<MachineInstr *> &CPEMIs);
CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
Align getCPEAlign(const MachineInstr &CPEMI);
void initializeFunctionInfo(const std::vector<MachineInstr *> &CPEMIs);
unsigned getOffsetOf(MachineInstr *MI) const;
unsigned getUserOffset(CPUser &) const;
nickdesaulniersUnsubmitted
Not Done
ReplyInline Actions

name param

nickdesaulniers: name param
void dumpBBs();
bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset, unsigned Disp,
bool NegativeOK);
bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
const CPUser &U);
void computeBlockSize(MachineBasicBlock *MBB);
MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI);
void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
void adjustBBOffsetsAfter(MachineBasicBlock *BB);
bool decrementCPEReferenceCount(unsigned CPI, MachineInstr *CPEMI);
int findInRangeCPEntry(CPUser &U, unsigned UserOffset);
int findLongFormInRangeCPEntry(CPUser &U, unsigned UserOffset);
bool findAvailableWater(CPUser &U, unsigned UserOffset,
water_iterator &WaterIter);
void createNewWater(unsigned CPUserIndex, unsigned UserOffset,
MachineBasicBlock *&NewMBB);
bool handleConstantPoolUser(unsigned CPUserIndex);
void removeDeadCPEMI(MachineInstr *CPEMI);
bool removeUnusedCPEntries();
bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
MachineInstr *CPEMI, unsigned Disp, bool NegOk,
bool DoDump = false);
bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water, CPUser &U,
unsigned &Growth);
bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
bool fixupImmediateBr(ImmBranch &Br);
bool fixupConditionalBr(ImmBranch &Br);
bool fixupUnconditionalBr(ImmBranch &Br);
};
} // end anonymous namespace
char CSKYConstantIslands::ID = 0;
bool CSKYConstantIslands::isOffsetInRange(unsigned UserOffset,
unsigned TrialOffset,
const CPUser &U) {
return isOffsetInRange(UserOffset, TrialOffset, U.getMaxDisp(), U.NegOk);
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
/// print block size and offset information - debugging
LLVM_DUMP_METHOD void CSKYConstantIslands::dumpBBs() {
for (unsigned J = 0, E = BBInfo.size(); J != E; ++J) {
const BasicBlockInfo &BBI = BBInfo[J];
dbgs() << format("%08x %bb.%u\t", BBI.Offset, J)
<< format(" size=%#x\n", BBInfo[J].Size);
}
}
#endif
bool CSKYConstantIslands::runOnMachineFunction(MachineFunction &Mf) {
MF = &Mf;
MCP = Mf.getConstantPool();
STI = &static_cast<const CSKYSubtarget &>(Mf.getSubtarget());
LLVM_DEBUG(dbgs() << "***** CSKYConstantIslands: "
<< MCP->getConstants().size() << " CP entries, aligned to "
<< MCP->getConstantPoolAlign().value() << " bytes *****\n");
if (!STI->useConstantIslands())
return false;
TII = STI->getInstrInfo();
MFI = MF->getInfo<CSKYMachineFunctionInfo>();
HasFarJump = false;
// This pass invalidates liveness information when it splits basic blocks.
MF->getRegInfo().invalidateLiveness();
// Renumber all of the machine basic blocks in the function, guaranteeing that
// the numbers agree with the position of the block in the function.
MF->RenumberBlocks();
bool MadeChange = false;
// Perform the initial placement of the constant pool entries. To start with,
// we put them all at the end of the function.
std::vector<MachineInstr *> CPEMIs;
if (!MCP->isEmpty())
doInitialPlacement(CPEMIs);
/// The next UID to take is the first unused one.
MFI->initPICLabelUId(CPEMIs.size());
// Do the initial scan of the function, building up information about the
// sizes of each block, the location of all the water, and finding all of the
// constant pool users.
initializeFunctionInfo(CPEMIs);
CPEMIs.clear();
LLVM_DEBUG(dumpBBs());
/// Remove dead constant pool entries.
MadeChange |= removeUnusedCPEntries();
// Iteratively place constant pool entries and fix up branches until there
// is no change.
unsigned NoCPIters = 0, NoBRIters = 0;
(void)NoBRIters;
nickdesaulniersUnsubmitted
Not Done
ReplyInline Actions

?

nickdesaulniers: ?
while (true) {
LLVM_DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n');
bool CPChange = false;
for (unsigned I = 0, E = CPUsers.size(); I != E; ++I)
CPChange |= handleConstantPoolUser(I);
if (CPChange && ++NoCPIters > 30)
report_fatal_error("Constant Island pass failed to converge!");
LLVM_DEBUG(dumpBBs());
// Clear NewWaterList now. If we split a block for branches, it should
// appear as "new water" for the next iteration of constant pool placement.
NewWaterList.clear();
LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
bool BRChange = false;
for (unsigned I = 0, E = ImmBranches.size(); I != E; ++I)
BRChange |= fixupImmediateBr(ImmBranches[I]);
if (BRChange && ++NoBRIters > 30)
report_fatal_error("Branch Fix Up pass failed to converge!");
LLVM_DEBUG(dumpBBs());
if (!CPChange && !BRChange)
break;
MadeChange = true;
}
LLVM_DEBUG(dbgs() << '\n'; dumpBBs());
BBInfo.clear();
WaterList.clear();
CPUsers.clear();
CPEntries.clear();
ImmBranches.clear();
return MadeChange;
}
/// doInitialPlacement - Perform the initial placement of the constant pool
/// entries. To start with, we put them all at the end of the function.
void CSKYConstantIslands::doInitialPlacement(
std::vector<MachineInstr *> &CPEMIs) {
// Create the basic block to hold the CPE's.
MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
MF->push_back(BB);
// MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
const Align MaxAlign = MCP->getConstantPoolAlign();
// Mark the basic block as required by the const-pool.
// If AlignConstantIslands isn't set, use 4-byte alignment for everything.
BB->setAlignment(AlignConstantIslands ? MaxAlign : Align(4));
// The function needs to be as aligned as the basic blocks. The linker may
// move functions around based on their alignment.
MF->ensureAlignment(BB->getAlignment());
// Order the entries in BB by descending alignment. That ensures correct
// alignment of all entries as long as BB is sufficiently aligned. Keep
// track of the insertion point for each alignment. We are going to bucket
// sort the entries as they are created.
SmallVector<MachineBasicBlock::iterator, 8> InsPoint(Log2(MaxAlign) + 1,
BB->end());
// Add all of the constants from the constant pool to the end block, use an
// identity mapping of CPI's to CPE's.
const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants();
const DataLayout &TD = MF->getDataLayout();
for (unsigned I = 0, E = CPs.size(); I != E; ++I) {
unsigned Size = TD.getTypeAllocSize(CPs[I].getType());
assert(Size >= 4 && "Too small constant pool entry");
Align Alignment = CPs[I].getAlign();
// Verify that all constant pool entries are a multiple of their alignment.
// If not, we would have to pad them out so that instructions stay aligned.
assert(isAligned(Alignment, Size) && "CP Entry not multiple of 4 bytes!");
// Insert CONSTPOOL_ENTRY before entries with a smaller alignment.
unsigned LogAlign = Log2(Alignment);
MachineBasicBlock::iterator InsAt = InsPoint[LogAlign];
MachineInstr *CPEMI =
BuildMI(*BB, InsAt, DebugLoc(), TII->get(CSKY::CONSTPOOL_ENTRY))
.addImm(I)
.addConstantPoolIndex(I)
.addImm(Size);
CPEMIs.push_back(CPEMI);
// Ensure that future entries with higher alignment get inserted before
// CPEMI. This is bucket sort with iterators.
for (unsigned A = LogAlign + 1; A <= Log2(MaxAlign); ++A)
if (InsPoint[A] == InsAt)
InsPoint[A] = CPEMI;
// Add a new CPEntry, but no corresponding CPUser yet.
CPEntries.emplace_back(1, CPEntry(CPEMI, I));
++NumCPEs;
LLVM_DEBUG(dbgs() << "Moved CPI#" << I << " to end of function, size = "
<< Size << ", align = " << Alignment.value() << '\n');
}
LLVM_DEBUG(BB->dump());
}
/// BBHasFallthrough - Return true if the specified basic block can fallthrough
/// into the block immediately after it.
static bool bbHasFallthrough(MachineBasicBlock *MBB) {
// Get the next machine basic block in the function.
MachineFunction::iterator MBBI = MBB->getIterator();
// Can't fall off end of function.
if (std::next(MBBI) == MBB->getParent()->end())
return false;
MachineBasicBlock *NextBB = &*std::next(MBBI);
for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
E = MBB->succ_end();
I != E; ++I)
if (*I == NextBB)
return true;
return false;
}
/// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
/// look up the corresponding CPEntry.
CSKYConstantIslands::CPEntry *
CSKYConstantIslands::findConstPoolEntry(unsigned CPI,
const MachineInstr *CPEMI) {
std::vector<CPEntry> &CPEs = CPEntries[CPI];
// Number of entries per constpool index should be small, just do a
// linear search.
for (unsigned I = 0, E = CPEs.size(); I != E; ++I) {
if (CPEs[I].CPEMI == CPEMI)
return &CPEs[I];
}
return nullptr;
}
/// getCPEAlign - Returns the required alignment of the constant pool entry
/// represented by CPEMI. Alignment is measured in log2(bytes) units.
Align CSKYConstantIslands::getCPEAlign(const MachineInstr &CPEMI) {
assert(CPEMI.getOpcode() == CSKY::CONSTPOOL_ENTRY);
// Everything is 4-byte aligned unless AlignConstantIslands is set.
if (!AlignConstantIslands)
return Align(4);
unsigned CPI = CPEMI.getOperand(1).getIndex();
assert(CPI < MCP->getConstants().size() && "Invalid constant pool index.");
return MCP->getConstants()[CPI].getAlign();
}
/// initializeFunctionInfo - Do the initial scan of the function, building up
/// information about the sizes of each block, the location of all the water,
/// and finding all of the constant pool users.
void CSKYConstantIslands::initializeFunctionInfo(
const std::vector<MachineInstr *> &CPEMIs) {
BBInfo.clear();
BBInfo.resize(MF->getNumBlockIDs());
// First thing, compute the size of all basic blocks, and see if the function
// has any inline assembly in it. If so, we have to be conservative about
// alignment assumptions, as we don't know for sure the size of any
// instructions in the inline assembly.
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
nickdesaulniersUnsubmitted
Not Done
ReplyInline Actions

would a range-for work better here? (similar to what's used on L552)

nickdesaulniers: would a range-for work better here? (similar to what's used on L552)
computeBlockSize(&*I);
// Compute block offsets.
adjustBBOffsetsAfter(&MF->front());
// Now go back through the instructions and build up our data structures.
for (MachineBasicBlock &MBB : *MF) {
// If this block doesn't fall through into the next MBB, then this is
// 'water' that a constant pool island could be placed.
if (!bbHasFallthrough(&MBB))
WaterList.push_back(&MBB);
for (MachineInstr &MI : MBB) {
if (MI.isDebugInstr())
continue;
int Opc = MI.getOpcode();
if (MI.isBranch() && !MI.isIndirectBranch()) {
bool IsCond = MI.isConditionalBranch();
unsigned Bits = 0;
unsigned Scale = 1;
int UOpc = Opc;
// TODO: Add support for 16bit instr.
Bits = 16;
Scale = 2;
if (IsCond) {
LLVM_DEBUG(MI.dump());
SmallVector<MachineOperand, 4> Cond;
Cond.push_back(MachineOperand::CreateImm(MI.getOpcode()));
Cond.push_back(MI.getOperand(0));
TII->reverseBranchCondition(Cond);
UOpc = Cond[0].getImm();
}
// Record this immediate branch.
unsigned MaxOffs = ((1 << (Bits - 1)) - 1) * Scale;
ImmBranches.push_back(ImmBranch(&MI, MaxOffs, IsCond, UOpc));
}
if (Opc == CSKY::CONSTPOOL_ENTRY)
continue;
// Scan the instructions for constant pool operands.
for (unsigned Op = 0, E = MI.getNumOperands(); Op != E; ++Op)
if (MI.getOperand(Op).isCPI()) {
// We found one. The addressing mode tells us the max displacement
// from the PC that this instruction permits.
// Basic size info comes from the TSFlags field.
unsigned Bits = 0;
unsigned Scale = 1;
bool NegOk = false;
unsigned LongFormBits = 0;
unsigned LongFormScale = 0;
unsigned LongFormOpcode = 0;
switch (Opc) {
default:
llvm_unreachable("Unknown addressing mode for CP reference!");
case CSKY::LRWJT32:
case CSKY::JSRI32:
case CSKY::LRW32:
Bits = 16;
Scale = 4;
LongFormOpcode = Opc;
LongFormBits = 16;
LongFormScale = 4;
break;
}
// Remember that this is a user of a CP entry.
unsigned CPI = MI.getOperand(Op).getIndex();
nickdesaulniersUnsubmitted
Not Done
ReplyInline Actions

I see MI.getOperand(Op) subexpression repeated. I think we have a range-for over operands that might help here?

nickdesaulniers: I see `MI.getOperand(Op)` subexpression repeated. I think we have a range-for over operands…
MachineInstr *CPEMI = CPEMIs[CPI];
unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
unsigned LongFormMaxOffs = ((1 << LongFormBits) - 1) * LongFormScale;
CPUsers.push_back(CPUser(&MI, CPEMI, MaxOffs, NegOk, LongFormMaxOffs,
LongFormOpcode));
// Increment corresponding CPEntry reference count.
CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
assert(CPE && "Cannot find a corresponding CPEntry!");
CPE->RefCount++;
// Instructions can only use one CP entry, don't bother scanning the
// rest of the operands.
break;
}
}
}
}
/// computeBlockSize - Compute the size and some alignment information for MBB.
/// This function updates BBInfo directly.
void CSKYConstantIslands::computeBlockSize(MachineBasicBlock *MBB) {
BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
BBI.Size = 0;
for (const MachineInstr &MI : *MBB)
BBI.Size += TII->getInstSizeInBytes(MI);
}
/// getOffsetOf - Return the current offset of the specified machine instruction
/// from the start of the function. This offset changes as stuff is moved
/// around inside the function.
unsigned CSKYConstantIslands::getOffsetOf(MachineInstr *MI) const {
MachineBasicBlock *MBB = MI->getParent();
// The offset is composed of two things: the sum of the sizes of all MBB's
// before this instruction's block, and the offset from the start of the block
// it is in.
unsigned Offset = BBInfo[MBB->getNumber()].Offset;
// Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?");
Offset += TII->getInstSizeInBytes(*I);
}
return Offset;
}
/// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
/// ID.
static bool compareMbbNumbers(const MachineBasicBlock *LHS,
const MachineBasicBlock *RHS) {
return LHS->getNumber() < RHS->getNumber();
}
/// updateForInsertedWaterBlock - When a block is newly inserted into the
/// machine function, it upsets all of the block numbers. Renumber the blocks
/// and update the arrays that parallel this numbering.
void CSKYConstantIslands::updateForInsertedWaterBlock(
MachineBasicBlock *NewBB) {
// Renumber the MBB's to keep them consecutive.
NewBB->getParent()->RenumberBlocks(NewBB);
// Insert an entry into BBInfo to align it properly with the (newly
// renumbered) block numbers.
BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
// Next, update WaterList. Specifically, we need to add NewMBB as having
// available water after it.
water_iterator IP = llvm::lower_bound(WaterList, NewBB, compareMbbNumbers);
WaterList.insert(IP, NewBB);
}
unsigned CSKYConstantIslands::getUserOffset(CPUser &U) const {
return getOffsetOf(U.MI);
}
/// Split the basic block containing MI into two blocks, which are joined by
/// an unconditional branch. Update data structures and renumber blocks to
/// account for this change and returns the newly created block.
MachineBasicBlock *
CSKYConstantIslands::splitBlockBeforeInstr(MachineInstr &MI) {
MachineBasicBlock *OrigBB = MI.getParent();
// Create a new MBB for the code after the OrigBB.
MachineBasicBlock *NewBB =
MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
MachineFunction::iterator MBBI = ++OrigBB->getIterator();
MF->insert(MBBI, NewBB);
// Splice the instructions starting with MI over to NewBB.
NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
// Add an unconditional branch from OrigBB to NewBB.
// Note the new unconditional branch is not being recorded.
// There doesn't seem to be meaningful DebugInfo available; this doesn't
// correspond to anything in the source.
// TODO: Add support for 16bit instr.
BuildMI(OrigBB, DebugLoc(), TII->get(CSKY::BR32)).addMBB(NewBB);
++NumSplit;
// Update the CFG. All succs of OrigBB are now succs of NewBB.
NewBB->transferSuccessors(OrigBB);
// OrigBB branches to NewBB.
OrigBB->addSuccessor(NewBB);
// Update internal data structures to account for the newly inserted MBB.
// This is almost the same as updateForInsertedWaterBlock, except that
// the Water goes after OrigBB, not NewBB.
MF->RenumberBlocks(NewBB);
// Insert an entry into BBInfo to align it properly with the (newly
// renumbered) block numbers.
BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
// Next, update WaterList. Specifically, we need to add OrigMBB as having
// available water after it (but not if it's already there, which happens
// when splitting before a conditional branch that is followed by an
// unconditional branch - in that case we want to insert NewBB).
water_iterator IP = llvm::lower_bound(WaterList, OrigBB, compareMbbNumbers);
MachineBasicBlock *WaterBB = *IP;
if (WaterBB == OrigBB)
WaterList.insert(std::next(IP), NewBB);
else
WaterList.insert(IP, OrigBB);
NewWaterList.insert(OrigBB);
// Figure out how large the OrigBB is. As the first half of the original
// block, it cannot contain a tablejump. The size includes
// the new jump we added. (It should be possible to do this without
// recounting everything, but it's very confusing, and this is rarely
// executed.)
computeBlockSize(OrigBB);
// Figure out how large the NewMBB is. As the second half of the original
// block, it may contain a tablejump.
computeBlockSize(NewBB);
// All BBOffsets following these blocks must be modified.
adjustBBOffsetsAfter(OrigBB);
return NewBB;
}
/// isOffsetInRange - Checks whether UserOffset (the location of a constant pool
/// reference) is within MaxDisp of TrialOffset (a proposed location of a
/// constant pool entry).
bool CSKYConstantIslands::isOffsetInRange(unsigned UserOffset,
unsigned TrialOffset,
unsigned MaxDisp, bool NegativeOK) {
if (UserOffset <= TrialOffset) {
// User before the Trial.
if (TrialOffset - UserOffset <= MaxDisp)
return true;
} else if (NegativeOK) {
if (UserOffset - TrialOffset <= MaxDisp)
return true;
}
return false;
}
/// isWaterInRange - Returns true if a CPE placed after the specified
/// Water (a basic block) will be in range for the specific MI.
///
/// Compute how much the function will grow by inserting a CPE after Water.
bool CSKYConstantIslands::isWaterInRange(unsigned UserOffset,
MachineBasicBlock *Water, CPUser &U,
unsigned &Growth) {
unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset();
unsigned NextBlockOffset;
Align NextBlockAlignment;
MachineFunction::const_iterator NextBlock = ++Water->getIterator();
if (NextBlock == MF->end()) {
NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
NextBlockAlignment = Align(1);
} else {
NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
NextBlockAlignment = NextBlock->getAlignment();
}
unsigned Size = U.CPEMI->getOperand(2).getImm();
unsigned CPEEnd = CPEOffset + Size;
// The CPE may be able to hide in the alignment padding before the next
// block. It may also cause more padding to be required if it is more aligned
// that the next block.
if (CPEEnd > NextBlockOffset) {
Growth = CPEEnd - NextBlockOffset;
// Compute the padding that would go at the end of the CPE to align the next
// block.
Growth += offsetToAlignment(CPEEnd, NextBlockAlignment);
// If the CPE is to be inserted before the instruction, that will raise
// the offset of the instruction. Also account for unknown alignment padding
// in blocks between CPE and the user.
if (CPEOffset < UserOffset)
UserOffset += Growth;
} else
// CPE fits in existing padding.
Growth = 0;
return isOffsetInRange(UserOffset, CPEOffset, U);
}
/// isCPEntryInRange - Returns true if the distance between specific MI and
/// specific ConstPool entry instruction can fit in MI's displacement field.
bool CSKYConstantIslands::isCPEntryInRange(MachineInstr *MI,
unsigned UserOffset,
MachineInstr *CPEMI,
unsigned MaxDisp, bool NegOk,
bool DoDump) {
unsigned CPEOffset = getOffsetOf(CPEMI);
if (DoDump) {
LLVM_DEBUG({
unsigned Block = MI->getParent()->getNumber();
const BasicBlockInfo &BBI = BBInfo[Block];
dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
<< " max delta=" << MaxDisp
<< format(" insn address=%#x", UserOffset) << " in "
<< printMBBReference(*MI->getParent()) << ": "
<< format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
<< format("CPE address=%#x offset=%+d: ", CPEOffset,
int(CPEOffset - UserOffset));
});
}
return isOffsetInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
}
#ifndef NDEBUG
/// BBIsJumpedOver - Return true of the specified basic block's only predecessor
/// unconditionally branches to its only successor.
static bool bbIsJumpedOver(MachineBasicBlock *MBB) {
if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
return false;
MachineBasicBlock *Succ = *MBB->succ_begin();
MachineBasicBlock *Pred = *MBB->pred_begin();
MachineInstr *PredMI = &Pred->back();
if (PredMI->getOpcode() == CSKY::BR32 /*TODO: change to 16bit instr. */)
return PredMI->getOperand(0).getMBB() == Succ;
return false;
}
#endif
void CSKYConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
unsigned BBNum = BB->getNumber();
for (unsigned I = BBNum + 1, E = MF->getNumBlockIDs(); I < E; ++I) {
// Get the offset and known bits at the end of the layout predecessor.
// Include the alignment of the current block.
unsigned Offset = BBInfo[I - 1].Offset + BBInfo[I - 1].Size;
BBInfo[I].Offset = Offset;
}
}
/// decrementCPEReferenceCount - find the constant pool entry with index CPI
/// and instruction CPEMI, and decrement its refcount. If the refcount
/// becomes 0 remove the entry and instruction. Returns true if we removed
/// the entry, false if we didn't.
bool CSKYConstantIslands::decrementCPEReferenceCount(unsigned CPI,
MachineInstr *CPEMI) {
// Find the old entry. Eliminate it if it is no longer used.
CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
assert(CPE && "Unexpected!");
if (--CPE->RefCount == 0) {
removeDeadCPEMI(CPEMI);
CPE->CPEMI = nullptr;
--NumCPEs;
return true;
}
return false;
}
/// LookForCPEntryInRange - see if the currently referenced CPE is in range;
/// if not, see if an in-range clone of the CPE is in range, and if so,
/// change the data structures so the user references the clone. Returns:
/// 0 = no existing entry found
/// 1 = entry found, and there were no code insertions or deletions
/// 2 = entry found, and there were code insertions or deletions
int CSKYConstantIslands::findInRangeCPEntry(CPUser &U, unsigned UserOffset) {
MachineInstr *UserMI = U.MI;
MachineInstr *CPEMI = U.CPEMI;
// Check to see if the CPE is already in-range.
if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getMaxDisp(), U.NegOk,
true)) {
LLVM_DEBUG(dbgs() << "In range\n");
return 1;
}
// No. Look for previously created clones of the CPE that are in range.
unsigned CPI = CPEMI->getOperand(1).getIndex();
std::vector<CPEntry> &CPEs = CPEntries[CPI];
for (unsigned I = 0, E = CPEs.size(); I != E; ++I) {
// We already tried this one
if (CPEs[I].CPEMI == CPEMI)
continue;
// Removing CPEs can leave empty entries, skip
if (CPEs[I].CPEMI == nullptr)
continue;
if (isCPEntryInRange(UserMI, UserOffset, CPEs[I].CPEMI, U.getMaxDisp(),
U.NegOk)) {
LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
<< CPEs[I].CPI << "\n");
// Point the CPUser node to the replacement
U.CPEMI = CPEs[I].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
for (unsigned J = 0, E = UserMI->getNumOperands(); J != E; ++J)
if (UserMI->getOperand(J).isCPI()) {
UserMI->getOperand(J).setIndex(CPEs[I].CPI);
break;
}
// Adjust the refcount of the clone...
CPEs[I].RefCount++;
// ...and the original. If we didn't remove the old entry, none of the
// addresses changed, so we don't need another pass.
return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
}
}
return 0;
}
/// LookForCPEntryInRange - see if the currently referenced CPE is in range;
/// This version checks if the longer form of the instruction can be used to
/// to satisfy things.
/// if not, see if an in-range clone of the CPE is in range, and if so,
/// change the data structures so the user references the clone. Returns:
/// 0 = no existing entry found
/// 1 = entry found, and there were no code insertions or deletions
/// 2 = entry found, and there were code insertions or deletions
int CSKYConstantIslands::findLongFormInRangeCPEntry(CPUser &U,
unsigned UserOffset) {
MachineInstr *UserMI = U.MI;
MachineInstr *CPEMI = U.CPEMI;
// Check to see if the CPE is already in-range.
if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getLongFormMaxDisp(),
U.NegOk, true)) {
LLVM_DEBUG(dbgs() << "In range\n");
UserMI->setDesc(TII->get(U.getLongFormOpcode()));
U.setMaxDisp(U.getLongFormMaxDisp());
return 2; // instruction is longer length now
}
// No. Look for previously created clones of the CPE that are in range.
unsigned CPI = CPEMI->getOperand(1).getIndex();
std::vector<CPEntry> &CPEs = CPEntries[CPI];
for (unsigned I = 0, E = CPEs.size(); I != E; ++I) {
// We already tried this one
if (CPEs[I].CPEMI == CPEMI)
continue;
// Removing CPEs can leave empty entries, skip
if (CPEs[I].CPEMI == nullptr)
continue;
if (isCPEntryInRange(UserMI, UserOffset, CPEs[I].CPEMI,
U.getLongFormMaxDisp(), U.NegOk)) {
LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
<< CPEs[I].CPI << "\n");
// Point the CPUser node to the replacement
U.CPEMI = CPEs[I].CPEMI;
// Change the CPI in the instruction operand to refer to the clone.
for (unsigned J = 0, E = UserMI->getNumOperands(); J != E; ++J)
if (UserMI->getOperand(J).isCPI()) {
UserMI->getOperand(J).setIndex(CPEs[I].CPI);
break;
}
// Adjust the refcount of the clone...
CPEs[I].RefCount++;
// ...and the original. If we didn't remove the old entry, none of the
// addresses changed, so we don't need another pass.
return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
}
}
return 0;
}
/// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
/// the specific unconditional branch instruction.
static inline unsigned getUnconditionalBrDisp(int Opc) {
switch (Opc) {
;
// TODO: Add support for 16bit instr.
case CSKY::BR32:
return ((1 << 16) - 1) * 2;
default:
break;
}
return ((1 << 16) - 1) * 2;
}
/// findAvailableWater - Look for an existing entry in the WaterList in which
/// we can place the CPE referenced from U so it's within range of U's MI.
/// Returns true if found, false if not. If it returns true, WaterIter
/// is set to the WaterList entry.
/// To ensure that this pass
/// terminates, the CPE location for a particular CPUser is only allowed to
/// move to a lower address, so search backward from the end of the list and
/// prefer the first water that is in range.
bool CSKYConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
water_iterator &WaterIter) {
if (WaterList.empty())
return false;
unsigned BestGrowth = ~0u;
for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();;
--IP) {
MachineBasicBlock *WaterBB = *IP;
// Check if water is in range and is either at a lower address than the
// current "high water mark" or a new water block that was created since
// the previous iteration by inserting an unconditional branch. In the
// latter case, we want to allow resetting the high water mark back to
// this new water since we haven't seen it before. Inserting branches
// should be relatively uncommon and when it does happen, we want to be
// sure to take advantage of it for all the CPEs near that block, so that
// we don't insert more branches than necessary.
unsigned Growth;
if (isWaterInRange(UserOffset, WaterBB, U, Growth) &&
(WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
NewWaterList.count(WaterBB)) &&
Growth < BestGrowth) {
// This is the least amount of required padding seen so far.
BestGrowth = Growth;
WaterIter = IP;
LLVM_DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB)
<< " Growth=" << Growth << '\n');
// Keep looking unless it is perfect.
if (BestGrowth == 0)
return true;
}
if (IP == B)
break;
}
return BestGrowth != ~0u;
}
/// createNewWater - No existing WaterList entry will work for
/// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
/// block is used if in range, and the conditional branch munged so control
/// flow is correct. Otherwise the block is split to create a hole with an
/// unconditional branch around it. In either case NewMBB is set to a
/// block following which the new island can be inserted (the WaterList
/// is not adjusted).
void CSKYConstantIslands::createNewWater(unsigned CPUserIndex,
unsigned UserOffset,
MachineBasicBlock *&NewMBB) {
CPUser &U = CPUsers[CPUserIndex];
MachineInstr *UserMI = U.MI;
MachineInstr *CPEMI = U.CPEMI;
MachineBasicBlock *UserMBB = UserMI->getParent();
const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()];
// If the block does not end in an unconditional branch already, and if the
// end of the block is within range, make new water there.
if (bbHasFallthrough(UserMBB)) {
// Size of branch to insert.
unsigned Delta = 2;
// Compute the offset where the CPE will begin.
unsigned CPEOffset = UserBBI.postOffset() + Delta;
if (isOffsetInRange(UserOffset, CPEOffset, U)) {
LLVM_DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB)
<< format(", expected CPE offset %#x\n", CPEOffset));
NewMBB = &*++UserMBB->getIterator();
// Add an unconditional branch from UserMBB to fallthrough block. Record
// it for branch lengthening; this new branch will not get out of range,
// but if the preceding conditional branch is out of range, the targets
// will be exchanged, and the altered branch may be out of range, so the
// machinery has to know about it.
// TODO: Add support for 16bit instr.
int UncondBr = CSKY::BR32;
auto *NewMI = BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr))
.addMBB(NewMBB)
.getInstr();
unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
ImmBranches.push_back(
ImmBranch(&UserMBB->back(), MaxDisp, false, UncondBr));
BBInfo[UserMBB->getNumber()].Size += TII->getInstSizeInBytes(*NewMI);
adjustBBOffsetsAfter(UserMBB);
return;
}
}
// What a big block. Find a place within the block to split it.
// Try to split the block so it's fully aligned. Compute the latest split
// point where we can add a 4-byte branch instruction, and then align to
// Align which is the largest possible alignment in the function.
const Align Align = MF->getAlignment();
unsigned BaseInsertOffset = UserOffset + U.getMaxDisp();
LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",
BaseInsertOffset));
// The 4 in the following is for the unconditional branch we'll be inserting
// Alignment of the island is handled
// inside isOffsetInRange.
BaseInsertOffset -= 4;
LLVM_DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset)
<< " la=" << Log2(Align) << '\n');
// This could point off the end of the block if we've already got constant
// pool entries following this block; only the last one is in the water list.
// Back past any possible branches (allow for a conditional and a maximally
// long unconditional).
if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
BaseInsertOffset = UserBBI.postOffset() - 8;
LLVM_DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
}
unsigned EndInsertOffset =
BaseInsertOffset + 4 + CPEMI->getOperand(2).getImm();
MachineBasicBlock::iterator MI = UserMI;
++MI;
unsigned CPUIndex = CPUserIndex + 1;
unsigned NumCPUsers = CPUsers.size();
// MachineInstr *LastIT = 0;
for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
Offset < BaseInsertOffset;
Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) {
assert(MI != UserMBB->end() && "Fell off end of block");
if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) {
CPUser &U = CPUsers[CPUIndex];
if (!isOffsetInRange(Offset, EndInsertOffset, U)) {
// Shift intertion point by one unit of alignment so it is within reach.
BaseInsertOffset -= Align.value();
EndInsertOffset -= Align.value();
}
// This is overly conservative, as we don't account for CPEMIs being
// reused within the block, but it doesn't matter much. Also assume CPEs
// are added in order with alignment padding. We may eventually be able
// to pack the aligned CPEs better.
EndInsertOffset += U.CPEMI->getOperand(2).getImm();
CPUIndex++;
}
}
NewMBB = splitBlockBeforeInstr(*--MI);
}
/// handleConstantPoolUser - Analyze the specified user, checking to see if it
/// is out-of-range. If so, pick up the constant pool value and move it some
/// place in-range. Return true if we changed any addresses (thus must run
/// another pass of branch lengthening), false otherwise.
bool CSKYConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) {
CPUser &U = CPUsers[CPUserIndex];
MachineInstr *UserMI = U.MI;
MachineInstr *CPEMI = U.CPEMI;
unsigned CPI = CPEMI->getOperand(1).getIndex();
unsigned Size = CPEMI->getOperand(2).getImm();
// Compute this only once, it's expensive.
unsigned UserOffset = getUserOffset(U);
// See if the current entry is within range, or there is a clone of it
// in range.
int result = findInRangeCPEntry(U, UserOffset);
if (result == 1)
return false;
if (result == 2)
return true;
// Look for water where we can place this CPE.
MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock();
MachineBasicBlock *NewMBB;
water_iterator IP;
if (findAvailableWater(U, UserOffset, IP)) {
LLVM_DEBUG(dbgs() << "Found water in range\n");
MachineBasicBlock *WaterBB = *IP;
// If the original WaterList entry was "new water" on this iteration,
// propagate that to the new island. This is just keeping NewWaterList
// updated to match the WaterList, which will be updated below.
if (NewWaterList.erase(WaterBB))
NewWaterList.insert(NewIsland);
// The new CPE goes before the following block (NewMBB).
NewMBB = &*++WaterBB->getIterator();
} else {
// No water found.
// we first see if a longer form of the instrucion could have reached
// the constant. in that case we won't bother to split
if (!NoLoadRelaxation) {
result = findLongFormInRangeCPEntry(U, UserOffset);
if (result != 0)
return true;
}
LLVM_DEBUG(dbgs() << "No water found\n");
createNewWater(CPUserIndex, UserOffset, NewMBB);
// splitBlockBeforeInstr adds to WaterList, which is important when it is
// called while handling branches so that the water will be seen on the
// next iteration for constant pools, but in this context, we don't want
// it. Check for this so it will be removed from the WaterList.
// Also remove any entry from NewWaterList.
MachineBasicBlock *WaterBB = &*--NewMBB->getIterator();
IP = llvm::find(WaterList, WaterBB);
if (IP != WaterList.end())
NewWaterList.erase(WaterBB);
// We are adding new water. Update NewWaterList.
NewWaterList.insert(NewIsland);
}
// Remove the original WaterList entry; we want subsequent insertions in
// this vicinity to go after the one we're about to insert. This
// considerably reduces the number of times we have to move the same CPE
// more than once and is also important to ensure the algorithm terminates.
if (IP != WaterList.end())
WaterList.erase(IP);
// Okay, we know we can put an island before NewMBB now, do it!
MF->insert(NewMBB->getIterator(), NewIsland);
// Update internal data structures to account for the newly inserted MBB.
updateForInsertedWaterBlock(NewIsland);
// Decrement the old entry, and remove it if refcount becomes 0.
decrementCPEReferenceCount(CPI, CPEMI);
// No existing clone of this CPE is within range.
// We will be generating a new clone. Get a UID for it.
unsigned ID = MFI->createPICLabelUId();
// Now that we have an island to add the CPE to, clone the original CPE and
// add it to the island.
U.HighWaterMark = NewIsland;
U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(CSKY::CONSTPOOL_ENTRY))
.addImm(ID)
.addConstantPoolIndex(CPI)
.addImm(Size);
CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
++NumCPEs;
// Mark the basic block as aligned as required by the const-pool entry.
NewIsland->setAlignment(getCPEAlign(*U.CPEMI));
// Increase the size of the island block to account for the new entry.
BBInfo[NewIsland->getNumber()].Size += Size;
adjustBBOffsetsAfter(&*--NewIsland->getIterator());
// Finally, change the CPI in the instruction operand to be ID.
for (unsigned I = 0, E = UserMI->getNumOperands(); I != E; ++I)
if (UserMI->getOperand(I).isCPI()) {
UserMI->getOperand(I).setIndex(ID);
break;
}
LLVM_DEBUG(
dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI
<< format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset));
return true;
}
/// removeDeadCPEMI - Remove a dead constant pool entry instruction. Update
/// sizes and offsets of impacted basic blocks.
void CSKYConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
MachineBasicBlock *CPEBB = CPEMI->getParent();
unsigned Size = CPEMI->getOperand(2).getImm();
CPEMI->eraseFromParent();
BBInfo[CPEBB->getNumber()].Size -= Size;
// All succeeding offsets have the current size value added in, fix this.
if (CPEBB->empty()) {
BBInfo[CPEBB->getNumber()].Size = 0;
// This block no longer needs to be aligned.
CPEBB->setAlignment(Align(1));
} else {
// Entries are sorted by descending alignment, so realign from the front.
CPEBB->setAlignment(getCPEAlign(*CPEBB->begin()));
}
adjustBBOffsetsAfter(CPEBB);
// An island has only one predecessor BB and one successor BB. Check if
// this BB's predecessor jumps directly to this BB's successor. This
// shouldn't happen currently.
assert(!bbIsJumpedOver(CPEBB) && "How did this happen?");
// FIXME: remove the empty blocks after all the work is done?
}
/// removeUnusedCPEntries - Remove constant pool entries whose refcounts
/// are zero.
bool CSKYConstantIslands::removeUnusedCPEntries() {
unsigned MadeChange = false;
for (unsigned I = 0, E = CPEntries.size(); I != E; ++I) {
std::vector<CPEntry> &CPEs = CPEntries[I];
for (unsigned J = 0, Ee = CPEs.size(); J != Ee; ++J) {
if (CPEs[J].RefCount == 0 && CPEs[J].CPEMI) {
removeDeadCPEMI(CPEs[J].CPEMI);
CPEs[J].CPEMI = nullptr;
MadeChange = true;
}
}
}
return MadeChange;
}
/// isBBInRange - Returns true if the distance between specific MI and
/// specific BB can fit in MI's displacement field.
bool CSKYConstantIslands::isBBInRange(MachineInstr *MI,
MachineBasicBlock *DestBB,
unsigned MaxDisp) {
unsigned PCAdj = 4;
unsigned BrOffset = getOffsetOf(MI) + PCAdj;
unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB)
<< " from " << printMBBReference(*MI->getParent())
<< " max delta=" << MaxDisp << " from " << getOffsetOf(MI)
<< " to " << DestOffset << " offset "
<< int(DestOffset - BrOffset) << "\t" << *MI);
if (BrOffset <= DestOffset) {
// Branch before the Dest.
if (DestOffset - BrOffset <= MaxDisp)
return true;
} else {
if (BrOffset - DestOffset <= MaxDisp)
return true;
}
return false;
}
/// fixupImmediateBr - Fix up an immediate branch whose destination is too far
/// away to fit in its displacement field.
bool CSKYConstantIslands::fixupImmediateBr(ImmBranch &Br) {
MachineInstr *MI = Br.MI;
MachineBasicBlock *DestBB = TII->getBranchDestBlock(*MI);
// Check to see if the DestBB is already in-range.
if (isBBInRange(MI, DestBB, Br.MaxDisp))
return false;
if (!Br.IsCond)
return fixupUnconditionalBr(Br);
return fixupConditionalBr(Br);
}
/// fixupUnconditionalBr - Fix up an unconditional branch whose destination is
/// too far away to fit in its displacement field. If the LR register has been
/// spilled in the epilogue, then we can use BSR to implement a far jump.
/// Otherwise, add an intermediate branch instruction to a branch.
bool CSKYConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
MachineInstr *MI = Br.MI;
MachineBasicBlock *MBB = MI->getParent();
MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
// Use BSR to implement far jump.
unsigned BR32MaxDisp = ((1 << 16) - 1) * 2;
if (isBBInRange(MI, DestBB, BR32MaxDisp)) {
Br.MaxDisp = BR32MaxDisp;
MI->setDesc(TII->get(CSKY::BR32));
} else {
// need to give the math a more careful look here
// this is really a segment address and not
// a PC relative address. FIXME. But I think that
// just reducing the bits by 1 as I've done is correct.
// The basic block we are branching too much be longword aligned.
// we know that RA is saved because we always save it right now.
// this requirement will be relaxed later but we also have an alternate
// way to implement this that I will implement that does not need jal.
// We should have a way to back out this alignment restriction
// if we "can" later. but it is not harmful.
//
DestBB->setAlignment(Align(4));
Br.MaxDisp = ((1 << 26) - 1) * 2;
MI->setDesc(TII->get(CSKY::BSR32));
}
BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(*MI);
adjustBBOffsetsAfter(MBB);
HasFarJump = true;
++NumUBrFixed;
LLVM_DEBUG(dbgs() << " Changed B to long jump " << *MI);
return true;
}
/// fixupConditionalBr - Fix up a conditional branch whose destination is too
/// far away to fit in its displacement field. It is converted to an inverse
/// conditional branch + an unconditional branch to the destination.
bool CSKYConstantIslands::fixupConditionalBr(ImmBranch &Br) {
MachineInstr *MI = Br.MI;
MachineBasicBlock *DestBB = TII->getBranchDestBlock(*MI);
unsigned Opcode = MI->getOpcode();
unsigned LongFormOpcode = longformBranchOpcode(Opcode);
unsigned LongFormMaxOff = branchMaxOffsets(LongFormOpcode);
// Check to see if the DestBB is already in-range.
if (isBBInRange(MI, DestBB, LongFormMaxOff)) {
Br.MaxDisp = LongFormMaxOff;
MI->setDesc(TII->get(LongFormOpcode));
return true;
}
// Add an unconditional branch to the destination and invert the branch
// condition to jump over it:
// bteqz L1
// =>
// bnez L2
// b L1
// L2:
// If the branch is at the end of its MBB and that has a fall-through block,
// direct the updated conditional branch to the fall-through block. Otherwise,
// split the MBB before the next instruction.
MachineBasicBlock *MBB = MI->getParent();
MachineInstr *BMI = &MBB->back();
bool NeedSplit = (BMI != MI) || !bbHasFallthrough(MBB);
++NumCBrFixed;
if (BMI != MI) {
if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) &&
BMI->isUnconditionalBranch()) {
// Last MI in the BB is an unconditional branch. Can we simply invert the
// condition and swap destinations:
// beqz L1
// b L2
// =>
// bnez L2
// b L1
MachineBasicBlock *NewDest = TII->getBranchDestBlock(*BMI);
if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
LLVM_DEBUG(
dbgs() << " Invert Bcc condition and swap its destination with "
<< *BMI);
BMI->getOperand(BMI->getNumExplicitOperands() - 1).setMBB(DestBB);
MI->getOperand(MI->getNumExplicitOperands() - 1).setMBB(NewDest);
SmallVector<MachineOperand, 4> Cond;
Cond.push_back(MachineOperand::CreateImm(MI->getOpcode()));
Cond.push_back(MI->getOperand(0));
TII->reverseBranchCondition(Cond);
return true;
}
}
}
if (NeedSplit) {
splitBlockBeforeInstr(*MI);
// No need for the branch to the next block. We're adding an unconditional
// branch to the destination.
int Delta = TII->getInstSizeInBytes(MBB->back());
BBInfo[MBB->getNumber()].Size -= Delta;
MBB->back().eraseFromParent();
// BBInfo[SplitBB].Offset is wrong temporarily, fixed below
}
MachineBasicBlock *NextBB = &*++MBB->getIterator();
LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB)
<< " also invert condition and change dest. to "
<< printMBBReference(*NextBB) << "\n");
// Insert a new conditional branch and a new unconditional branch.
// Also update the ImmBranch as well as adding a new entry for the new branch.
auto *NewMI = BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
.addReg(MI->getOperand(0).getReg())
.addMBB(NextBB)
.getInstr();
SmallVector<MachineOperand, 4> Cond;
Cond.push_back(MachineOperand::CreateImm(NewMI->getOpcode()));
Cond.push_back(NewMI->getOperand(0));
TII->reverseBranchCondition(Cond);
Br.MI = &MBB->back();
BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
// Remove the old conditional branch. It may or may not still be in MBB.
BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
MI->eraseFromParent();
adjustBBOffsetsAfter(MBB);
return true;
}
/// Returns a pass that converts branches to long branches.
FunctionPass *llvm::createCSKYConstantIslandPass() {
return new CSKYConstantIslands();
}
INITIALIZE_PASS(CSKYConstantIslands, DEBUG_TYPE,
"CSKY constant island placement and branch shortening pass",
false, false)
No newline at end of file

llvm/lib/Target/CSKY/CSKYConstantPoolValue.h

  • This file was added.
//===-- CSKYConstantPoolValue.h - CSKY constantpool value -----*- C++ -*---===//
//
craig.topperUnsubmitted
Done
ReplyInline Actions

Pad to 80 columns

craig.topper: Pad to 80 columns
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements the CSKY specific constantpool value class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_CSKY_CONSTANTPOOLVALUE_H
#define LLVM_TARGET_CSKY_CONSTANTPOOLVALUE_H
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/Support/ErrorHandling.h"
#include <cstddef>
namespace llvm {
class BlockAddress;
class Constant;
class GlobalValue;
class LLVMContext;
class MachineBasicBlock;
namespace CSKYCP {
enum CSKYCPKind {
CPValue,
CPExtSymbol,
CPBlockAddress,
CPLSDA,
CPMachineBasicBlock,
CPJT
};
enum CSKYCPModifier { no_modifier, TLSGD, GOT, GOTOFF, GOTTPOFF, TPOFF };
} // namespace CSKYCP
/// CSKYConstantPoolValue - CSKY specific constantpool value. This is used to
/// represent PC-relative displacement between the address of the load
/// instruction and the constant being loaded, i.e. (&GV-(LPIC+8)).
class CSKYConstantPoolValue : public MachineConstantPoolValue {
unsigned LabelId; // Label id of the load.
CSKYCP::CSKYCPKind Kind; // Kind of constant.
unsigned char PCAdjust; // Extra adjustment if constantpool is pc-relative.
// 8 for CSKY, 4 for Thumb.
CSKYCP::CSKYCPModifier Modifier; // GV modifier i.e. (&GV(modifier)-(LPIC+8))
bool AddCurrentAddress;
protected:
CSKYConstantPoolValue(Type *Ty, unsigned id, CSKYCP::CSKYCPKind Kind,
unsigned char PCAdj, CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress);
CSKYConstantPoolValue(LLVMContext &C, unsigned id, CSKYCP::CSKYCPKind Kind,
unsigned char PCAdj, CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress);
public:
virtual ~CSKYConstantPoolValue();
CSKYCP::CSKYCPModifier getModifier() const { return Modifier; }
const char *getModifierText() const;
bool hasModifier() const { return Modifier != CSKYCP::no_modifier; }
bool mustAddCurrentAddress() const { return AddCurrentAddress; }
unsigned getLabelId() const { return LabelId; }
unsigned char getPCAdjustment() const { return PCAdjust; }
bool isGlobalValue() const { return Kind == CSKYCP::CPValue; }
bool isExtSymbol() const { return Kind == CSKYCP::CPExtSymbol; }
bool isBlockAddress() const { return Kind == CSKYCP::CPBlockAddress; }
bool isLSDA() const { return Kind == CSKYCP::CPLSDA; }
bool isMachineBasicBlock() const {
return Kind == CSKYCP::CPMachineBasicBlock;
}
bool isJT() const { return Kind == CSKYCP::CPJT; }
bool equals(const CSKYConstantPoolValue *A) const {
return this->LabelId == A->LabelId && this->PCAdjust == A->PCAdjust &&
this->Modifier == A->Modifier;
}
void dump() const;
virtual unsigned getRelocationInfo() const { return 2; }
/// hasSameValue - Return true if this CSKY constpool value can share the same
/// constantpool entry as another CSKY constpool value.
virtual bool hasSameValue(CSKYConstantPoolValue *ACPV);
int getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) override;
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
void print(raw_ostream &O) const override;
};
inline raw_ostream &operator<<(raw_ostream &O, const CSKYConstantPoolValue &V) {
V.print(O);
return O;
}
/// CSKYConstantPoolConstant - CSKY-specific constant pool values for Constants,
/// Functions, and BlockAddresses.
class CSKYConstantPoolConstant : public CSKYConstantPoolValue {
const Constant *CVal; // Constant being loaded.
CSKYConstantPoolConstant(const Constant *C, unsigned ID,
CSKYCP::CSKYCPKind Kind, unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress);
CSKYConstantPoolConstant(Type *Ty, const Constant *C, unsigned ID,
CSKYCP::CSKYCPKind Kind, unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress);
public:
static CSKYConstantPoolConstant *Create(const Constant *C, unsigned ID);
static CSKYConstantPoolConstant *Create(const GlobalValue *GV,
CSKYCP::CSKYCPModifier Modifier);
static CSKYConstantPoolConstant *Create(const Constant *C, unsigned ID,
CSKYCP::CSKYCPKind Kind,
unsigned char PCAdj);
static CSKYConstantPoolConstant *Create(const Constant *C, unsigned ID,
CSKYCP::CSKYCPKind Kind,
unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress);
const GlobalValue *getGV() const;
const BlockAddress *getBlockAddress() const;
int getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) override;
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
void print(raw_ostream &O) const override;
/// hasSameValue - Return true if this CSKY constpool value can share the same
/// constantpool entry as another CSKY constpool value.
virtual bool hasSameValue(CSKYConstantPoolValue *ACPV);
static bool classof(const CSKYConstantPoolValue *APV) {
return APV->isGlobalValue() || APV->isBlockAddress() || APV->isLSDA();
}
};
/// CSKYConstantPoolSymbol - CSKY-specific constantpool values for external
/// symbols.
class CSKYConstantPoolSymbol : public CSKYConstantPoolValue {
const char *S; // ExtSymbol being loaded.
CSKYConstantPoolSymbol(LLVMContext &C, const char *s, unsigned id,
unsigned char PCAdj, CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress);
public:
~CSKYConstantPoolSymbol();
static CSKYConstantPoolSymbol *Create(LLVMContext &C, const char *s,
unsigned ID, unsigned char PCAdj);
const char *getSymbol() const { return S; }
int getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) override;
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
void print(raw_ostream &O) const override;
/// hasSameValue - Return true if this CSKY constpool value can share the same
/// constantpool entry as another CSKY constpool value.
virtual bool hasSameValue(CSKYConstantPoolValue *ACPV);
static bool classof(const CSKYConstantPoolValue *ACPV) {
return ACPV->isExtSymbol();
}
};
/// CSKYConstantPoolMBB - CSKY-specific constantpool value of a machine basic
/// block.
class CSKYConstantPoolMBB : public CSKYConstantPoolValue {
const MachineBasicBlock *MBB; // Machine basic block.
CSKYConstantPoolMBB(LLVMContext &C, const MachineBasicBlock *mbb, unsigned id,
unsigned char PCAdj, CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress);
public:
static CSKYConstantPoolMBB *Create(LLVMContext &C,
const MachineBasicBlock *mbb, unsigned ID,
unsigned char PCAdj);
const MachineBasicBlock *getMBB() const { return MBB; }
int getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) override;
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
void print(raw_ostream &O) const override;
/// hasSameValue - Return true if this CSKY constpool value can share the same
/// constantpool entry as another CSKY constpool value.
virtual bool hasSameValue(CSKYConstantPoolValue *ACPV);
static bool classof(const CSKYConstantPoolValue *ACPV) {
return ACPV->isMachineBasicBlock();
}
};
/// CSKYConstantPoolJT - CSKY-specific constantpool value of a jump table.
class CSKYConstantPoolJT : public CSKYConstantPoolValue {
signed JTI; // Machine basic block.
CSKYConstantPoolJT(LLVMContext &C, int JTIndex, unsigned id,
unsigned char PCAdj, CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress);
public:
static CSKYConstantPoolJT *Create(LLVMContext &C, int JTI, unsigned id,
unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier);
signed getJTI() { return JTI; }
int getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) override;
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
void print(raw_ostream &O) const override;
/// hasSameValue - Return true if this CSKY constpool value can share the same
/// constantpool entry as another CSKY constpool value.
virtual bool hasSameValue(CSKYConstantPoolValue *ACPV);
static bool classof(const CSKYConstantPoolValue *ACPV) {
return ACPV->isJT();
}
};
} // namespace llvm
#endif

llvm/lib/Target/CSKY/CSKYConstantPoolValue.cpp

  • This file was added.
//===-- CSKYConstantPoolValue.cpp - CSKY constantpool value ---------------===//
//
craig.topperUnsubmitted
Done
ReplyInline Actions

Pad to 80 columns

craig.topper: Pad to 80 columns
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements the CSKY specific constantpool value class.
//
//===----------------------------------------------------------------------===//
#include "CSKYConstantPoolValue.h"
#include "llvm/ADT/FoldingSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
// CSKYConstantPoolValue
//===----------------------------------------------------------------------===//
CSKYConstantPoolValue::CSKYConstantPoolValue(Type *Ty, unsigned Id,
CSKYCP::CSKYCPKind Kind,
unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress)
: MachineConstantPoolValue(Ty), LabelId(Id), Kind(Kind), PCAdjust(PCAdj),
Modifier(Modifier), AddCurrentAddress(AddCurrentAddress) {}
CSKYConstantPoolValue::CSKYConstantPoolValue(LLVMContext &C, unsigned Id,
CSKYCP::CSKYCPKind Kind,
unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress)
: MachineConstantPoolValue((Type *)Type::getInt32Ty(C)), LabelId(Id),
Kind(Kind), PCAdjust(PCAdj), Modifier(Modifier),
AddCurrentAddress(AddCurrentAddress) {}
CSKYConstantPoolValue::~CSKYConstantPoolValue() {}
const char *CSKYConstantPoolValue::getModifierText() const {
switch (Modifier) {
// FIXME: Are these case sensitive? It'd be nice to lower-case all the
// strings if that's legal.
case CSKYCP::no_modifier:
return "none";
case CSKYCP::TLSGD:
return "tlsgd";
case CSKYCP::GOT:
return "GOT";
case CSKYCP::GOTOFF:
return "GOTOFF";
case CSKYCP::GOTTPOFF:
return "gottpoff";
case CSKYCP::TPOFF:
return "tpoff";
}
llvm_unreachable("Unknown modifier!");
}
int CSKYConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) {
llvm_unreachable("Shouldn't be calling this directly!");
}
void CSKYConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
ID.AddInteger(LabelId);
ID.AddInteger(PCAdjust);
}
bool CSKYConstantPoolValue::hasSameValue(CSKYConstantPoolValue *CCPV) {
if (CCPV->Kind == Kind && CCPV->PCAdjust == PCAdjust &&
CCPV->Modifier == Modifier) {
if (CCPV->LabelId == LabelId)
return true;
// Two PC relative constpool entries containing the same GV address or
// external symbols. FIXME: What about blockaddress?
if (Kind == CSKYCP::CPValue || Kind == CSKYCP::CPExtSymbol)
return true;
}
return false;
}
void CSKYConstantPoolValue::dump() const { errs() << " " << *this; }
void CSKYConstantPoolValue::print(raw_ostream &O) const {
if (Modifier)
O << "(" << getModifierText() << ")";
if (PCAdjust != 0) {
O << "-(LPC" << LabelId << "+" << (unsigned)PCAdjust;
if (AddCurrentAddress)
O << "-.";
O << ")";
}
}
//===----------------------------------------------------------------------===//
// CSKYConstantPoolConstant
//===----------------------------------------------------------------------===//
CSKYConstantPoolConstant::CSKYConstantPoolConstant(
Type *Ty, const Constant *C, unsigned ID, CSKYCP::CSKYCPKind Kind,
unsigned char PCAdj, CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress)
: CSKYConstantPoolValue(Ty, ID, Kind, PCAdj, Modifier, AddCurrentAddress),
CVal(C) {}
CSKYConstantPoolConstant::CSKYConstantPoolConstant(
const Constant *C, unsigned ID, CSKYCP::CSKYCPKind Kind,
unsigned char PCAdj, CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress)
: CSKYConstantPoolValue((Type *)C->getType(), ID, Kind, PCAdj, Modifier,
AddCurrentAddress),
CVal(C) {}
CSKYConstantPoolConstant *CSKYConstantPoolConstant::Create(const Constant *C,
unsigned ID) {
return new CSKYConstantPoolConstant(C, ID, CSKYCP::CPValue, 0,
CSKYCP::no_modifier, false);
}
CSKYConstantPoolConstant *
CSKYConstantPoolConstant::Create(const GlobalValue *GV,
CSKYCP::CSKYCPModifier Modifier) {
return new CSKYConstantPoolConstant(
(Type *)Type::getInt32Ty(GV->getContext()), GV, 0, CSKYCP::CPValue, 0,
Modifier, false);
}
CSKYConstantPoolConstant *
CSKYConstantPoolConstant::Create(const Constant *C, unsigned ID,
CSKYCP::CSKYCPKind Kind, unsigned char PCAdj) {
return new CSKYConstantPoolConstant(C, ID, Kind, PCAdj, CSKYCP::no_modifier,
false);
}
CSKYConstantPoolConstant *
CSKYConstantPoolConstant::Create(const Constant *C, unsigned ID,
CSKYCP::CSKYCPKind Kind, unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress) {
return new CSKYConstantPoolConstant(C, ID, Kind, PCAdj, Modifier,
AddCurrentAddress);
}
const GlobalValue *CSKYConstantPoolConstant::getGV() const {
assert(isa<GlobalValue>(CVal) && "CVal should be GlobalValue");
return cast<GlobalValue>(CVal);
}
const BlockAddress *CSKYConstantPoolConstant::getBlockAddress() const {
assert(isa<BlockAddress>(CVal) && "CVal should be BlockAddress");
return cast<BlockAddress>(CVal);
}
int CSKYConstantPoolConstant::getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) {
unsigned AlignMask = Alignment.value() - 1;
const std::vector<MachineConstantPoolEntry> Constants = CP->getConstants();
for (unsigned I = 0, E = Constants.size(); I != E; ++I) {
if (Constants[I].isMachineConstantPoolEntry() &&
(Constants[I].getAlign().value() & AlignMask) == 0) {
CSKYConstantPoolValue *CPV =
(CSKYConstantPoolValue *)Constants[I].Val.MachineCPVal;
CSKYConstantPoolConstant *APC = dyn_cast<CSKYConstantPoolConstant>(CPV);
if (!APC)
continue;
if (APC->CVal == CVal && equals(APC))
return I;
}
}
return -1;
}
bool CSKYConstantPoolConstant::hasSameValue(CSKYConstantPoolValue *CCPV) {
const CSKYConstantPoolConstant *ACPC =
dyn_cast<CSKYConstantPoolConstant>(CCPV);
return ACPC && ACPC->CVal == CVal &&
CSKYConstantPoolValue::hasSameValue(CCPV);
}
void CSKYConstantPoolConstant::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
ID.AddPointer(CVal);
CSKYConstantPoolValue::addSelectionDAGCSEId(ID);
}
void CSKYConstantPoolConstant::print(raw_ostream &O) const {
O << CVal->getName();
CSKYConstantPoolValue::print(O);
}
//===----------------------------------------------------------------------===//
// CSKYConstantPoolSymbol
//===----------------------------------------------------------------------===//
CSKYConstantPoolSymbol::CSKYConstantPoolSymbol(LLVMContext &C, const char *S,
unsigned Id, unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress)
: CSKYConstantPoolValue(C, Id, CSKYCP::CPExtSymbol, PCAdj, Modifier,
AddCurrentAddress),
S(strdup(S)) {}
CSKYConstantPoolSymbol::~CSKYConstantPoolSymbol() = default;
CSKYConstantPoolSymbol *CSKYConstantPoolSymbol::Create(LLVMContext &C,
const char *S,
unsigned ID,
unsigned char PCAdj) {
return new CSKYConstantPoolSymbol(C, S, ID, PCAdj, CSKYCP::no_modifier,
false);
}
static bool cpvStreq(const char *S1, const char *S2) {
if (S1 == S2)
return true;
if (S1 && S2 && strcmp(S1, S2) == 0)
return true;
return false;
}
int CSKYConstantPoolSymbol::getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) {
unsigned AlignMask = Alignment.value() - 1;
const std::vector<MachineConstantPoolEntry> Constants = CP->getConstants();
for (unsigned I = 0, E = Constants.size(); I != E; ++I) {
if (Constants[I].isMachineConstantPoolEntry() &&
(Constants[I].getAlign().value() & AlignMask) == 0) {
CSKYConstantPoolValue *CPV =
(CSKYConstantPoolValue *)Constants[I].Val.MachineCPVal;
CSKYConstantPoolSymbol *APS = dyn_cast<CSKYConstantPoolSymbol>(CPV);
if (!APS)
continue;
if (cpvStreq(APS->S, S) && equals(APS))
return I;
}
}
return -1;
}
bool CSKYConstantPoolSymbol::hasSameValue(CSKYConstantPoolValue *CCPV) {
const CSKYConstantPoolSymbol *ACPS = dyn_cast<CSKYConstantPoolSymbol>(CCPV);
return ACPS && cpvStreq(ACPS->S, S) &&
CSKYConstantPoolValue::hasSameValue(CCPV);
}
void CSKYConstantPoolSymbol::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
ID.AddPointer(S);
CSKYConstantPoolValue::addSelectionDAGCSEId(ID);
}
void CSKYConstantPoolSymbol::print(raw_ostream &O) const {
O << S;
CSKYConstantPoolValue::print(O);
}
//===----------------------------------------------------------------------===//
// CSKYConstantPoolMBB
//===----------------------------------------------------------------------===//
CSKYConstantPoolMBB::CSKYConstantPoolMBB(LLVMContext &C,
const MachineBasicBlock *Mbb,
unsigned Id, unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress)
: CSKYConstantPoolValue(C, Id, CSKYCP::CPMachineBasicBlock, PCAdj, Modifier,
AddCurrentAddress),
MBB(Mbb) {}
CSKYConstantPoolMBB *CSKYConstantPoolMBB::Create(LLVMContext &C,
const MachineBasicBlock *Mbb,
unsigned ID,
unsigned char PCAdj) {
return new CSKYConstantPoolMBB(C, Mbb, ID, PCAdj, CSKYCP::no_modifier, false);
}
int CSKYConstantPoolMBB::getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) {
unsigned AlignMask = Alignment.value() - 1;
const std::vector<MachineConstantPoolEntry> Constants = CP->getConstants();
for (unsigned I = 0, E = Constants.size(); I != E; ++I) {
if (Constants[I].isMachineConstantPoolEntry() &&
(Constants[I].getAlign().value() & AlignMask) == 0) {
CSKYConstantPoolValue *CPV =
(CSKYConstantPoolValue *)Constants[I].Val.MachineCPVal;
CSKYConstantPoolMBB *APMBB = dyn_cast<CSKYConstantPoolMBB>(CPV);
if (!APMBB)
continue;
if (APMBB->MBB == MBB && equals(APMBB))
return I;
}
}
return -1;
}
bool CSKYConstantPoolMBB::hasSameValue(CSKYConstantPoolValue *CCPV) {
const CSKYConstantPoolMBB *ACPMBB = dyn_cast<CSKYConstantPoolMBB>(CCPV);
return ACPMBB && ACPMBB->MBB == MBB &&
CSKYConstantPoolValue::hasSameValue(CCPV);
}
void CSKYConstantPoolMBB::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
ID.AddPointer(MBB);
CSKYConstantPoolValue::addSelectionDAGCSEId(ID);
}
void CSKYConstantPoolMBB::print(raw_ostream &O) const {
O << "BB#" << MBB->getNumber();
CSKYConstantPoolValue::print(O);
}
//===----------------------------------------------------------------------===//
// CSKYConstantPoolJT
//===----------------------------------------------------------------------===//
CSKYConstantPoolJT::CSKYConstantPoolJT(LLVMContext &C, int JTIndex, unsigned Id,
unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier,
bool AddCurrentAddress)
: CSKYConstantPoolValue(C, Id, CSKYCP::CPJT, PCAdj, Modifier,
AddCurrentAddress),
JTI(JTIndex) {}
CSKYConstantPoolJT *
CSKYConstantPoolJT::Create(LLVMContext &C, int JTI, unsigned Id,
unsigned char PCAdj,
CSKYCP::CSKYCPModifier Modifier) {
return new CSKYConstantPoolJT(C, JTI, Id, PCAdj, Modifier, false);
}
int CSKYConstantPoolJT::getExistingMachineCPValue(MachineConstantPool *CP,
Align Alignment) {
unsigned AlignMask = Alignment.value() - 1;
const std::vector<MachineConstantPoolEntry> Constants = CP->getConstants();
for (unsigned I = 0, E = Constants.size(); I != E; ++I) {
if (Constants[I].isMachineConstantPoolEntry() &&
(Constants[I].getAlign().value() & AlignMask) == 0) {
CSKYConstantPoolValue *CPV =
(CSKYConstantPoolValue *)Constants[I].Val.MachineCPVal;
CSKYConstantPoolJT *APJT = dyn_cast<CSKYConstantPoolJT>(CPV);
if (!APJT)
continue;
if (APJT->JTI == JTI && equals(APJT))
return I;
}
}
return -1;
}
bool CSKYConstantPoolJT::hasSameValue(CSKYConstantPoolValue *CCPV) {
const CSKYConstantPoolJT *ACPJT = dyn_cast<CSKYConstantPoolJT>(CCPV);
return ACPJT && ACPJT->JTI == JTI &&
CSKYConstantPoolValue::hasSameValue(CCPV);
}
void CSKYConstantPoolJT::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
ID.AddInteger(JTI);
CSKYConstantPoolValue::addSelectionDAGCSEId(ID);
}
void CSKYConstantPoolJT::print(raw_ostream &O) const {
O << "JTI#" << JTI;
CSKYConstantPoolValue::print(O);
}

llvm/lib/Target/CSKY/CSKYFrameLowering.h

llvm/lib/Target/CSKY/CSKYFrameLowering.cpp

  • This file was added.
//===-- CSKYFrameLowering.h - Define frame lowering for CSKY -*- C++ -*----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class implements CSKY-specific bits of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//
#include "CSKYFrameLowering.h"
#include "CSKYMachineFunctionInfo.h"
#include "CSKYSubtarget.h"
#include "Utils/CSKYBaseInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/RegisterScavenging.h"
using namespace llvm;
CSKYFrameLowering::CSKYFrameLowering(const CSKYSubtarget &STI)
: TargetFrameLowering(StackGrowsDown, /*StackAlignment*/ Align(4),
/*LocalAreaOffset*/ 0),
STI(STI) {
v2sf = STI.hasFPUv2SingleFloat();
v2df = STI.hasFPUv2DoubleFloat();
craig.topperUnsubmitted
Done
ReplyInline Actions

Capitalize variable name

craig.topper: Capitalize variable name
v3sf = STI.hasFPUv3SingleFloat();
v3df = STI.hasFPUv3DoubleFloat();
}
// TODO: mov this function to instr info
static void emitSPAdj(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
const DebugLoc &DL, const CSKYInstrInfo *TII,
int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
bool IsSub = NumBytes < 0;
unsigned Opc = IsSub ? CSKY::SUBI32 : CSKY::ADDI32;
if (IsSub)
NumBytes = -NumBytes;
unsigned Value;
while (NumBytes) {
if (NumBytes > 0x1000) {
NumBytes -= 0x1000;
Value = 0x1000;
} else {
Value = NumBytes;
NumBytes = 0;
}
BuildMI(MBB, MBBI, DL, TII->get(Opc), CSKY::SP)
.addReg(CSKY::SP)
.addImm(Value)
.setMIFlags(MIFlags);
}
}
void CSKYFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned StackSize = MFI.getStackSize();
const CSKYInstrInfo *TII = STI.getInstrInfo();
CSKYMachineFunctionInfo *FuncInfo = MF.getInfo<CSKYMachineFunctionInfo>();
unsigned CSRSize = FuncInfo->getCSRSize();
DebugLoc DL;
// Callee saved registers already spilled.
// TODO: Allocate vararg register save area.
// arg regs save size
// Skip FrameSetup instructions
while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
++MBBI;
// Insert CFI
// Allocas
unsigned NumBytes = StackSize - CSRSize;
emitSPAdj(MBB, MBBI, DL, TII, -NumBytes, MachineInstr::FrameSetup);
}
void CSKYFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
CSKYMachineFunctionInfo *FuncInfo = MF.getInfo<CSKYMachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.end();
const MachineFrameInfo &MFI = MF.getFrameInfo();
const CSKYInstrInfo *TII = STI.getInstrInfo();
unsigned StackSize = MFI.getStackSize();
unsigned CSRSize = FuncInfo->getCSRSize();
DebugLoc DL;
if (!MBB.empty()) {
MBBI = MBB.getFirstTerminator();
if (MBBI == MBB.end())
MBBI = MBB.getLastNonDebugInstr();
DL = MBBI->getDebugLoc();
if (!MBBI->isTerminator())
MBBI = std::next(MBBI);
while (MBBI != MBB.begin() &&
std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy))
--MBBI;
}
unsigned NumBytes = StackSize - CSRSize;
emitSPAdj(MBB, MBBI, DL, TII, NumBytes, MachineInstr::FrameDestroy);
}
bool CSKYFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
return MF.getTarget().Options.DisableFramePointerElim(MF) ||
RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
MFI.isFrameAddressTaken();
}
bool CSKYFrameLowering::hasBP(const MachineFunction &MF) const { return false; }
bool CSKYFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
return !MF.getFrameInfo().hasVarSizedObjects();
}
int CSKYFrameLowering::resolveFrameIndexReference(const MachineFunction &MF,
int FI, Register &FrameReg,
int SPAdj) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize();
// int Spilled = FuncInfo->getFrameSpillOffset();
// TODO: Use fp
// int FPOffset = Offset - CFI->getFrameSpillOffset();
// Negative FI denotes this is an incoming parameter.
// bool isFixed = MFI.isFixedObjectIndex(FI);
FrameReg = CSKY::SP;
Offset += SPAdj;
return Offset;
}
bool CSKYFrameLowering::spillCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
MachineFunction &MF = *MBB.getParent();
const CSKYInstrInfo *TII = STI.getInstrInfo();
CSKYMachineFunctionInfo *FuncInfo = MF.getInfo<CSKYMachineFunctionInfo>();
unsigned CSRSize = FuncInfo->getCSRSize();
DebugLoc DL;
if (MI != MBB.end() && !MI->isDebugInstr())
DL = MI->getDebugLoc();
emitSPAdj(MBB, MI, DL, TII, -CSRSize, MachineInstr::FrameSetup);
for (const auto &Info : CSI) {
Register Reg = Info.getReg();
int FI = Info.getFrameIdx();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII->storeRegToStackSlot(MBB, MI, Reg, getKillRegState(true), FI, RC,
STI.getRegisterInfo());
MachineInstrBuilder(MF, std::prev(MI)).setMIFlag(MachineInstr::FrameSetup);
}
return true;
}
bool CSKYFrameLowering::restoreCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
MachineFunction &MF = *MBB.getParent();
const CSKYInstrInfo *TII = STI.getInstrInfo();
CSKYMachineFunctionInfo *FuncInfo = MF.getInfo<CSKYMachineFunctionInfo>();
unsigned CSRSize = FuncInfo->getCSRSize();
DebugLoc DL;
if (MI != MBB.end() && !MI->isDebugInstr())
DL = MI->getDebugLoc();
for (const auto &Info : CSI) {
Register Reg = Info.getReg();
int FI = Info.getFrameIdx();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII->loadRegFromStackSlot(MBB, MI, Reg, FI, RC, STI.getRegisterInfo());
MachineInstrBuilder(MF, std::prev(MI))
.setMIFlag(MachineInstr::FrameDestroy);
}
emitSPAdj(MBB, MI, DL, TII, CSRSize, MachineInstr::FrameDestroy);
return true;
}
void CSKYFrameLowering::determineCalleeSaves(MachineFunction &MF,
BitVector &SavedRegs,
RegScavenger *RS) const {
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
CSKYMachineFunctionInfo *FuncInfo = MF.getInfo<CSKYMachineFunctionInfo>();
const CSKYRegisterInfo *RegInfo = static_cast<const CSKYRegisterInfo *>(
MF.getSubtarget().getRegisterInfo());
MachineFrameInfo &MFI = MF.getFrameInfo();
bool HasFP = hasFP(MF);
bool HasBP = hasBP(MF);
Register FrameReg = RegInfo->getFrameRegister(MF);
Register BaseReg = RegInfo->getBaseRegister();
bool CanEliminateFrame = true;
unsigned GPRSpilledCnt = 0;
unsigned FPR32SpilledCnt = 0;
unsigned FPR64SpilledCnt = 0;
if (HasFP)
SavedRegs.set(FrameReg);
if (HasBP)
SavedRegs.set(BaseReg);
if (FuncInfo->getGlobalBaseReg() != 0)
SavedRegs.set(FuncInfo->getGlobalBaseReg());
const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
for (unsigned I = 0; CSRegs[I]; ++I) {
unsigned Reg = CSRegs[I];
if (SavedRegs.test(Reg)) {
// record spilled CSRSize
CanEliminateFrame = false;
if (CSKY::GPRRegClass.contains(Reg))
++GPRSpilledCnt;
else if (CSKY::FPR32RegClass.contains(Reg) ||
CSKY::sFPR32RegClass.contains(Reg))
++FPR32SpilledCnt;
else if (CSKY::FPR64RegClass.contains(Reg) ||
CSKY::sFPR64RegClass.contains(Reg))
++FPR64SpilledCnt;
else
assert(0 && "unknown reg class");
} else {
// TODO: record unspilled GPR
}
}
if (!CanEliminateFrame)
FuncInfo->setHasStackFrame(true);
FuncInfo->setCSRSize(GPRSpilledCnt * 4 + FPR32SpilledCnt * 4 +
FPR64SpilledCnt * 8);
if (FuncInfo->isCRSpilled())
RS->addScavengingFrameIndex(MFI.CreateFixedObject(4, 4, false));
}
MachineBasicBlock::iterator CSKYFrameLowering::eliminateCallFramePseudoInstr(
MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
const CSKYInstrInfo *TII = STI.getInstrInfo();
DebugLoc DL = MI->getDebugLoc();
if (!hasReservedCallFrame(MF)) {
int64_t Amount = MI->getOperand(0).getImm();
if (MI->getOpcode() == CSKY::ADJCALLSTACKDOWN)
Amount = -Amount;
// Adjust sp register
emitSPAdj(MBB, MI, DL, TII, Amount);
}
return MBB.erase(MI);
}

llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp

  • This file was added.
//===-- CSKYISelDAGToDAG.cpp - A dag to dag inst selector for CSKY---------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines an instruction selector for the CSKY target.
//
//===----------------------------------------------------------------------===//
#include "CSKY.h"
#include "CSKYConstantPoolValue.h"
#include "CSKYTargetMachine.h"
#include "MCTargetDesc/CSKYMCTargetDesc.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
using namespace llvm;
#define DEBUG_TYPE "csky-isel"
namespace {
class CSKYDAGToDAGISel : public SelectionDAGISel {
const CSKYSubtarget *Subtarget;
public:
explicit CSKYDAGToDAGISel(CSKYTargetMachine &TM) : SelectionDAGISel(TM) {}
StringRef getPassName() const override {
return "CSKY DAG->DAG Pattern Instruction Selection";
}
bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through.
Subtarget = &MF.getSubtarget<CSKYSubtarget>();
SelectionDAGISel::runOnMachineFunction(MF);
return true;
}
void Select(SDNode *N) override;
bool selectAddrFi(SDValue Addr, SDValue &Base);
bool selectAddCarry(SDNode *N);
bool selectSubCarry(SDNode *N);
bool selectMulLohi(SDNode *N);
bool selectSdivrem(SDNode *N);
#include "CSKYGenDAGISel.inc"
};
} // namespace
void CSKYDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode()) {
LLVM_DEBUG(dbgs() << "== "; N->dump(CurDAG); dbgs() << "\n");
N->setNodeId(-1);
return;
}
SDLoc Dl(N);
unsigned Opcode = N->getOpcode();
bool IsSelected = false;
switch (Opcode) {
default:
break;
case ISD::ADDCARRY:
IsSelected = selectAddCarry(N);
break;
case ISD::SUBCARRY:
IsSelected = selectSubCarry(N);
break;
case ISD::UMUL_LOHI:
case ISD::SMUL_LOHI:
IsSelected = selectMulLohi(N);
break;
case ISD::SDIVREM:
IsSelected = selectSdivrem(N);
break;
case ISD::GLOBAL_OFFSET_TABLE:
Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
ReplaceNode(N, CurDAG->getRegister(GP, N->getValueType(0)).getNode());
IsSelected = true;
break;
}
if (IsSelected)
return;
SelectCode(N);
}
bool CSKYDAGToDAGISel::selectSdivrem(SDNode *N) {
craig.topperUnsubmitted
Done
ReplyInline Actions

I believe LLVM style would prefer "auto *SDIVREM" over "auto SDIVREM" so it;s clear to the read it is a pointer. This applies to other places in this file.

craig.topper: I believe LLVM style would prefer "auto *SDIVREM" over "auto SDIVREM" so it;s clear to the read…
auto VT = N->getValueType(0);
auto *SDIVREM = CurDAG->getMachineNode(CSKY::DIVF, SDLoc(N), MVT::Untyped,
{N->getOperand(0), N->getOperand(1)});
SDValue SDIV = CurDAG->getTargetExtractSubreg(CSKY::GPRSubReg0, SDLoc(N), VT,
SDValue(SDIVREM, 0));
SDValue SRem = CurDAG->getTargetExtractSubreg(CSKY::GPRSubReg1, SDLoc(N), VT,
SDValue(SDIVREM, 0));
ReplaceUses(SDValue(N, 0), SDIV);
ReplaceUses(SDValue(N, 1), SRem);
CurDAG->RemoveDeadNode(N);
return true;
}
bool CSKYDAGToDAGISel::selectMulLohi(SDNode *N) {
auto VT = N->getValueType(0);
auto *MULOHI = CurDAG->getMachineNode(
N->getOpcode() == ISD::UMUL_LOHI ? CSKY::MULU32 : CSKY::MULS32, SDLoc(N),
MVT::Untyped, {N->getOperand(0), N->getOperand(1)});
SDValue Lo = CurDAG->getTargetExtractSubreg(CSKY::GPRSubReg0, SDLoc(N), VT,
SDValue(MULOHI, 0));
SDValue Hi = CurDAG->getTargetExtractSubreg(CSKY::GPRSubReg1, SDLoc(N), VT,
SDValue(MULOHI, 0));
ReplaceUses(SDValue(N, 0), Lo);
ReplaceUses(SDValue(N, 1), Hi);
CurDAG->RemoveDeadNode(N);
return true;
}
bool CSKYDAGToDAGISel::selectAddCarry(SDNode *N) {
MachineSDNode *NewNode = nullptr;
auto Type0 = N->getValueType(0);
auto Type1 = N->getValueType(1);
auto Op0 = N->getOperand(0);
auto Op1 = N->getOperand(1);
auto Op2 = N->getOperand(2);
SDLoc Dl(N);
if (isNullConstant(Op2)) {
auto *CA = CurDAG->getMachineNode(CSKY::CLRC32, Dl, Type1);
NewNode = CurDAG->getMachineNode(CSKY::ADDC32, Dl, {Type0, Type1},
{Op0, Op1, SDValue(CA, 0)});
} else if (isOneConstant(Op2)) {
auto *CA = CurDAG->getMachineNode(CSKY::SETC32, Dl, Type1);
NewNode = CurDAG->getMachineNode(CSKY::ADDC32, Dl, {Type0, Type1},
{Op0, Op1, SDValue(CA, 0)});
} else {
NewNode = CurDAG->getMachineNode(CSKY::ADDC32, Dl, {Type0, Type1},
{Op0, Op1, Op2});
}
ReplaceNode(N, NewNode);
return true;
}
bool CSKYDAGToDAGISel::selectSubCarry(SDNode *N) {
MachineSDNode *NewNode = nullptr;
auto Type0 = N->getValueType(0);
auto Type1 = N->getValueType(1);
auto Op0 = N->getOperand(0);
auto Op1 = N->getOperand(1);
auto Op2 = N->getOperand(2);
SDLoc Dl(N);
if (isNullConstant(Op2)) {
auto *CA = CurDAG->getMachineNode(CSKY::SETC32, Dl, Type1);
NewNode = CurDAG->getMachineNode(CSKY::SUBC32, Dl, {Type0, Type1},
{Op0, Op1, SDValue(CA, 0)});
} else if (isOneConstant(Op2)) {
auto *CA = CurDAG->getMachineNode(CSKY::CLRC32, Dl, Type1);
NewNode = CurDAG->getMachineNode(CSKY::SUBC32, Dl, {Type0, Type1},
{Op0, Op1, SDValue(CA, 0)});
} else {
NewNode = CurDAG->getMachineNode(CSKY::SUBC32, Dl, {Type0, Type1},
{Op0, Op1, Op2});
}
ReplaceNode(N, NewNode);
return true;
}
bool CSKYDAGToDAGISel::selectAddrFi(SDValue Addr, SDValue &Base) {
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
return true;
}
return false;
}
FunctionPass *llvm::createCSKYISelDag(CSKYTargetMachine &TM) {
return new CSKYDAGToDAGISel(TM);
}
No newline at end of file

llvm/lib/Target/CSKY/CSKYISelLowering.h

llvm/lib/Target/CSKY/CSKYISelLowering.cpp

  • This file was added.
//===-- CSKYISelLowering.cpp - CSKY DAG Lowering Implementation ----------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines the interfaces that CSKY uses to lower LLVM code into a
// selection DAG.
//
//===----------------------------------------------------------------------===//
#include "CSKYISelLowering.h"
#include "CSKYCallingConv.h"
#include "CSKYConstantPoolValue.h"
#include "CSKYMachineFunctionInfo.h"
#include "CSKYRegisterInfo.h"
#include "CSKYSubtarget.h"
#include "Utils/CSKYBaseInfo.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/IR/IntrinsicsCSKY.h"
#include "llvm/Support/Debug.h"
using namespace llvm;
#include "CSKYGenCallingConv.inc"
#include "CSKYMachineFunctionInfo.h"
craig.topperUnsubmitted
Done
ReplyInline Actions

Use MCPhysReg instead of uint16_t.

craig.topper: Use MCPhysReg instead of uint16_t.
static const MCPhysReg GPRArgRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3};
CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
const CSKYSubtarget &STI)
: TargetLowering(TM), Subtarget(STI) {
// Register Class
addRegisterClass(MVT::i32, &CSKY::GPRRegClass);
if (!STI.useSoftFloat()) {
if (STI.hasFPUv2SingleFloat())
addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass);
else if (STI.hasFPUv3SingleFloat())
addRegisterClass(MVT::f32, &CSKY::FPR32RegClass);
if (STI.hasFPUv2DoubleFloat())
addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass);
else if (STI.hasFPUv3DoubleFloat())
addRegisterClass(MVT::f64, &CSKY::FPR64RegClass);
}
// Compute derived properties from the register classes.
computeRegisterProperties(STI.getRegisterInfo());
// Integer
setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
setOperationAction(ISD::BR_CC, MVT::i32, Expand);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
// IF NODSPV1
setOperationAction(ISD::MULHS, MVT::i32, Expand);
setOperationAction(ISD::MULHU, MVT::i32, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::i32, MVT::i1, Promote);
setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, MVT::i1, Promote);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
setOperationAction(ISD::JumpTable, MVT::i32, Custom);
setOperationAction(ISD::ExternalSymbol, MVT::i32, Custom);
// Float
ISD::CondCode FPCCToExtend[] = {
ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
ISD::SETUGE, ISD::SETULT, ISD::SETULE,
};
if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat()) {
setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
setOperationAction(ISD::FREM, MVT::f32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
setOperationAction(ISD::BR_CC, MVT::f32, Expand);
if (STI.hasFPUv2SingleFloat())
setOperationAction(ISD::SELECT, MVT::f32, Expand);
for (auto CC : FPCCToExtend)
setCondCodeAction(CC, MVT::f32, Expand);
}
if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat()) {
setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
setOperationAction(ISD::FREM, MVT::f64, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
setOperationAction(ISD::BR_CC, MVT::f64, Expand);
if (STI.hasFPUv2DoubleFloat())
setOperationAction(ISD::SELECT, MVT::f64, Expand);
for (auto CC : FPCCToExtend)
setCondCodeAction(CC, MVT::f64, Expand);
}
// DAG combine
// Attributes
setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
setMaxAtomicSizeInBitsSupported(32);
setMinCmpXchgSizeInBits(32);
setStackPointerRegisterToSaveRestore(CSKY::SP);
const Align FunctionAlignment(2);
setMinFunctionAlignment(FunctionAlignment);
setSchedulingPreference(Sched::Source);
}
Value *CSKYTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
AtomicOrdering Ord) const {
BasicBlock *BB = Builder.GetInsertBlock();
Module *M = BB->getParent()->getParent();
auto *PT = cast<PointerType>(Addr->getType());
Type *Ty = PT->getElementType();
unsigned SZ = Ty->getPrimitiveSizeInBits();
assert((SZ == 32) && "Only 32-bit atomic loads supported");
Function *Fn = Intrinsic::getDeclaration(M, Intrinsic::csky_ldex_w);
PointerType *NewPtrTy =
Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
Addr = Builder.CreateBitCast(Addr, NewPtrTy);
Value *Call = Builder.CreateCall(Fn, Addr, "ldex");
return Builder.CreateBitCast(Call, Ty);
}
/// Perform a store-conditional operation to Addr. Return the status of the
/// store. This should be 0 if the store succeeded, non-zero otherwise.
Value *CSKYTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
Value *Val, Value *Addr,
AtomicOrdering Ord) const {
BasicBlock *BB = Builder.GetInsertBlock();
Module *M = BB->getParent()->getParent();
Type *Ty = Val->getType();
unsigned SZ = Ty->getPrimitiveSizeInBits();
Type *CastTy = Builder.getIntNTy(SZ);
assert((SZ == 32) && "Only 32-bit atomic stores supported");
Function *Fn = Intrinsic::getDeclaration(M, Intrinsic::csky_stex_w);
unsigned AS = Addr->getType()->getPointerAddressSpace();
Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
craig.topperUnsubmitted
Done
ReplyInline Actions

Stray semicolon?

craig.topper: Stray semicolon?
Val = Builder.CreateBitCast(Val, CastTy);
Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stex");
return Builder.CreateSub(Builder.getIntN(SZ, 1), Call);
}
SDValue CSKYTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default:
llvm_unreachable("unimplemented op");
case ISD::GlobalAddress:
return LowerGlobalAddress(Op, DAG);
case ISD::ExternalSymbol:
return LowerExternalSymbol(Op, DAG);
case ISD::ConstantPool:
return LowerConstantPool(Op, DAG);
case ISD::JumpTable:
return LowerJumpTable(Op, DAG);
case ISD::BlockAddress:
return LowerBlockAddress(Op, DAG);
case ISD::ConstantFP:
return LowerConstantFP(Op, DAG);
case ISD::BUILD_VECTOR:
return LowerBUILD_VECTOR(Op, DAG);
}
}
SDValue CSKYTargetLowering::PerformDAGCombine(
SDNode *N, TargetLowering::DAGCombinerInfo &DCI) const {
return SDValue();
}
SDValue CSKYTargetLowering::LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
CSKYMachineFunctionInfo *FuncInfo = MF.getInfo<CSKYMachineFunctionInfo>();
SmallVector<CCValAssign, 16> ArgLocs;
EVT PtrVT = getPointerTy(DAG.getDataLayout());
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
*DAG.getContext());
CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg));
// Calculate the amount of stack space that we need to allocate to store
// byval and varargs.
unsigned ArgRegBegin = CSKY::R4;
for (auto &VA : ArgLocs) {
// Process byVal args.
if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
break;
ISD::ArgFlagsTy Flags = Ins[VA.getValNo()].Flags;
if (!Flags.isByVal())
continue;
assert(VA.isMemLoc() && "Unexpected byval arg in reg.");
unsigned BeginReg, EndReg;
CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), BeginReg,
EndReg);
// Get first byVal reg.
ArgRegBegin = std::min(ArgRegBegin, BeginReg);
CCInfo.nextInRegsParam();
}
CCInfo.rewindByValRegsInfo();
if (IsVarArg && MFI.hasVAStart()) {
unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
if (RegIdx != array_lengthof(GPRArgRegs)) {
ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
}
}
unsigned TotalArgRegsSaveSize = (CSKY::R4 - ArgRegBegin) * 4;
FuncInfo->setArgRegsSaveSize(TotalArgRegsSaveSize);
Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
unsigned CurArgIdx = 0;
int LastInsIndex = -1;
for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
CCValAssign &VA = ArgLocs[I];
craig.topperUnsubmitted
Done
ReplyInline Actions

Is this commented out code needed?

craig.topper: Is this commented out code needed?
EVT ValVT = VA.getValVT();
unsigned ValNo = VA.getValNo();
if (Ins[ValNo].isOrigArg()) {
std::advance(CurOrigArg, Ins[ValNo].getOrigArgIndex() - CurArgIdx);
CurArgIdx = Ins[ValNo].getOrigArgIndex();
}
SDValue ArgValue;
if (VA.isRegLoc()) {
const TargetRegisterClass *RC = nullptr;
EVT RegVT = VA.getLocVT();
switch (RegVT.getSimpleVT().SimpleTy) {
default:
llvm_unreachable("RegVT not supported by FormalArguments Lowering");
break;
case MVT::i32:
RC = &CSKY::GPRRegClass;
break;
case MVT::f32:
RC = Subtarget.hasFPUv2SingleFloat() ? &CSKY::sFPR32RegClass
: &CSKY::FPR32RegClass;
break;
case MVT::f64:
RC = Subtarget.hasFPUv2DoubleFloat() ? &CSKY::sFPR64RegClass
: &CSKY::FPR64RegClass;
break;
case MVT::v2i64:
case MVT::v4i32:
case MVT::v8i16:
case MVT::v16i8:
case MVT::v8f16:
case MVT::v4f32:
case MVT::v2f64:
RC = &CSKY::sFPR128RegClass;
break;
case MVT::v2i16:
case MVT::v4i8:
RC = &CSKY::GPR_DSPRegClass;
break;
}
Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
switch (VA.getLocInfo()) {
default:
llvm_unreachable("Unhandled loc info!");
case CCValAssign::Full:
case CCValAssign::AExt:
case CCValAssign::SExt:
case CCValAssign::ZExt:
break;
case CCValAssign::BCvt:
ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
break;
}
} else {
assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
int Index = VA.getValNo();
// Some Ins[] entries become multiple ArgLoc[] entries.
// Process them only once.
if (Index != LastInsIndex) {
ISD::ArgFlagsTy Flags = Ins[Index].Flags;
if (Flags.isByVal()) {
// Iterate by val args.
unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
// Store byval regs to stack.
int FI = StoreByValRegs(CCInfo, DAG, DL, Chain, &*CurOrigArg,
CurByValIndex, VA.getLocMemOffset(),
Flags.getByValSize());
ArgValue = DAG.getFrameIndex(FI, PtrVT);
CCInfo.nextInRegsParam();
} else {
unsigned ArgOffset = VA.getLocMemOffset();
unsigned ArgSize = ValVT.getSizeInBits() / 8;
int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
ArgValue = DAG.getLoad(ValVT, DL, Chain, FIN,
MachinePointerInfo::getFixedStack(MF, FI));
}
LastInsIndex = Index;
}
}
// Store VarArgs to stack.
if (IsVarArg && MFI.hasVAStart()) {
int FI = StoreByValRegs(
CCInfo, DAG, DL, Chain, nullptr, CCInfo.getInRegsParamsCount(),
CCInfo.getNextStackOffset(), std::max(4U, TotalArgRegsSaveSize));
FuncInfo->setVarArgsFrameIndex(FI);
}
assert(ArgValue);
InVals.push_back(ArgValue);
}
return Chain;
}
bool CSKYTargetLowering::CanLowerReturn(
CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv));
}
SDValue
CSKYTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SDLoc &DL, SelectionDAG &DAG) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
*DAG.getContext());
CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv));
SDValue Glue;
SDValue Flag;
SmallVector<SDValue, 4> RetOps(1, Chain);
for (unsigned I = 0; I < RVLocs.size(); ++I) {
CCValAssign &VA = RVLocs[I];
assert(VA.isRegLoc() && "Can only return in registers!");
SDValue Arg = OutVals[I];
switch (VA.getLocInfo()) {
default:
llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
break;
case CCValAssign::AExt:
Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
break;
case CCValAssign::ZExt:
Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
break;
case CCValAssign::BCvt:
Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
}
craig.topperUnsubmitted
Done
ReplyInline Actions

Is this code needed?

craig.topper: Is this code needed?
Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Glue);
// Guarantee that all emitted copies are stuck together.
Glue = Chain.getValue(1);
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
}
RetOps[0] = Chain; // Update chain.
if (Glue.getNode())
RetOps.push_back(Glue);
return DAG.getNode(CSKYISD::RET, DL, MVT::Other, RetOps);
}
SDValue CSKYTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const {
SelectionDAG &DAG = CLI.DAG;
SDLoc &DL = CLI.DL;
SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
SDValue Chain = CLI.Chain;
SDValue Callee = CLI.Callee;
bool &IsTailCall = CLI.IsTailCall;
CallingConv::ID CallConv = CLI.CallConv;
bool IsVarArg = CLI.IsVarArg;
EVT PtrVT = getPointerTy(DAG.getDataLayout());
MachineFunction &MF = DAG.getMachineFunction();
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, IsVarArg));
unsigned NumBytes = CCInfo.getNextStackOffset();
SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::SP, PtrVT);
if (!IsTailCall)
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
// TODO: handle byval args
// Copy argument values to their designated locations.
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
CCValAssign &VA = ArgLocs[I];
SDValue Arg = OutVals[I];
if (VA.isRegLoc()) {
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
} else {
assert(VA.isMemLoc());
// Create store
SDValue Address =
DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
MemOpChains.push_back(
DAG.getStore(Chain, DL, Arg, Address, MachinePointerInfo()));
}
}
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
SDValue Glue;
for (auto &Reg : RegsToPass) {
Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
Glue = Chain.getValue(1);
}
unsigned Opcode = 0;
if (!IsTailCall)
Opcode = CSKYISD::CALL;
else
Opcode = CSKYISD::JMP;
// The first call operand is the chain and the second is the target address.
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);
// Add argument registers to the end of the list so that they are known live
// into the call.
for (auto &Reg : RegsToPass)
Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
if (!IsTailCall) {
const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
Ops.push_back(DAG.getRegisterMask(Mask));
}
// Glue the call to the argument copies, if any.
if (Glue.getNode())
Ops.push_back(Glue);
// Emit the call.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
Glue = Chain.getValue(1);
craig.topperUnsubmitted
Done
ReplyInline Actions

Is this code needed?

craig.topper: Is this code needed?
if (!IsTailCall)
Chain =
DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, DL, PtrVT, true),
DAG.getConstant(0, DL, PtrVT, true), Glue, DL);
if (!Ins.empty())
Glue = Chain.getValue(1);
// Handle result values, copying them out of physical
// registers into vregs that we return.
return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, DL, DAG, InVals);
}
// Lower the result values of call into the appropriate copies out of
// appropriate physical registers.
SDValue CSKYTargetLowering::LowerCallResult(
SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
SmallVector<CCValAssign, 16> RVLocs;
MachineFunction &MF = DAG.getMachineFunction();
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv));
for (auto &VA : RVLocs) {
// Copy the value out
SDValue RetValue =
DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
// Glue the RetValue to the end of the call sequence
Chain = RetValue.getValue(1);
Glue = RetValue.getValue(2);
switch (VA.getLocInfo()) {
default:
llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
break;
case CCValAssign::BCvt:
RetValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), RetValue);
}
InVals.push_back(RetValue);
}
return Chain;
}
static SDValue getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty,
SelectionDAG &DAG, unsigned Flags, bool UseLrw) {
SDValue Addr = DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
if (!UseLrw)
return Addr;
return DAG.getLoad(
Ty, DL, DAG.getEntryNode(), Addr,
MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
}
static SDValue getTargetNode(ExternalSymbolSDNode *N, SDLoc DL, EVT Ty,
SelectionDAG &DAG, unsigned Flags, bool UseLrw) {
SDValue Addr = DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flags);
if (!UseLrw)
return Addr;
return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Addr, MachinePointerInfo());
}
static SDValue getTargetNode(GlobalAddressSDNode *N, SDLoc DL, EVT Ty,
SelectionDAG &DAG, unsigned Flags, bool UseLrw) {
SDValue Addr =
DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, N->getOffset(), Flags);
if (!UseLrw)
return Addr;
return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Addr,
MachinePointerInfo(N->getGlobal(), N->getOffset()));
}
static SDValue getTargetNode(BlockAddressSDNode *N, SDLoc DL, EVT Ty,
SelectionDAG &DAG, unsigned Flags, bool UseLrw) {
SDValue Addr = DAG.getTargetBlockAddress(N->getBlockAddress(), Ty,
N->getOffset(), Flags);
if (!UseLrw)
return Addr;
return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Addr,
MachinePointerInfo(N->getBlockAddress(), N->getOffset()));
}
static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty,
SelectionDAG &DAG, unsigned Flags, bool UseLrw) {
SDValue Addr;
if (N->isMachineConstantPoolEntry())
Addr = DAG.getTargetConstantPool(N->getMachineCPVal(), Ty, N->getAlign(),
N->getOffset(), Flags);
else
Addr = DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
N->getOffset(), Flags);
if (!UseLrw)
return Addr;
return DAG.getLoad(
Ty, DL, DAG.getEntryNode(), Addr,
MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
}
template <class NodeTy>
SDValue CSKYTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
bool IsLocal) const {
SDLoc DL(N);
EVT Ty = getPointerTy(DAG.getDataLayout());
SDValue Addr;
bool IsPIC = isPositionIndependent();
if (Subtarget.useConstantIslands()) {
Addr = getTargetNode(N, DL, Ty, DAG, 0, true);
} else {
if (IsPIC && getTargetMachine().getCodeModel() == CodeModel::Small) {
Addr = getTargetNode(N, DL, Ty, DAG, CSKYII::MO_GOT12, false);
} else {
unsigned HiFlag =
!IsPIC ? CSKYII::MO_ADDR_HI16
: (IsLocal ? CSKYII::MO_GOTOFF_HI16 : CSKYII::MO_GOT_HI16);
unsigned LoFlag =
!IsPIC ? CSKYII::MO_ADDR_LO16
: (IsLocal ? CSKYII::MO_GOTOFF_LO16 : CSKYII::MO_GOT_LO16);
SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, HiFlag, false);
SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, LoFlag, false);
SDValue MNHi =
SDValue(DAG.getMachineNode(CSKY::MOVIH32, DL, Ty, AddrHi), 0);
Addr = SDValue(DAG.getMachineNode(CSKY::ORI32, DL, Ty, MNHi, AddrLo), 0);
}
}
if (!IsPIC)
return Addr;
SDValue Result =
DAG.getNode(ISD::ADD, DL, Ty, {DAG.getGLOBAL_OFFSET_TABLE(Ty), Addr});
if (IsLocal)
return Result;
bool UseConst = Subtarget.useConstantIslands();
return DAG.getLoad(
Ty, DL, UseConst ? SDValue(Addr.getNode(), 1) : DAG.getEntryNode(),
Result, MachinePointerInfo::getGOT(DAG.getMachineFunction()));
}
SDValue CSKYTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const {
EVT Ty = Op.getValueType();
GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
const GlobalValue *GV = N->getGlobal();
bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
if (Subtarget.useConstantIslands()) {
bool IsPIC = isPositionIndependent();
CSKYConstantPoolValue *CPV = CSKYConstantPoolConstant::Create(
GV, !IsPIC ? CSKYCP::no_modifier
: (IsLocal ? CSKYCP::GOTOFF : CSKYCP::GOT));
return getAddr(cast<ConstantPoolSDNode>(DAG.getConstantPool(CPV, Ty)), DAG,
IsLocal);
}
return getAddr(N, DAG, IsLocal);
}
SDValue CSKYTargetLowering::LowerExternalSymbol(SDValue Op,
SelectionDAG &DAG) const {
EVT Ty = getPointerTy(DAG.getDataLayout());
ExternalSymbolSDNode *N = cast<ExternalSymbolSDNode>(Op);
if (Subtarget.useConstantIslands()) {
MachineFunction &MF = DAG.getMachineFunction();
CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>();
unsigned CSKYPCLabelIndex = CFI->createPICLabelUId();
CSKYConstantPoolValue *CPV = CSKYConstantPoolSymbol::Create(
*DAG.getContext(), N->getSymbol(), CSKYPCLabelIndex, 0);
return getAddr(cast<ConstantPoolSDNode>(DAG.getConstantPool(CPV, Ty)), DAG);
}
return getAddr(N, DAG);
}
SDValue CSKYTargetLowering::LowerBlockAddress(SDValue Op,
SelectionDAG &DAG) const {
EVT Ty = Op.getValueType();
BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
const BlockAddress *BA = N->getBlockAddress();
if (Subtarget.useConstantIslands()) {
bool IsPIC = isPositionIndependent();
CSKYConstantPoolValue *CPV = CSKYConstantPoolConstant::Create(
BA, !IsPIC ? CSKYCP::no_modifier : CSKYCP::GOTOFF);
return getAddr(cast<BlockAddressSDNode>(DAG.getConstantPool(CPV, Ty)), DAG);
}
return getAddr(N, DAG);
}
SDValue CSKYTargetLowering::LowerJumpTable(SDValue Op,
SelectionDAG &DAG) const {
EVT Ty = getPointerTy(DAG.getDataLayout());
JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
if (Subtarget.useConstantIslands()) {
MachineFunction &MF = DAG.getMachineFunction();
CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>();
unsigned CSKYPCLabelIndex = CFI->createPICLabelUId();
CSKYConstantPoolValue *CPV =
CSKYConstantPoolJT::Create(*DAG.getContext(), N->getIndex(),
CSKYPCLabelIndex, 0, CSKYCP::no_modifier);
auto TCP = DAG.getTargetConstantPool(CPV, Ty);
auto JT = DAG.getTargetJumpTable(N->getIndex(), Ty);
return DAG.getNode(CSKYISD::JT_CP_WRAP, SDLoc(N), TCP.getValueType(),
{JT, TCP});
}
return getAddr(N, DAG);
}
SDValue CSKYTargetLowering::LowerConstantPool(SDValue Op,
SelectionDAG &DAG) const {
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
return getAddr(N, DAG);
}
SDValue CSKYTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
auto VT = Op.getValueType();
assert(VT == MVT::v4i8 || VT == MVT::v2i16);
SDLoc Dl(Op);
SDValue Result = DAG.getConstant(0, Dl, MVT::i32);
SDValue Shift = DAG.getConstant(VT.getScalarSizeInBits(), Dl, MVT::i32);
SDValue Mask = DAG.getConstant(
APInt::getMaxValue(VT.getScalarSizeInBits()).zext(32), Dl, MVT::i32);
for (size_t I = 0; I < Op.getNumOperands(); I++) {
auto V = Op.getOperand(Op.getNumOperands() - 1 - I);
if (V.isUndef()) {
;
} else {
auto C = DAG.getNode(ISD::AND, Dl, MVT::i32, {V, Mask});
Result = DAG.getNode(ISD::OR, Dl, MVT::i32, {Result, C});
}
if (I != Op.getNumOperands() - 1)
Result = DAG.getNode(ISD::SHL, Dl, MVT::i32, {Result, Shift});
}
return DAG.getBitcast(VT, Result);
}
SDValue CSKYTargetLowering::LowerConstantFP(SDValue Op,
SelectionDAG &DAG) const {
assert(Op.getValueType() == MVT::f32 || Op.getValueType() == MVT::f64);
EVT VT = Op.getValueType();
SDLoc Dl(Op);
SDValue Tmp = DAG.getConstant(
dyn_cast<ConstantFPSDNode>(Op.getNode())->getValueAPF().bitcastToAPInt(),
Dl, VT == MVT::f32 ? MVT::i32 : MVT::i64);
if (VT == MVT::f32)
return DAG.getNode(CSKYISD::BITCAST, Dl, VT, Tmp);
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Tmp,
DAG.getConstant(0, Dl, MVT::i32));
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Tmp,
DAG.getConstant(1, Dl, MVT::i32));
return DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, Dl, MVT::f64, {Lo, Hi});
}
CCAssignFn *CSKYTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
bool IsVarArg) const {
if (Subtarget.useSoftFloat())
return CC_CSKY_ABIV2_SOFT;
if (Subtarget.hasFPUv2DoubleFloat() || Subtarget.hasFPUv3DoubleFloat())
return CC_CSKY_ABIV2_DF;
if (Subtarget.hasFPUv2SingleFloat() || Subtarget.hasFPUv3SingleFloat())
return CC_CSKY_ABIV2_SF;
return CC_CSKY_ABIV2_SOFT;
}
CCAssignFn *CSKYTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
if (Subtarget.useSoftFloat())
return RetCC_CSKY_ABIV2_SOFT;
if (Subtarget.hasFPUv2DoubleFloat() || Subtarget.hasFPUv3DoubleFloat())
return RetCC_CSKY_ABIV2_DF;
if (Subtarget.hasFPUv2SingleFloat() || Subtarget.hasFPUv3SingleFloat())
return RetCC_CSKY_ABIV2_SF;
return RetCC_CSKY_ABIV2_SOFT;
}
const char *CSKYTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default:
llvm_unreachable("unknown CSKYISD node");
case CSKYISD::RET:
return "CSKYISD::RET";
case CSKYISD::JMP:
return "CSKYISD::JMP";
case CSKYISD::CALL:
return "CSKYISD::CALL";
case CSKYISD::BITCAST:
return "CSKYISD::BITCAST";
case CSKYISD::BITCAST_FROM_LOHI:
return "CSKYISD::BITCAST_FROM_LOHI";
case CSKYISD::BITCAST_TO_LOHI:
return "CSKYISD::BITCAST_TO_LOHI";
case CSKYISD::JT_CP_WRAP:
return "CSKYISD::JT_CP_WRAP";
}
}
EVT CSKYTargetLowering::getSetCCResultType(const DataLayout &DL,
LLVMContext &Context, EVT VT) const {
if (!VT.isVector())
return MVT::i32;
return VT.changeVectorElementTypeToInteger();
}
bool CSKYTargetLowering::useSoftFloat() const {
return Subtarget.useSoftFloat();
}
void CSKYTargetLowering::HandleByVal(CCState *State, unsigned &ByValSize,
Align Align) const {
unsigned Reg = State->AllocateReg(GPRArgRegs);
if (!Reg)
return;
// Maximum available in reg size for byVal args.
unsigned Available = (CSKY::R4 - Reg) * 4;
unsigned ByValRegBegin = Reg;
unsigned ByValRegEnd = std::min<unsigned>(Reg + ByValSize / 4, CSKY::R4);
State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
for (unsigned I = Reg + 1; I != ByValRegEnd; ++I)
State->AllocateReg(GPRArgRegs);
ByValSize = Available >= ByValSize ? 0 : ByValSize - Available;
}
// Allocate stack slots adjacent to arguments passing by caller
// and store unallocated registers there, which reassembles byval
// args and variadic args that were split between registers and memory.
int CSKYTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
const SDLoc &DL, SDValue &Chain,
const Value *OrigArg,
unsigned InRegsParamRecordIdx,
int ArgOffset, unsigned ArgSize) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned BeginReg, EndReg;
if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, BeginReg, EndReg);
} else {
unsigned BeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
BeginReg = BeginIdx == 4 ? (unsigned)CSKY::R4 : GPRArgRegs[BeginIdx];
EndReg = CSKY::R4;
}
if (BeginReg != EndReg)
ArgOffset = -4 * (CSKY::R4 - BeginReg);
EVT PtrVT = getPointerTy(DAG.getDataLayout());
int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SmallVector<SDValue, 4> MemOps;
for (unsigned Reg = BeginReg, I = 0; Reg < EndReg; ++Reg, ++I) {
Register VReg = MF.addLiveIn(Reg, &CSKY::GPRRegClass);
SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i32);
SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
MachinePointerInfo(OrigArg, 4 * I));
MemOps.push_back(Store);
FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(4, DL, PtrVT));
}
if (!MemOps.empty())
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
return FI;
}

llvm/lib/Target/CSKY/CSKYInstrFormats.td

llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td

  • This file was added.
//===- CSKYInstrFormatsF1.td - CSKY Float1.0 Instr Format --*- tablegen -*-===//
//
craig.topperUnsubmitted
Done
ReplyInline Actions

80 columns

craig.topper: 80 columns
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// CSKY Instruction Format Float1.0 Definitions.
//
//===----------------------------------------------------------------------===//
class CSKYFP1Inst<dag outs, dag ins, string asmstr, list<dag> pattern>
: CSKY32Inst<AddrModeNone, 0x3d, outs, ins, asmstr, pattern>, Requires<[HasFPUv2_SF]> {
}
class F_XYZ_BASE<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> pattern>
: CSKYFP1Inst<outs, ins, opcodestr, pattern> {
bits<4> vrx;
bits<4> vry;
bits<4> vrz;
let Inst{25 - 21} = {0, vry};
let Inst{20 - 16} = {0, vrx};
let Inst{15 - 11} = datatype;
let Inst{10 - 5} = sop;
let Inst{4 - 0} = {0, vrz};
}
class F_XZ_GF<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> pattern>
: CSKYFP1Inst<outs, ins, opcodestr, pattern> {
bits<4> vrx;
bits<5> rz;
let Inst{25 - 21} = 0;
let Inst{20 - 16} = {0, vrx};
let Inst{15 - 11} = datatype;
let Inst{10 - 5} = sop;
let Inst{4 - 0} = {rz};
}
class F_XZ_FG<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> pattern>
: CSKYFP1Inst<outs, ins, opcodestr, pattern> {
bits<5> rx;
bits<4> vrz;
let Inst{25 - 21} = 0;
let Inst{20 - 16} = {rx};
let Inst{15 - 11} = datatype;
let Inst{10 - 5} = sop;
let Inst{4 - 0} = {0, vrz};
}
class F_XZ_TRANS_FROM<bits<6> sop, string op, RegisterClass regtype1, RegisterClass regtype2>
: F_XZ_GF<3, sop, (outs regtype1:$rz), (ins regtype2:$vrx), !strconcat(op, "\t$rz, $vrx"),
[]>;
class F_XZ_TRANS_TO<bits<6> sop, string op, RegisterClass regtype1, RegisterClass regtype2>
: F_XZ_FG<3, sop, (outs regtype1:$vrz), (ins regtype2:$rx), !strconcat(op, "\t$vrz, $rx"),
[]>;
let vry = 0 in {
class F_XZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterClass regtype>
: F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrz, $vrx"),
[(set regtype:$vrz, (opnode regtype:$vrx))]>;
class F_MOV<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterClass regtype>
: F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrz, $vrx"),
[]>;
class F_XZ_TRANS<bits<6> sop, string op, RegisterClass regtype1, RegisterClass regtype2>
: F_XYZ_BASE<3, sop, (outs regtype1:$vrz), (ins regtype2:$vrx), !strconcat(op, "\t$vrz, $vrx"),
[]>;
class F_XZ_TRANS_DS<bits<6> sop, string op, PatFrag opnode>
: F_XYZ_BASE<3, sop, (outs sFPR32:$vrz), (ins sFPR64:$vrx), !strconcat(op, "\t$vrz, $vrx"),
[(set sFPR32:$vrz, (opnode sFPR64:$vrx))]>;
class F_XZ_TRANS_SD<bits<6> sop, string op, PatFrag opnode>
: F_XYZ_BASE<3, sop, (outs sFPR64:$vrz), (ins sFPR32:$vrx), !strconcat(op, "\t$vrz, $vrx"),
[(set sFPR64:$vrz, (opnode sFPR32:$vrx))]>;
}
multiclass FT_MOV<bits<6> sop, string op> {
def _S : F_MOV<0, sop, op, "s", sFPR32>;
let Predicates = [HasFPUv2_DF] in
def _D : F_MOV<1, sop, op, "d", sFPR64>;
}
multiclass FT_XZ<bits<6> sop, string op, PatFrag opnode> {
def _S : F_XZ<0, sop, op, "s", opnode, sFPR32>;
let Predicates = [HasFPUv2_DF] in
def _D : F_XZ<1, sop, op, "d", opnode, sFPR64>;
}
let vrz = 0, isCompare = 1 in {
class F_CMPXY<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterClass regtype>
: F_XYZ_BASE<datatype, sop, (outs CARRY:$ca), (ins regtype:$vrx, regtype:$vry), !strconcat(op#op_su, "\t$vrx, $vry"),
[]>;
let vry = 0 in{
class F_CMPZX<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterClass regtype>
: F_XYZ_BASE<datatype, sop, (outs CARRY:$ca), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrx"),
[]>;
}
}
class F_XYZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterClass regtype>
: F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrx, regtype:$vry),
!strconcat(op#op_su, "\t$vrz, $vrx, $vry"),
[(set regtype:$vrz, (opnode regtype:$vrx, regtype:$vry))]>;
multiclass FT_XYZ<bits<6> sop, string op, PatFrag opnode> {
def _S : F_XYZ<0, sop, op, "s", opnode, sFPR32>;
let Predicates = [HasFPUv2_DF] in
def _D : F_XYZ<1, sop, op, "d", opnode, sFPR64>;
}
let Constraints = "$vrt = $vrz" in {
class F_ACCUM_XYZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterClass regtype>
: F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrt, regtype:$vrx, regtype:$vry),
!strconcat(op#op_su, "\t$vrz, $vrx, $vry"),
[(set regtype:$vrz, (opnode regtype:$vrt, regtype:$vrx, regtype:$vry))]>;
}
multiclass FT_ACCUM_XYZ<bits<6> sop, string op, PatFrag opnode> {
def _S : F_ACCUM_XYZ<0, sop, op, "s", opnode, sFPR32>;
let Predicates = [HasFPUv2_DF] in
def _D : F_ACCUM_XYZ<1, sop, op, "d", opnode, sFPR64>;
}
multiclass FT_CMPXY<bits<6> sop, string op> {
def _S : F_CMPXY<0, sop, op, "s", sFPR32>;
let Predicates = [HasFPUv2_DF] in
def _D : F_CMPXY<1, sop, op, "d", sFPR64>;
}
multiclass FT_CMPZX<bits<6> sop, string op> {
def _S : F_CMPZX<0, sop, op, "s", sFPR32>;
let Predicates = [HasFPUv2_DF] in
def _D : F_CMPZX<1, sop, op, "d", sFPR64>;
}
class F_I8_XY_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, list<dag> pattern>
: CSKY32Inst<AddrMode32SDF, 0x3d, outs, ins, opcodestr, pattern> {
bits<5> rx;
bits<4> vrz;
bits<8> imm8;
let Inst{25} = 0;
let Inst{24 - 21} = imm8{7 - 4}; //imm4h
let Inst{20 - 16} = rx; //rx
let Inst{15 - 9} = sop;
let Inst{8} = sop_su;
let Inst{7 - 4} = imm8{3 - 0}; // imm4l
let Inst{3 - 0} = vrz;
}
class F_XYZ_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, bits<2> shift, list<dag> pattern>
: CSKY32Inst<AddrModeNone, 0x3d, outs, ins, opcodestr, pattern> {
bits<2> shift;
bits<5> rx;
bits<5> ry;
bits<4> vrz;
let Inst{25 - 21} = ry; // ry;
let Inst{20 - 16} = rx; // rx;
let Inst{15 - 9} = sop;
let Inst{8} = sop_su;
let Inst{7} = 0;
let Inst{6,5} = shift; // shift;
let Inst{4} = 0;
let Inst{3 - 0} = vrz;
}
class F_XYAI_LD<bits<7> sop, bits<1> sop_su, string op, string op_su,
RegisterClass regtype, Operand operand>
: F_I8_XY_MEM<sop, sop_su, (outs regtype:$vrz), (ins GPR:$rx, operand:$imm8),
!strconcat(op#op_su, "\t$vrz, ($rx, $imm8)"), []>;
class F_XYAR_LD<bits<7> sop, bits<1> sop_su, string op, string op_su,
RegisterClass regtype, bits<2> shift>
: F_XYZ_MEM<sop, sop_su, (outs regtype:$vrz), (ins GPR:$rx, GPR:$ry),
op#op_su#"\t$vrz, $rx, ($ry << "#!cast<int>(shift)#")", shift, []>;
class F_XYAI_ST<bits<7> sop, bits<1> sop_su, string op, string op_su,
RegisterClass regtype, Operand operand>
: F_I8_XY_MEM<sop, sop_su, (outs), (ins regtype:$vrz, GPR:$rx, operand:$imm8),
!strconcat(op#op_su, "\t$vrz, ($rx, $imm8)"), []>;
class F_XYAR_ST<bits<7> sop, bits<1> sop_su, string op, string op_su,
RegisterClass regtype, bits<2> shift>
: F_XYZ_MEM<sop, sop_su, (outs), (ins regtype:$vrz, GPR:$rx, GPR:$ry),
op#op_su#"\t$vrz, $rx, ($ry << "#!cast<int>(shift)#")", shift, []>;
def Mem8SL2 : Operand<iPTR>, ComplexPattern<iPTR, 2, "SelectAddrRegImm8", []> {
let MIOperandInfo = (ops GPR, i32imm);
let PrintMethod = "printAddrModeRegImmOperand";
let EncoderMethod = "getAddrModeFloatImm8_sl2OpValue";
}
def FRRS : Operand<iPTR>, ComplexPattern<iPTR, 3, "SelectAddrRegReg", []> {
let MIOperandInfo = (ops GPR, GPR, i32imm);
let PrintMethod = "printAddrModeRegRegSLOperand";
let EncoderMethod = "getAddrModeFloatRegRegSLOpValue";
}
multiclass FT_XYAI_LD<bits<7> sop, string op> {
def _S : F_XYAI_LD<sop, 0, op, "s", sFPR32, uimm8_2>;
let Predicates = [HasFPUv2_DF] in
def _D : F_XYAI_LD<sop, 1, op, "d", sFPR64, uimm8_2>;
}
multiclass FT_XYAR_LD<bits<7> sop, string op, bits<2> shift> {
def _S#!cast<int>(shift) : F_XYAR_LD<sop, 0, op, "s", sFPR32, shift>;
let Predicates = [HasFPUv2_DF] in
def _D#!cast<int>(shift) : F_XYAR_LD<sop, 1, op, "d", sFPR64, shift>;
}
multiclass FT_XYAI_ST<bits<7> sop, string op> {
def _S : F_XYAI_ST<sop, 0, op, "s", sFPR32, uimm8_2>;
let Predicates = [HasFPUv2_DF] in
def _D : F_XYAI_ST<sop, 1, op, "d", sFPR64, uimm8_2>;
}
multiclass FT_XYAR_ST<bits<7> sop, string op, bits<2> shift> {
def _S#!cast<int>(shift) : F_XYAR_ST<sop, 0, op, "s", sFPR32, shift>;
let Predicates = [HasFPUv2_DF] in
def _D#!cast<int>(shift) : F_XYAR_ST<sop, 1, op, "d", sFPR64, shift>;
}

llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td

llvm/lib/Target/CSKY/CSKYInstrInfo.h

llvm/lib/Target/CSKY/CSKYInstrInfo.cpp

  • This file was added.
//===-- CSKYInstrInfo.h - CSKY Instruction Information --------*- C++ -*---===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the CSKY implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#include "CSKYInstrInfo.h"
#include "CSKYConstantPoolValue.h"
#include "CSKYMachineFunctionInfo.h"
#include "CSKYTargetMachine.h"
using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "CSKYGenInstrInfo.inc"
CSKYInstrInfo::CSKYInstrInfo(CSKYSubtarget &STI)
: CSKYGenInstrInfo(CSKY::ADJCALLSTACKDOWN, CSKY::ADJCALLSTACKUP), STI(STI) {
v2sf = STI.hasFPUv2SingleFloat();
v2df = STI.hasFPUv2DoubleFloat();
v3sf = STI.hasFPUv3SingleFloat();
v3df = STI.hasFPUv3DoubleFloat();
}
void CSKYInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register SrcReg, bool IsKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
DebugLoc DL;
if (I != MBB.end())
DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
CSKYMachineFunctionInfo *MFI = MF.getInfo<CSKYMachineFunctionInfo>();
if (CSKY::GPRRegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::ST32W))
.addReg(SrcReg, getKillRegState(IsKill))
.addFrameIndex(FI)
.addImm(0);
return;
} else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::FST_S))
.addReg(SrcReg, getKillRegState(IsKill))
.addFrameIndex(FI)
.addImm(0);
return;
} else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::FST_D))
.addReg(SrcReg, getKillRegState(IsKill))
.addFrameIndex(FI)
.addImm(0);
return;
} else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::f2FST_S))
.addReg(SrcReg, getKillRegState(IsKill))
.addFrameIndex(FI)
.addImm(0);
return;
} else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::f2FST_D))
.addReg(SrcReg, getKillRegState(IsKill))
.addFrameIndex(FI)
.addImm(0);
return;
} else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::SPILL_CARRY))
.addReg(SrcReg, getKillRegState(IsKill))
.addFrameIndex(FI)
.addImm(0);
MFI->setSpillsCR();
return;
} else if (CSKY::GPRPairRegClass.hasSubClassEq(RC)) {
auto NewReg = MRI.createVirtualRegister(&CSKY::GPRRegClass);
BuildMI(MBB, I, DL, get(CSKY::ADDI32), NewReg).addFrameIndex(FI).addImm(0);
arsenmUnsubmitted
Done
ReplyInline Actions

Grammatically weird error throughout

arsenm: Grammatically weird error throughout
BuildMI(MBB, I, DL, get(CSKY::STM32_2))
.addReg(SrcReg, getKillRegState(IsKill))
.addReg(NewReg, getKillRegState(true));
return;
}
llvm_unreachable("Unknown RegisterClass");
}
void CSKYInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register DestReg, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
DebugLoc DL;
if (I != MBB.end())
DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
CSKYMachineFunctionInfo *MFI = MF.getInfo<CSKYMachineFunctionInfo>();
if (CSKY::GPRRegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::LD32W), DestReg).addFrameIndex(FI).addImm(0);
return;
} else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::FLD_S), DestReg).addFrameIndex(FI).addImm(0);
return;
} else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::FLD_D), DestReg).addFrameIndex(FI).addImm(0);
return;
} else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::f2FLD_S), DestReg)
.addFrameIndex(FI)
.addImm(0);
return;
} else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::f2FLD_D), DestReg)
.addFrameIndex(FI)
.addImm(0);
return;
} else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) {
BuildMI(MBB, I, DL, get(CSKY::RESTORE_CARRY), DestReg)
.addFrameIndex(FI)
.addImm(0);
MFI->setSpillsCR();
return;
} else if (CSKY::GPRPairRegClass.hasSubClassEq(RC)) {
auto NewReg = MRI.createVirtualRegister(&CSKY::GPRRegClass);
BuildMI(MBB, I, DL, get(CSKY::ADDI32), NewReg).addFrameIndex(FI).addImm(0);
BuildMI(MBB, I, DL, get(CSKY::LDM32_2), DestReg)
.addReg(NewReg, getKillRegState(true));
return;
}
llvm_unreachable("Unknown RegisterClass");
}
void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
unsigned Opcode = 0;
if (CSKY::GPRRegClass.contains(DestReg, SrcReg)) {
Opcode = CSKY::MOV32;
} else if (v2sf && CSKY::sFPR32RegClass.contains(DestReg, SrcReg)) {
Opcode = CSKY::FMOV_S;
} else if (v3sf && CSKY::FPR32RegClass.contains(DestReg, SrcReg)) {
Opcode = CSKY::f2FMOV_S;
} else if (v2df && CSKY::sFPR64RegClass.contains(DestReg, SrcReg)) {
Opcode = CSKY::FMOV_D;
} else if (v3df && CSKY::FPR64RegClass.contains(DestReg, SrcReg)) {
Opcode = CSKY::f2FMOV_D;
} else if (v2sf && CSKY::sFPR32RegClass.contains(SrcReg) &&
CSKY::GPRRegClass.contains(DestReg)) {
Opcode = CSKY::FMFVRL;
} else if (v3sf && CSKY::FPR32RegClass.contains(SrcReg) &&
CSKY::GPRRegClass.contains(DestReg)) {
Opcode = CSKY::f2FMFVRL;
} else if (v2df && CSKY::sFPR64RegClass.contains(SrcReg) &&
CSKY::GPRRegClass.contains(DestReg)) {
Opcode = CSKY::FMFVRL_D;
} else if (v3df && CSKY::FPR64RegClass.contains(SrcReg) &&
CSKY::GPRRegClass.contains(DestReg)) {
Opcode = CSKY::f2FMFVRL_D;
} else if (v2sf && CSKY::GPRRegClass.contains(SrcReg) &&
CSKY::sFPR32RegClass.contains(DestReg)) {
Opcode = CSKY::FMTVRL;
} else if (v3sf && CSKY::GPRRegClass.contains(SrcReg) &&
CSKY::FPR32RegClass.contains(DestReg)) {
Opcode = CSKY::f2FMTVRL;
} else if (v2df && CSKY::GPRRegClass.contains(SrcReg) &&
CSKY::sFPR64RegClass.contains(DestReg)) {
Opcode = CSKY::FMTVRL_D;
} else if (v3df && CSKY::GPRRegClass.contains(SrcReg) &&
CSKY::FPR64RegClass.contains(DestReg)) {
Opcode = CSKY::f2FMTVRL_D;
} else if (CSKY::GPRRegClass.contains(SrcReg) &&
CSKY::CARRYRegClass.contains(DestReg)) {
Opcode = CSKY::BTSTI32;
} else if (CSKY::CARRYRegClass.contains(SrcReg) &&
CSKY::GPRRegClass.contains(DestReg)) {
Opcode = CSKY::MVC32;
} else {
llvm_unreachable("Unknown RegisterClass");
}
if (Opcode == CSKY::BTSTI32) {
BuildMI(MBB, I, DL, get(Opcode))
.addReg(DestReg, RegState::Define)
.addReg(SrcReg, getKillRegState(KillSrc))
.addImm(0);
} else {
BuildMI(MBB, I, DL, get(Opcode))
.addReg(DestReg, RegState::Define)
.addReg(SrcReg, getKillRegState(KillSrc));
}
}
static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
SmallVectorImpl<MachineOperand> &Cond) {
// Block ends with fall-through condbranch.
assert(LastInst.getDesc().isConditionalBranch() &&
"Unknown conditional branch");
Target = LastInst.getOperand(1).getMBB();
Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
Cond.push_back(LastInst.getOperand(0));
}
bool CSKYInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const {
TBB = FBB = nullptr;
Cond.clear();
// If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
if (I == MBB.end() || !isUnpredicatedTerminator(*I))
return false;
// Count the number of terminators and find the first unconditional or
// indirect branch.
MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
int NumTerminators = 0;
for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
J++) {
NumTerminators++;
if (J->getDesc().isUnconditionalBranch() ||
J->getDesc().isIndirectBranch()) {
FirstUncondOrIndirectBr = J.getReverse();
}
}
// If AllowModify is true, we can erase any terminators after
// FirstUncondOrIndirectBR.
if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
std::next(FirstUncondOrIndirectBr)->eraseFromParent();
NumTerminators--;
}
I = FirstUncondOrIndirectBr;
}
// We can't handle blocks that end in an indirect branch.
if (I->getDesc().isIndirectBranch())
return true;
// We can't handle blocks with more than 2 terminators.
if (NumTerminators > 2)
return true;
// Handle a single unconditional branch.
if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
TBB = getBranchDestBlock(*I);
return false;
}
// Handle a single conditional branch.
if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
parseCondBranch(*I, TBB, Cond);
return false;
}
// Handle a conditional branch followed by an unconditional branch.
if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
I->getDesc().isUnconditionalBranch()) {
parseCondBranch(*std::prev(I), TBB, Cond);
FBB = getBranchDestBlock(*I);
return false;
}
// Otherwise, we can't handle this.
return true;
}
unsigned CSKYInstrInfo::insertBranch(
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
if (BytesAdded)
*BytesAdded = 0;
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
"CSKY branch conditions have two components!");
// Unconditional branch.
if (Cond.empty()) {
MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
return 1;
}
// Either a one or two-way conditional branch.
unsigned Opc = Cond[0].getImm();
MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).addMBB(TBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(CondMI);
// One-way conditional branch.
if (!FBB)
return 1;
// Two-way conditional branch.
MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(FBB);
if (BytesAdded)
*BytesAdded += getInstSizeInBytes(MI);
return 2;
}
bool CSKYInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
auto &MBB = *MI.getParent();
auto DL = MI.getDebugLoc();
MachineFunction *MF = MBB.getParent();
CSKYMachineFunctionInfo *CFI = MF->getInfo<CSKYMachineFunctionInfo>();
MachineConstantPool *MCP = MF->getConstantPool();
switch (MI.getOpcode()) {
case CSKY::GETGOT32: {
CSKYConstantPoolValue *CPV = CSKYConstantPoolSymbol::Create(
MF->getFunction().getContext(), "_GLOBAL_OFFSET_TABLE_",
CFI->createPICLabelUId(), 0);
unsigned CPI = MCP->getConstantPoolIndex(CPV, Align(4));
MachineMemOperand *MO =
MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
MachineMemOperand::MOLoad, 4, Align(4));
BuildMI(MBB, MI, DL, get(CSKY::LRW32), MI.getOperand(0).getReg())
.addConstantPoolIndex(CPI)
.addMemOperand(MO);
MBB.erase(MI);
return true;
}
}
return false;
}
// This function is only used by BranchRelaxation.
// Since we need to reserve constant pool for each branch instruction,
// there is no need to do branch relaxation before constant island pass.
unsigned int CSKYInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
MachineBasicBlock &NewDestBB,
const DebugLoc &DL,
int64_t BrOffset,
RegScavenger *RS) const {
assert(MBB.empty() &&
"new block should be inserted for expanding unconditional branch");
assert(MBB.pred_size() == 1);
MachineFunction *MF = MBB.getParent();
CSKYMachineFunctionInfo *CFI = MF->getInfo<CSKYMachineFunctionInfo>();
MachineConstantPool *MCP = MF->getConstantPool();
unsigned PCLabelID = CFI->createPICLabelUId();
CSKYConstantPoolValue *CPV = CSKYConstantPoolMBB::Create(
MF->getFunction().getContext(), &NewDestBB, PCLabelID, 0);
unsigned CPI = MCP->getConstantPoolIndex(CPV, Align(4));
/*
jmpi [(cp - pc) >> 2]
cp: (DestBB)
*/
BuildMI(&MBB, DL, get(CSKY::JMPI32)).addConstantPoolIndex(CPI);
return 4;
}
unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {
if (BytesRemoved)
*BytesRemoved = 0;
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
if (I == MBB.end())
return 0;
if (!I->getDesc().isUnconditionalBranch() &&
!I->getDesc().isConditionalBranch())
return 0;
// Remove the branch.
if (BytesRemoved)
*BytesRemoved += getInstSizeInBytes(*I);
I->eraseFromParent();
I = MBB.end();
if (I == MBB.begin())
return 1;
--I;
if (!I->getDesc().isConditionalBranch())
return 1;
// Remove the branch.
if (BytesRemoved)
*BytesRemoved += getInstSizeInBytes(*I);
I->eraseFromParent();
return 2;
}
MachineBasicBlock *
CSKYInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
assert(MI.getDesc().isBranch() && "Unexpected opcode!");
// The branch target is always the last operand.
int NumOp = MI.getNumExplicitOperands();
assert(MI.getOperand(NumOp - 1).isMBB() && "Expected MBB!");
return MI.getOperand(NumOp - 1).getMBB();
}
bool CSKYInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
int64_t BrOffset) const {
switch (BranchOp) {
default:
llvm_unreachable("Unexpected opcode!");
case CSKY::BR32:
case CSKY::BT32:
case CSKY::BF32:
case CSKY::BHZ32:
case CSKY::BHSZ32:
case CSKY::BLZ32:
case CSKY::BLSZ32:
case CSKY::BNEZ32:
case CSKY::BEZ32:
return isIntN(16, BrOffset / 2);
}
}
static unsigned getOppositeBranchOpc(unsigned Opcode) {
switch (Opcode) {
default:
llvm_unreachable("Unknown conditional branch!");
case CSKY::BT32:
return CSKY::BF32;
case CSKY::BF32:
return CSKY::BT32;
case CSKY::BHZ32:
return CSKY::BLSZ32;
case CSKY::BHSZ32:
return CSKY::BLZ32;
case CSKY::BLZ32:
return CSKY::BHSZ32;
case CSKY::BLSZ32:
return CSKY::BHZ32;
case CSKY::BNEZ32:
return CSKY::BEZ32;
case CSKY::BEZ32:
return CSKY::BNEZ32;
}
}
bool CSKYInstrInfo::reverseBranchCondition(
SmallVectorImpl<MachineOperand> &Cond) const {
assert((Cond.size() == 2) && "Invalid branch condition!");
Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
return false;
}
Register CSKYInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
CSKYMachineFunctionInfo *MFI = MF->getInfo<CSKYMachineFunctionInfo>();
Register GlobalBaseReg = MFI->getGlobalBaseReg();
if (GlobalBaseReg != 0)
return GlobalBaseReg;
// We use r28 as a global base register
GlobalBaseReg = CSKY::GP;
// Insert a pseudo instruction to set the GlobalBaseReg into the first
// MBB of the function
MachineBasicBlock &FirstMBB = MF->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
DebugLoc Dl;
BuildMI(FirstMBB, MBBI, Dl, get(CSKY::GETGOT32), GlobalBaseReg);
MFI->setGlobalBaseReg(GlobalBaseReg);
return GlobalBaseReg;
}
unsigned CSKYInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
return MI.getDesc().getSize();
case CSKY::CONSTPOOL_ENTRY:
return MI.getOperand(2).getImm();
case TargetOpcode::INLINEASM: {
const MachineFunction *MF = MI.getParent()->getParent();
const char *AsmStr = MI.getOperand(0).getSymbolName();
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
}
}
}

llvm/lib/Target/CSKY/CSKYInstrInfo.td

llvm/lib/Target/CSKY/CSKYInstrInfoF1.td

  • This file was added.
//===- CSKYInstrInfoF1.td - CSKY Instruction Float1.0 ------*- tablegen -*-===//
//
craig.topperUnsubmitted
Done
ReplyInline Actions

Pad to 80 columns

craig.topper: Pad to 80 columns
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the CSKY instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
include "CSKYInstrFormatsF1.td"
def bitcast_fpimm_to_i32l16 : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant(
N->getValueAPF().bitcastToAPInt().getZExtValue() & 0xFFFFUL,
SDLoc(N), MVT::i32);
}]>;
def bitcast_fpimm_to_i32h16 : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant(
N->getValueAPF().bitcastToAPInt().getZExtValue() & 0xFFFF0000UL,
SDLoc(N), MVT::i32);
}]>;
def bitcast_fpimm_to_i64_hi32l16 : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant(
(N->getValueAPF().bitcastToAPInt().getZExtValue() >> 32) & 0xFFFFUL,
SDLoc(N), MVT::i32);
}]>;
def bitcast_fpimm_to_i64_hi32h16 : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant(
(N->getValueAPF().bitcastToAPInt().getZExtValue() >> 32) & 0xFFFF0000UL,
SDLoc(N), MVT::i32);
}]>;
def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
//arithmetic
defm FABS : FT_XZ<0b000110, "fabs", UnOpFrag<(fabs node:$Src)>>;
defm FNEG : FT_XZ<0b000111, "fneg", UnOpFrag<(fneg node:$Src)>>;
defm FSQRT : FT_XZ<0b011010, "fsqrt", UnOpFrag<(fsqrt node:$Src)>>;
defm FADD : FT_XYZ<0b000000, "fadd", BinOpFrag<(fadd node:$LHS, node:$RHS)>>;
defm FSUB : FT_XYZ<0b000001, "fsub", BinOpFrag<(fsub node:$LHS, node:$RHS)>>;
defm FDIV : FT_XYZ<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;
defm FMUL : FT_XYZ<0b010000, "fmul", BinOpFrag<(fmul node:$LHS, node:$RHS)>>;
defm FNMUL : FT_XYZ<0b010001, "fnmul", BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>>;
defm FMAC : FT_ACCUM_XYZ<0b010100, "fmac", TriOpFrag<(fadd node:$LHS, (fmul node:$MHS, node:$RHS))>>;
defm FMSC : FT_ACCUM_XYZ<0b010101, "fmsc", TriOpFrag<(fsub (fmul node:$MHS, node:$RHS), node:$LHS)>>;
defm FNMAC : FT_ACCUM_XYZ<0b010110, "fnmac", TriOpFrag<(fsub node:$LHS, (fmul node:$MHS, node:$RHS))>>;
defm FNMSC : FT_ACCUM_XYZ<0b010111, "fnmsc", TriOpFrag<(fneg (fadd node:$LHS, (fmul node:$MHS, node:$RHS)))>>;
defm FCMPHS : FT_CMPXY<0b001100, "fcmphs">;
defm FCMPLT : FT_CMPXY<0b001101, "fcmplt">;
defm FCMPNE : FT_CMPXY<0b001110, "fcmpne">;
defm FCMPUO : FT_CMPXY<0b001111, "fcmpuo">;
defm FCMPZHS : FT_CMPZX<0b001000, "fcmpzhs">;
defm FCMPZLS : FT_CMPZX<0b001001, "fcmpzls">;
defm FCMPZNE : FT_CMPZX<0b001010, "fcmpzne">;
defm FCMPZUO : FT_CMPZX<0b001011, "fcmpzuo">;
//fmov, fmtvr, fmfvr
defm FMOV : FT_MOV<0b000100, "fmov">;
def FMFVRL : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR32:$vrx),
"fmfvrl\t$rz, $vrx", [(set GPR:$rz, (bitconvert sFPR32:$vrx))]>;
def FMTVRL : F_XZ_FG<3, 0b011011, (outs sFPR32:$vrz), (ins GPR:$rx),
"fmtvrl\t$vrz, $rx", [(set sFPR32:$vrz, (bitconvert GPR:$rx))]>;
let Predicates = [HasFPUv2_DF] in {
def FMFVRL_D : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR64:$vrx),
"fmfvrl\t$rz, $vrx", []>;
def FMFVRH_D : F_XZ_GF<3, 0b011000, (outs GPR:$rz), (ins sFPR64:$vrx),
"fmfvrh\t$rz, $vrx", []>;
def FMTVRL_D : F_XZ_FG<3, 0b011011, (outs sFPR64:$vrz), (ins GPR:$rx),
"fmtvrl\t$vrz, $rx", []>;
let Constraints = "$vrZ = $vrz" in
def FMTVRH_D : F_XZ_FG<3, 0b011010, (outs sFPR64:$vrz), (ins sFPR64:$vrZ, GPR:$rx),
"fmtvrh\t$vrz, $rx", []>;
}
//fcvt
def FSITOS : F_XZ_TRANS<0b010000, "fsitos", sFPR32, sFPR32>;
def : Pat<(f32 (sint_to_fp GPR:$a)),
(FSITOS (COPY_TO_REGCLASS GPR:$a, sFPR32))>,
Requires<[HasFPUv2_SF]>;
def FUITOS : F_XZ_TRANS<0b010001, "fuitos", sFPR32, sFPR32>;
def : Pat<(f32 (uint_to_fp GPR:$a)),
(FUITOS (COPY_TO_REGCLASS GPR:$a, sFPR32))>,
Requires<[HasFPUv2_SF]>;
def FSITOD : F_XZ_TRANS<0b010100, "fsitod", sFPR64, sFPR64>;
def : Pat<(f64 (sint_to_fp GPR:$a)),
(FSITOD (COPY_TO_REGCLASS GPR:$a, sFPR64))>,
Requires<[HasFPUv2_DF]>;
def FUITOD : F_XZ_TRANS<0b010101, "fuitod", sFPR64, sFPR64>;
def : Pat<(f64 (uint_to_fp GPR:$a)),
(FUITOD (COPY_TO_REGCLASS GPR:$a, sFPR64))>,
Requires<[HasFPUv2_DF]>;
let Predicates = [HasFPUv2_DF] in {
def FDTOS : F_XZ_TRANS_DS<0b010110,"fdtos", UnOpFrag<(fpround node:$Src)>>;
def FSTOD : F_XZ_TRANS_SD<0b010111,"fstod", UnOpFrag<(fpextend node:$Src)>>;
}
def rpiFSTOSI : F_XZ_TRANS<0b000010, "fstosi.rpi", sFPR32, sFPR32>;
def rpiFSTOUI : F_XZ_TRANS<0b000110, "fstoui.rpi", sFPR32, sFPR32>;
def rzFSTOSI : F_XZ_TRANS<0b000001, "fstosi.rz", sFPR32, sFPR32>;
def rzFSTOUI : F_XZ_TRANS<0b000101, "fstoui.rz", sFPR32, sFPR32>;
def rnFSTOSI : F_XZ_TRANS<0b000000, "fstosi.rn", sFPR32, sFPR32>;
def rnFSTOUI : F_XZ_TRANS<0b000100, "fstoui.rn", sFPR32, sFPR32>;
def rniFSTOSI : F_XZ_TRANS<0b000011, "fstosi.rni", sFPR32, sFPR32>;
def rniFSTOUI : F_XZ_TRANS<0b000111, "fstoui.rni", sFPR32, sFPR32>;
let Predicates = [HasFPUv2_DF] in {
def rpiFDTOSI : F_XZ_TRANS<0b001010, "fdtosi.rpi", sFPR64, sFPR64>;
def rpiFDTOUI : F_XZ_TRANS<0b001110, "fdtoui.rpi", sFPR64, sFPR64>;
def rzFDTOSI : F_XZ_TRANS<0b001001, "fdtosi.rz", sFPR64, sFPR64>;
def rzFDTOUI : F_XZ_TRANS<0b001101, "fdtoui.rz", sFPR64, sFPR64>;
def rnFDTOSI : F_XZ_TRANS<0b001000, "fdtosi.rn", sFPR64, sFPR64>;
def rnFDTOUI : F_XZ_TRANS<0b001100, "fdtoui.rn", sFPR64, sFPR64>;
def rniFDTOSI : F_XZ_TRANS<0b001011, "fdtosi.rni", sFPR64, sFPR64>;
def rniFDTOUI : F_XZ_TRANS<0b001111, "fdtoui.rni", sFPR64, sFPR64>;
}
multiclass FPToIntegerPats<SDNode round, string SUFFIX> {
def : Pat<(i32 (fp_to_sint (round sFPR32:$Rn))),
(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32:$Rn), GPR)>,
Requires<[HasFPUv2_SF]>;
def : Pat<(i32 (fp_to_uint (round sFPR32:$Rn))),
(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32:$Rn), GPR)>,
Requires<[HasFPUv2_SF]>;
def : Pat<(i32 (fp_to_sint (round sFPR64:$Rn))),
(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64:$Rn), GPR)>,
Requires<[HasFPUv2_DF]>;
def : Pat<(i32 (fp_to_uint (round sFPR64:$Rn))),
(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOUI) sFPR64:$Rn), GPR)>,
Requires<[HasFPUv2_DF]>;
}
defm: FPToIntegerPats<fceil, "rpi">;
defm: FPToIntegerPats<fround, "rn">;
defm: FPToIntegerPats<ffloor, "rni">;
multiclass FPToIntegerTowardszeroPats<string SUFFIX> {
def : Pat<(i32 (fp_to_sint sFPR32:$Rn)),
(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32:$Rn), GPR)>,
Requires<[HasFPUv2_SF]>;
def : Pat<(i32 (fp_to_uint sFPR32:$Rn)),
(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32:$Rn), GPR)>,
Requires<[HasFPUv2_SF]>;
def : Pat<(i32 (fp_to_sint sFPR64:$Rn)),
(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64:$Rn), GPR)>,
Requires<[HasFPUv2_DF]>;
def : Pat<(i32 (fp_to_uint sFPR64:$Rn)),
(COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOUI) sFPR64:$Rn), GPR)>,
Requires<[HasFPUv2_DF]>;
}
defm: FPToIntegerTowardszeroPats<"rz">;
//fld, fst
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
defm FLD : FT_XYAI_LD<0b0010000, "fld">;
defm FLDR : FT_XYAR_LD<0b0010100, "fldr", 0>;
defm FLDR : FT_XYAR_LD<0b0010100, "fldr", 1>;
defm FLDR : FT_XYAR_LD<0b0010100, "fldr", 2>;
defm FLDR : FT_XYAR_LD<0b0010100, "fldr", 3>;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
defm FST : FT_XYAI_ST<0b0010010, "fst">;
defm FSTR : FT_XYAR_ST<0b0010110, "fstr", 0>;
defm FSTR : FT_XYAR_ST<0b0010110, "fstr", 1>;
defm FSTR : FT_XYAR_ST<0b0010110, "fstr", 2>;
defm FSTR : FT_XYAR_ST<0b0010110, "fstr", 3>;
}
defm : LdPat<load, uimm8_2, FLD_S, f32>, Requires<[HasFPUv2_SF]>;
defm : LdPat<load, uimm8_2, FLD_D, f64>, Requires<[HasFPUv2_DF]>;
defm : LdrPat<load, "FLDR_S", f32>, Requires<[HasFPUv2_SF]>;
defm : LdrPat<load, "FLDR_D", f64>, Requires<[HasFPUv2_DF]>;
defm : StPat<store, f32, uimm8_2, FST_S>, Requires<[HasFPUv2_SF]>;
defm : StPat<store, f64, uimm8_2, FST_D>, Requires<[HasFPUv2_DF]>;
defm : StrPat<store, f32, "FSTR_S">, Requires<[HasFPUv2_SF]>;
defm : StrPat<store, f64, "FSTR_D">, Requires<[HasFPUv2_DF]>;
def : Pat<(f32 fpimm:$imm),(COPY_TO_REGCLASS (ORI32 (MOVIH32 (fpimm16_sr16_XFORM fpimm:$imm)), (fpimm16_sr0_XFORM fpimm:$imm)),sFPR32)>,
Requires<[HasFPUv2_SF]>;
def : Pat<(f32 fpimm16_16:$imm),(COPY_TO_REGCLASS (MOVIH32 (fpimm16_sr16_XFORM fpimm16_16:$imm)), sFPR32)>,
Requires<[HasFPUv2_SF]>;
def : Pat<(f32 fpimm16:$imm),(COPY_TO_REGCLASS (MOVI32 (fpimm16_sr0_XFORM fpimm16:$imm)), sFPR32)>,
Requires<[HasFPUv2_SF]>;
def : Pat<(f64(CSKY_BITCAST_FROM_LOHI GPR:$rs1, GPR:$rs2)), (FMTVRH_D(FMTVRL_D GPR:$rs1), GPR:$rs2)>,
Requires<[HasFPUv2_DF]>;
multiclass BRCond_Bin<CondCode CC, string Instr, Instruction Br, Instruction MV> {
let Predicates = [HasFPUv2_SF] in
def : Pat<(brcond (i32 (setcc sFPR32:$rs1, sFPR32:$rs2, CC)), bb:$imm16),
(Br (!cast<Instruction>(Instr#_S) sFPR32:$rs1, sFPR32:$rs2), bb:$imm16)>;
let Predicates = [HasFPUv2_DF] in
def : Pat<(brcond (i32 (setcc sFPR64:$rs1, sFPR64:$rs2, CC)), bb:$imm16),
(Br (!cast<Instruction>(Instr#_D) sFPR64:$rs1, sFPR64:$rs2), bb:$imm16)>;
let Predicates = [HasFPUv2_SF] in
def : Pat<(i32 (setcc sFPR32:$rs1, sFPR32:$rs2, CC)),
(MV (!cast<Instruction>(Instr#_S) sFPR32:$rs1, sFPR32:$rs2))>;
let Predicates = [HasFPUv2_DF] in
def : Pat<(i32 (setcc sFPR64:$rs1, sFPR64:$rs2, CC)),
(MV (!cast<Instruction>(Instr#_D) sFPR64:$rs1, sFPR64:$rs2))>;
}
multiclass BRCond_Bin_SWAP<CondCode CC, string Instr, Instruction Br, Instruction MV> {
let Predicates = [HasFPUv2_SF] in
def : Pat<(brcond (i32 (setcc sFPR32:$rs1, sFPR32:$rs2, CC)), bb:$imm16),
(Br (!cast<Instruction>(Instr#_S) sFPR32:$rs2, sFPR32:$rs1), bb:$imm16)>;
let Predicates = [HasFPUv2_DF] in
def : Pat<(brcond (i32 (setcc sFPR64:$rs1, sFPR64:$rs2, CC)), bb:$imm16),
(Br (!cast<Instruction>(Instr#_D) sFPR64:$rs2, sFPR64:$rs1), bb:$imm16)>;
let Predicates = [HasFPUv2_SF] in
def : Pat<(i32 (setcc sFPR32:$rs1, sFPR32:$rs2, CC)),
(MV (!cast<Instruction>(Instr#_S) sFPR32:$rs2, sFPR32:$rs1))>;
let Predicates = [HasFPUv2_DF] in
def : Pat<(i32 (setcc sFPR64:$rs1, sFPR64:$rs2, CC)),
(MV (!cast<Instruction>(Instr#_D) sFPR64:$rs2, sFPR64:$rs1))>;
}
multiclass BRCond_Un<CondCode CC, string Instr, Instruction Br, Instruction MV, PatLeaf FConstant, PatLeaf IConstant> {
let Predicates = [HasFPUv2_SF] in
def : Pat<(brcond (i32 (setcc sFPR32:$rs1, FConstant, CC)), bb:$imm16),
(Br (!cast<Instruction>(Instr#_S) sFPR32:$rs1), bb:$imm16)>;
let Predicates = [HasFPUv2_DF] in
def : Pat<(brcond (i32 (setcc sFPR64:$rs1, (CSKY_BITCAST_FROM_LOHI IConstant, IConstant), CC)), bb:$imm16),
(Br (!cast<Instruction>(Instr#_D) sFPR64:$rs1), bb:$imm16)>;
let Predicates = [HasFPUv2_SF] in
def : Pat<(i32 (setcc sFPR32:$rs1, FConstant, CC)),
(MV (!cast<Instruction>(Instr#_S) sFPR32:$rs1))>;
let Predicates = [HasFPUv2_DF] in
def : Pat<(i32 (setcc sFPR64:$rs1, (CSKY_BITCAST_FROM_LOHI IConstant, IConstant), CC)),
(MV (!cast<Instruction>(Instr#_D) sFPR64:$rs1))>;
}
// inverse (order && compare) to (unorder || inverse(compare))
defm : BRCond_Bin<SETUNE, "FCMPNE", BT32, MVC32>;
defm : BRCond_Bin<SETOEQ, "FCMPNE", BF32, MVCV32>;
defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, MVC32>;
defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, MVC32>;
defm : BRCond_Bin<SETUO, "FCMPUO", BT32, MVC32>;
defm : BRCond_Bin<SETO, "FCMPUO", BF32, MVCV32>;
defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, MVC32>;
defm : BRCond_Bin_SWAP<SETOLE, "FCMPHS", BT32, MVC32>;
defm : BRCond_Bin<SETNE, "FCMPNE", BT32, MVC32>;
defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, MVCV32>;
defm : BRCond_Bin<SETGE, "FCMPHS", BT32, MVC32>;
defm : BRCond_Bin<SETLT, "FCMPLT", BT32, MVC32>;
defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, MVC32>;
defm : BRCond_Bin_SWAP<SETLE, "FCMPHS", BT32, MVC32>;
// -----------
defm : BRCond_Un<SETOGE, "FCMPZHS", BT32, MVC32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETOLT, "FCMPZHS", BF32, MVCV32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETOLE, "FCMPZLS", BT32, MVC32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETOGT, "FCMPZLS", BF32, MVCV32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETUNE, "FCMPZNE", BT32, MVC32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETOEQ, "FCMPZNE", BF32, MVCV32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETUO, "FCMPZUO", BT32, MVC32, fpimm, (i32 imm)>;
defm : BRCond_Un<SETO, "FCMPZUO", BF32, MVCV32, fpimm, (i32 imm)>;
defm : BRCond_Un<SETGE, "FCMPZHS", BT32, MVC32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETLT, "FCMPZHS", BF32, MVCV32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETLE, "FCMPZLS", BT32, MVC32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETGT, "FCMPZLS", BF32, MVCV32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETNE, "FCMPZNE", BT32, MVC32, fpimm0, (i32 0)>;
defm : BRCond_Un<SETEQ, "FCMPZNE", BF32, MVCV32, fpimm0, (i32 0)>;
No newline at end of file

llvm/lib/Target/CSKY/CSKYInstrInfoF2.td

llvm/lib/Target/CSKY/CSKYMCInstLower.h

llvm/lib/Target/CSKY/CSKYMCInstLower.cpp

llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.h

  • This file was added.
//=- CSKYMachineFunctionInfo.h - CSKY machine function info -------*- C++ -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file declares CSKY-specific per-machine-function information.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_CSKY_CSKYMACHINEFUNCTIONINFO_H
#define LLVM_LIB_TARGET_CSKY_CSKYMACHINEFUNCTIONINFO_H
#include "llvm/CodeGen/MachineFunction.h"
namespace llvm {
class CSKYMachineFunctionInfo : public MachineFunctionInfo {
MachineFunction &MF;
// True if this function has a stack frame.
bool HasStackFrame = false;
// Size of callee saved registers.
unsigned CSRSize = 0;
// Size of registers for byval arg and vararg.
unsigned ArgSize = 0;
// FrameIndex of varargs.
int VarArgsFrameIndex = 0;
unsigned PICLabelUId = 0;
bool SpillsCR = false;
Register GlobalBaseReg = 0;
arsenmUnsubmitted
Not Done
ReplyInline Actions

I'm trying to remove the dependency on machine function state in the constructor in D80249

arsenm: I'm trying to remove the dependency on machine function state in the constructor in D80249
zixuan-wuAuthorUnsubmitted
Done
ReplyInline Actions

D80249 has not been committed yet. I think I can rebase and catch up D80249 if it's committed before I commit this patch. If not, I would keep machine function state as original.

zixuan-wu: D80249 has not been committed yet. I think I can rebase and catch up D80249 if it's committed…
public:
CSKYMachineFunctionInfo(MachineFunction &MF) : MF(MF) {}
bool hasStackFrame() const { return HasStackFrame; }
void setHasStackFrame(bool v) { HasStackFrame = v; }
unsigned getCSRSize() const { return CSRSize; }
void setCSRSize(unsigned int size) { CSRSize = size; }
void setSpillsCR() { SpillsCR = true; }
bool isCRSpilled() const { return SpillsCR; }
unsigned getArgRegsSaveSize() const { return ArgSize; }
void setArgRegsSaveSize(unsigned size) { ArgSize = size; }
void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
void initPICLabelUId(unsigned UId) { PICLabelUId = UId; }
unsigned createPICLabelUId() { return PICLabelUId++; }
Register getGlobalBaseReg() const { return GlobalBaseReg; }
void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }
};
} // namespace llvm
#endif // LLVM_LIB_TARGET_CSKY_CSKYMACHINEFUNCTIONINFO_H

llvm/lib/Target/CSKY/CSKYMachineFunctionInfo.cpp

llvm/lib/Target/CSKY/CSKYRegisterInfo.h

llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp

  • This file was added.
//===-- CSKYRegisterInfo.h - CSKY Register Information Impl ---*- C++ -*---===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the CSKY implementation of the TargetRegisterInfo class.
//
//===----------------------------------------------------------------------===//
#include "CSKYRegisterInfo.h"
#include "CSKY.h"
#include "CSKYSubtarget.h"
#include "Utils/CSKYBaseInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#define GET_REGINFO_TARGET_DESC
#include "CSKYGenRegisterInfo.inc"
using namespace llvm;
CSKYRegisterInfo::CSKYRegisterInfo() : CSKYGenRegisterInfo(CSKY::LR, 0, 0, 0) {}
const uint32_t *
CSKYRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID Id) const {
const CSKYSubtarget &STI = MF.getSubtarget<CSKYSubtarget>();
if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat())
return CSR_GPR_FPR64_RegMask;
if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat())
return CSR_GPR_FPR32_RegMask;
return CSR_I32_RegMask;
}
BitVector CSKYRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
markSuperRegs(Reserved, CSKY::SP);
markSuperRegs(Reserved, CSKY::R26);
markSuperRegs(Reserved, CSKY::R27);
markSuperRegs(Reserved, CSKY::GP);
markSuperRegs(Reserved, CSKY::R29);
markSuperRegs(Reserved, CSKY::R30);
markSuperRegs(Reserved, CSKY::R31);
// TODO: FP, BP
assert(checkAllSuperRegsMarked(Reserved));
return Reserved;
}
Register CSKYRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
// TODO: FP
return CSKY::SP;
}
Register CSKYRegisterInfo::getBaseRegister() const { return CSKY::R9; }
const MCPhysReg *
CSKYRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const CSKYSubtarget &STI = MF->getSubtarget<CSKYSubtarget>();
if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat())
return CSR_GPR_FPR64_SaveList;
if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat())
return CSR_GPR_FPR32_SaveList;
return CSR_I32_SaveList;
}
void CSKYRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS) const {
assert(!SPAdj && "Unexpected zero SPAdj.");
MachineInstr *MI = &*II;
arsenmUnsubmitted
Done
ReplyInline Actions

Can do just MI->getOpcode()

arsenm: Can do just MI->getOpcode()
auto DL = MI->getDebugLoc();
MachineBasicBlock &MBB = *MI->getParent();
MachineFunction &MF = *MBB.getParent();
const CSKYFrameLowering *CFI = getFrameLowering(MF);
const CSKYInstrInfo *TII = MF.getSubtarget<CSKYSubtarget>().getInstrInfo();
arsenmUnsubmitted
Done
ReplyInline Actions

Register

arsenm: Register
MachineRegisterInfo &MRI = MF.getRegInfo();
MachineInstr *NewMI = nullptr;
switch (MI->getOpcode()) {
default:
break;
case CSKY::RESTORE_CARRY: {
Register NewReg = MRI.createVirtualRegister(&CSKY::GPRRegClass);
NewMI = BuildMI(MBB, II, DL, TII->get(CSKY::LD32W), NewReg)
.add(MI->getOperand(1))
.add(MI->getOperand(2))
.getInstr();
BuildMI(MBB, II, DL, TII->get(CSKY::BTSTI32))
.add(MI->getOperand(0))
.addReg(NewReg, getKillRegState(true))
.addImm(0);
MBB.erase(MI->getIterator());
break;
}
case CSKY::SPILL_CARRY: {
Register NewReg = MRI.createVirtualRegister(&CSKY::GPRRegClass);
BuildMI(MBB, II, DL, TII->get(CSKY::MVC32), NewReg).add(MI->getOperand(0));
NewMI = BuildMI(MBB, II, DL, TII->get(CSKY::ST32W))
.addReg(NewReg, getKillRegState(true))
.add(MI->getOperand(1))
.add(MI->getOperand(2))
.getInstr();
MBB.erase(MI->getIterator());
break;
}
}
if (NewMI != nullptr)
MI = NewMI;
Register FrameReg;
int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
int Offset = CFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
if (rewriteFrameIndex(*MI, FIOperandNum, FrameReg, Offset, TII))
return;
// TODO:: use sratchReg
}
bool CSKYRegisterInfo::rewriteFrameIndex(MachineInstr &MI,
unsigned FrameRegIndex,
Register FrameReg, int &Offset,
const CSKYInstrInfo *TII) const {
unsigned Opcode = MI.getOpcode();
MachineOperand *RegOp = nullptr;
MachineOperand *ImmOp = nullptr;
switch (Opcode) {
default:
RegOp = &MI.getOperand(FrameRegIndex);
ImmOp = &MI.getOperand(FrameRegIndex + 1);
break;
case CSKY::LDM32_2:
case CSKY::STM32_2:
RegOp = &MI.getOperand(FrameRegIndex);
break;
}
arsenmUnsubmitted
Done
ReplyInline Actions

Constant if

arsenm: Constant if
if (RegOp != nullptr)
RegOp->ChangeToRegister(FrameReg, false);
if (ImmOp != nullptr)
ImmOp->ChangeToImmediate(Offset);
return true;
}

llvm/lib/Target/CSKY/CSKYRegisterInfo.td

llvm/lib/Target/CSKY/CSKYSubtarget.h

llvm/lib/Target/CSKY/CSKYSubtarget.cpp

  • This file was added.
//===-- CSKYSubtarget.h - Define Subtarget for the CSKY----------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file declares the CSKY specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//
#include "CSKYSubtarget.h"
using namespace llvm;
#define DEBUG_TYPE "csky-subtarget"
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "CSKYGenSubtargetInfo.inc"
static cl::opt<bool>
CSKYConstantIslands("csky-constant-islands", cl::NotHidden,
cl::desc("Enable csky constant islands."),
cl::init(true));
void CSKYSubtarget::initializeEnvironment() {
HasFPUv2SingleFloat = false;
HasFPUv2DoubleFloat = false;
HasFPUv2 = false;
HasFPUv3HalfWord = false;
HasFPUv3HalfFloat = false;
HasFPUv3SingleFloat = false;
HasFPUv3DoubleFloat = false;
HasFPUv3 = false;
HasFdivdu = false;
UseSoftFloat = true;
Has3E3r1 = false;
}
bool CSKYSubtarget::useConstantIslands() const { return CSKYConstantIslands; }
CSKYSubtarget &CSKYSubtarget::initializeSubtargetDependencies(const Triple &TT,
StringRef CPU,
StringRef FS) {
arsenmUnsubmitted
Done
ReplyInline Actions

No reason to use std:: string here

arsenm: No reason to use std:: string here
initializeEnvironment();
if (CPU.empty())
CPU = "generic-csky";
ParseSubtargetFeatures(CPU, CPU, FS);
return *this;
}
CSKYSubtarget::CSKYSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
const TargetMachine &TM)
: CSKYGenSubtargetInfo(TT, CPU, CPU, FS),
FrameLowering(initializeSubtargetDependencies(TT, CPU, FS)),
InstrInfo(*this), RegInfo(), TLInfo(TM, *this) {}

llvm/lib/Target/CSKY/CSKYTargetMachine.h

llvm/lib/Target/CSKY/CSKYTargetMachine.cpp

  • This file was added.
//===--- CSKYTargetMachine.cpp - Define TargetMachine for CSKY ------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// Implements the info about CSKY target spec.
//
//===----------------------------------------------------------------------===//
#include "CSKYTargetMachine.h"
#include "CSKY.h"
#include "CSKYTargetObjectFile.h"
#include "TargetInfo/CSKYTargetInfo.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTarget() {
RegisterTargetMachine<CSKYTargetMachine> X(getTheCSKYTarget());
PassRegistry *Registry = PassRegistry::getPassRegistry();
// TODO: Initialize pass
initializeCSKYConstantIslandsPass(*Registry);
}
using namespace llvm;
// Specifies how data is to be laid out in memory.
// The layout specification consists of a list of specifications separated by
// the minus sign character ('-').
static std::string computeDataLayout(const Triple &TT) {
std::string Ret;
// Specifies target lays out data in Big or Little endian form.
Ret += "e";
// S<size> Specifies the natural alignment of the stack in bits.
Ret += "-S32";
Ret += DataLayout::getManglingComponent(TT);
// p[n]:<size>:<abi>:<pref>:<idx>
// Specifies the size of a pointer and its <abi> and <pref> erred alignments
// for address space n.
Ret += "-p:32:32";
// i<size>:<abi>:<pref>
// This specifies the alignment for an integer type of a given bit <size>.
Ret += "-i32:32:32";
Ret += "-i64:32:32";
// f<size>:<abi>:<pref>
// This specifies the alignment for a floating-point type of a given bit
// <size>.
Ret += "-f32:32:32";
Ret += "-f64:32:32";
// v<size>:<abi>:<pref>
// This specifies the alignment for a vector type of a given bit <size>.
Ret += "-v64:32:32";
Ret += "-v128:32:32";
// S<size> Specifies the natural alignment of the stack in bits.
Ret += "-S32";
// a:<abi>:<pref> This specifies the alignment for an object of aggregate
// type.
Ret += "-a:0:32";
// F<type><abi> Specifies the alignment for function pointers.
Ret += "-Fi32";
// n<size1>:<size2>:<size3>... Specifies a set of native integer widths for
// target.
Ret += "-n32";
return Ret;
}
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
Optional<Reloc::Model> RM) {
if (!RM.hasValue())
return Reloc::Static;
return *RM;
}
CSKYTargetMachine::CSKYTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Optional<Reloc::Model> RM,
Optional<CodeModel::Model> CM,
CodeGenOpt::Level OL, bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<CSKYELFTargetObjectFile>()) {
initAsmInfo();
}
const CSKYSubtarget *
CSKYTargetMachine::getSubtargetImpl(const Function &F) const {
Attribute CPUAttr = F.getFnAttribute("target-cpu");
Attribute FSAttr = F.getFnAttribute("target-features");
craig.topperUnsubmitted
Done
ReplyInline Actions

Replace this with

std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;

Same for FSAttr. This change made was to all targets in tree a few weeks ago.

craig.topper: Replace this with ``` std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str()…
std::string CPU =
CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
std::string FS =
FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
std::string Key = CPU + FS;
auto &I = SubtargetMap[Key];
if (!I) {
// This needs to be done before we create a new subtarget since any
// creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions.
resetTargetOptions(F);
I = std::make_unique<CSKYSubtarget>(TargetTriple, CPU, FS, *this);
}
return I.get();
arsenmUnsubmitted
Not Done
ReplyInline Actions

We should move this logic into the base implementation with a template argument for the subtarget class; I think every target reproduces approximately the same thing

arsenm: We should move this logic into the base implementation with a template argument for the…
zixuan-wuAuthorUnsubmitted
Done
ReplyInline Actions

Yes, it's too much housekeeping work. But it's another orthogonal issue and should be handled together with other targets in other patch.

zixuan-wu: Yes, it's too much housekeeping work. But it's another orthogonal issue and should be handled…
}
namespace {
class CSKYPassConfig : public TargetPassConfig {
public:
CSKYPassConfig(CSKYTargetMachine &TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {}
CSKYTargetMachine &getCSKYTargetMachine() const {
return getTM<CSKYTargetMachine>();
}
// TODO: override add pass API
bool addInstSelector() override;
void addIRPasses() override;
void addPreEmitPass() override;
};
void CSKYPassConfig::addIRPasses() {
addPass(createAtomicExpandPass());
TargetPassConfig::addIRPasses();
}
bool CSKYPassConfig::addInstSelector() {
addPass(createCSKYISelDag(getCSKYTargetMachine()));
return false;
}
void CSKYPassConfig::addPreEmitPass() {
addPass(createCSKYConstantIslandPass());
addPass(&BranchRelaxationPassID);
}
} // namespace
TargetPassConfig *CSKYTargetMachine::createPassConfig(PassManagerBase &PM) {
return new CSKYPassConfig(*this, PM);
}

llvm/lib/Target/CSKY/CSKYTargetObjectFile.h

llvm/lib/Target/CSKY/CSKYTargetObjectFile.cpp

llvm/lib/Target/CSKY/Disassembler/CMakeLists.txt

llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp

llvm/lib/Target/CSKY/Disassembler/LLVMBuild.txt

llvm/lib/Target/CSKY/LLVMBuild.txt

llvm/lib/Target/CSKY/MCTargetDesc/CMakeLists.txt

llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp

llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp

llvm/lib/Target/CSKY/MCTargetDesc/CSKYFixupKinds.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCExpr.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCExpr.cpp

  • This file was added.
//===-- CSKYMCExpr.cpp - CSKY specific MC expression classes -*- C++ -*----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "CSKYMCExpr.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCStreamer.h"
using namespace llvm;
#define DEBUG_TYPE "cskymcexpr"
const CSKYMCExpr *CSKYMCExpr::create(const MCExpr *Expr, VariantKind Kind,
MCContext &Ctx) {
return new (Ctx) CSKYMCExpr(Kind, Expr);
}
void CSKYMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
Expr->print(OS, MAI);
switch (Kind) {
default:
LLVM_DEBUG(dbgs() << "Kind = " << Kind << ".");
llvm_unreachable("Invalid kind!");
case VK_CSKY_None:
break;
case VK_CSKY_ADDR_HI:
OS << "@hi";
break;
case VK_CSKY_ADDR_LO:
OS << "@lo";
break;
case VK_CSKY_GOT_HI:
OS << "@GOT_HI16";
break;
case VK_CSKY_GOT_LO:
OS << "@GOT_LO16";
break;
case VK_CSKY_GOTOFF_HI:
OS << "@GOTOFF_HI16";
break;
case VK_CSKY_GOTOFF_LO:
OS << "@GOTOFF_LO16";
break;
case VK_CSKY_GOT:
case VK_CSKY_GOT12:
OS << "@GOT";
break;
case VK_CSKY_GOTOFF:
OS << "@GOTOFF";
break;
case VK_CSKY_ADDR:
break;
case VK_CSKY_TLSGD:
craig.topperUnsubmitted
Done
ReplyInline Actions

Is this code needed?

craig.topper: Is this code needed?
break;
case VK_CSKY_TPOFF:
break;
case VK_CSKY_GOTTPOFF:
break;
}
}
void CSKYMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
Streamer.visitUsedExpr(*getSubExpr());
}
bool CSKYMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup))
return false;
Res =
MCValue::get(Res.getSymA(), Res.getSymB(), Res.getConstant(), getKind());
return true;
}

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp

llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetAsmStreamer.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetAsmStreamer.cpp

llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetELFStreamer.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetELFStreamer.cpp

llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.h

llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.cpp

llvm/lib/Target/CSKY/MCTargetDesc/LLVMBuild.txt

llvm/lib/Target/CSKY/README.txt

llvm/lib/Target/CSKY/TargetInfo/CMakeLists.txt

llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.h

llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp

llvm/lib/Target/CSKY/TargetInfo/LLVMBuild.txt

llvm/lib/Target/CSKY/Utils/CMakeLists.txt

llvm/lib/Target/CSKY/Utils/CSKYBaseInfo.h

llvm/lib/Target/CSKY/Utils/CSKYBaseInfo.cpp

llvm/lib/Target/CSKY/Utils/LLVMBuild.txt

llvm/lib/Target/LLVMBuild.txt

llvm/test/CodeGen/CSKY/add.ll

llvm/test/CodeGen/CSKY/and.ll

llvm/test/CodeGen/CSKY/ashr.ll

llvm/test/CodeGen/CSKY/atomicrmw.ll

llvm/test/CodeGen/CSKY/br-double.ll

llvm/test/CodeGen/CSKY/br-float.ll

llvm/test/CodeGen/CSKY/br.ll

llvm/test/CodeGen/CSKY/call.ll

llvm/test/CodeGen/CSKY/cmpxchg.ll

llvm/test/CodeGen/CSKY/fadd.ll

llvm/test/CodeGen/CSKY/fcmp.ll

llvm/test/CodeGen/CSKY/fdiv.ll

llvm/test/CodeGen/CSKY/fmul.ll

llvm/test/CodeGen/CSKY/fneg.ll

llvm/test/CodeGen/CSKY/fpext.ll

llvm/test/CodeGen/CSKY/fptosi.ll

llvm/test/CodeGen/CSKY/fptoui.ll

llvm/test/CodeGen/CSKY/fptrunc.ll

llvm/test/CodeGen/CSKY/frem.ll

llvm/test/CodeGen/CSKY/fsub.ll

llvm/test/CodeGen/CSKY/icmp.ll

llvm/test/CodeGen/CSKY/indirectbr.ll

llvm/test/CodeGen/CSKY/inttoptr.ll

llvm/test/CodeGen/CSKY/ld-float.ll

llvm/test/CodeGen/CSKY/ld.ll

llvm/test/CodeGen/CSKY/lit.local.cfg

llvm/test/CodeGen/CSKY/lshr.ll

llvm/test/CodeGen/CSKY/mul.ll

llvm/test/CodeGen/CSKY/mula.ll

llvm/test/CodeGen/CSKY/or.ll

llvm/test/CodeGen/CSKY/ptrtoint.ll

llvm/test/CodeGen/CSKY/sdiv.ll

llvm/test/CodeGen/CSKY/select-float.ll

llvm/test/CodeGen/CSKY/select.ll

llvm/test/CodeGen/CSKY/sext.ll

llvm/test/CodeGen/CSKY/shl.ll

llvm/test/CodeGen/CSKY/sitofp.ll

llvm/test/CodeGen/CSKY/srem.ll

llvm/test/CodeGen/CSKY/st-float.ll

llvm/test/CodeGen/CSKY/st.ll

llvm/test/CodeGen/CSKY/sub.ll

llvm/test/CodeGen/CSKY/switch.ll

llvm/test/CodeGen/CSKY/trunc.ll

llvm/test/CodeGen/CSKY/udiv.ll

llvm/test/CodeGen/CSKY/uitofp.ll

llvm/test/CodeGen/CSKY/urem.ll

llvm/test/CodeGen/CSKY/xor.ll

llvm/test/CodeGen/CSKY/zext.ll

llvm/utils/UpdateTestChecks/asm.py