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[RISCV 3/10] Add stub backend
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Authored by asb on Aug 16 2016, 8:22 AM.

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Summary

This contains just enough for lib/Target/RISCV to compile. Notably a basic RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc -march=riscv32 myinput.ll and will find it fails due to the lack of MCAsmInfo.

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rL LLVM

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asb updated this revision to Diff 68186.Aug 16 2016, 8:22 AM
asb retitled this revision from to [RISCV 3/10] Add stub backend.
asb updated this object.
asb added reviewers: theraven, jyknight.
asb added a subscriber: llvm-commits.
emaste added a subscriber: emaste.Aug 16 2016, 2:42 PM
t.p.northover added inline comments.
lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
19 ↗(On Diff #68186)

Does it support JIT? I'd have thought you'd flip this when implementing the pseudo-linker under lib/ExecutionEngine.

asb updated this revision to Diff 68378.Aug 17 2016, 10:20 AM
asb marked an inline comment as done.

Address review comment from @t.p.northover

lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
19 ↗(On Diff #68186)

That's an error - good catch! Thanks.

jyknight added inline comments.Aug 18 2016, 10:56 AM
lib/Target/RISCV/RISCVTargetMachine.cpp
40 ↗(On Diff #68378)

Default model is expected to be PIC instead of static? That's different from most general purpose targets. Perhaps deserves a comment? Or a note in the nonexistent psABI doc. :)

asb updated this revision to Diff 68685.Aug 19 2016, 7:30 AM
asb marked an inline comment as done.

Address review comment from @jyknight, match RISC-V gcc's behaviour in defaulting to Reloc::Static.

jyknight accepted this revision.Aug 19 2016, 8:23 AM
jyknight edited edge metadata.
This revision is now accepted and ready to land.Aug 19 2016, 8:23 AM
reames added a subscriber: reames.Aug 21 2016, 12:04 PM
reames added inline comments.
lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
27 ↗(On Diff #68685)

Might want to add an assert(false && "not yet implemented").

asb updated this revision to Diff 69347.Aug 26 2016, 5:17 AM
asb edited edge metadata.
asb marked an inline comment as done.

Add a link to the RISC-V ISA docs in CompilerWriterInfo.rst

lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
27 ↗(On Diff #68685)

llvm_unreachable would be even better. However in this specific case we actually need to define LLVMInitializeRISCVTargetMC as a no-op. llc will call the initialisation functions for all backends that were compiled in, so if this function is made to assert it means that all codegen tests for other archs will fail.

I've modified the comment to be clear it's not purely a matter of being present for linking.

theraven edited edge metadata.Aug 26 2016, 5:58 AM

A couple of small nits inline.

CMakeLists.txt
276 ↗(On Diff #69347)

Not really an objection, but MIPS and SPARC are both capitalised as if they were words. It would be more consistent to call the back end RiscV, though this would be ugly.

docs/CompilerWriterInfo.rst
86 ↗(On Diff #69347)

Please also add a link to the ABI spec here.

lib/Target/RISCV/RISCVTargetMachine.cpp
34 ↗(On Diff #69347)

Please assert TT.isArch32Bit() here, so that we catch fire if someone tries to use this back end for the 128-bit RISC-V variant in the future.

asb updated this revision to Diff 69361.Aug 26 2016, 6:34 AM
asb edited edge metadata.
asb marked 2 inline comments as done.

assert if trying to compile for RV128 (or at least, a RISC-V that is neither 32-bit or 64-bit).

CMakeLists.txt
276 ↗(On Diff #69347)

Yes, after considering the alternatives I decided RISCV would be least ugly. Plus ARM of course goes for all caps too.

docs/CompilerWriterInfo.rst
86 ↗(On Diff #69347)

What exists of the ABI spec is contained within the user-level ISA specification (chapter 20). The separate ABI doc was an extract from the user-level ISA that was put out because the ABI supported by the tools was changed in-between ISA releases. The v2.1 spec contains the most up to date and complete ABI specification.

I think everything here looks reasonable now. I only had a minor comment though so it may be good to check others are happy.

asb updated this revision to Diff 74223.EditedOct 11 2016, 3:47 AM

Refresh patch to follow the changes made to other backends in rL283702, moving TheRISCV32Target and TheRISCV64Target behind an accessor function.

This revision was automatically updated to reflect the committed changes.