This is an archive of the discontinued LLVM Phabricator instance.

Differential D77097

[ARM] Add data gathering hint instruction
ClosedPublic

Authored by stuij on Mar 30 2020, 2:48 PM.

Details

Reviewers
t.p.northover
rengolin
SjoerdMeijer
ab
danielkiss
samparker
Commits
rGcb6aeb223929: [ARM] Add data gathering hint instruction
Summary

This patch upstreams support the optional ARMv8.0 Data Gathering Hint (DGH)
extension, which adds the Data Gathering Hint instruction to the hint
space.

See ARMv8.0-DGH in the Arm Architecture Reference Manual Armv8 for more
information.

Diff Detail

Event Timeline

stuij created this revision.Mar 30 2020, 2:48 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 30 2020, 2:48 PM
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
stuij added reviewers: t.p.northover, rengolin, SjoerdMeijer, ab, danielkiss, samparker.Mar 30 2020, 2:55 PM
stuij edited the summary of this revision. (Show Details)
stuij added subscribers: ostannard, LukeGeeson.
Harbormaster completed remote builds in B51034: Diff 253710.Mar 30 2020, 3:52 PM
SjoerdMeijer added inline comments.Mar 31 2020, 9:15 AM
llvm/test/MC/AArch64/armv8.6a-dgh.s
1 ↗(On Diff #253710)

If this is optional in v8.0, I guess this does not necessarily need to be in a file called armv8.6.a-dgh.s. Can you just stick in a the file with the other hint instructions? Saves us a whole 1-line test file.

stuij updated this revision to Diff 254035.Mar 31 2020, 4:20 PM
stuij edited the summary of this revision. (Show Details)

put tests in existing files

Harbormaster completed remote builds in B51213: Diff 254035.Mar 31 2020, 5:06 PM
SjoerdMeijer accepted this revision.Apr 1 2020, 12:36 AM

Cheers, LGTM

This revision is now accepted and ready to land.Apr 1 2020, 12:36 AM
Closed by commit rGcb6aeb223929: [ARM] Add data gathering hint instruction (authored by olista01, committed by stuij). · Explain WhyApr 5 2020, 8:00 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
1 line
test/
MC/
AArch64/
2 lines
Disassembler/
AArch64/
2 lines

Diff 255167

llvm/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 705 Lines • ▼ Show 20 Lines
def HINT : HintI<"hint">; def HINT : HintI<"hint">;
def : InstAlias<"nop", (HINT 0b000)>; def : InstAlias<"nop", (HINT 0b000)>;
def : InstAlias<"yield",(HINT 0b001)>; def : InstAlias<"yield",(HINT 0b001)>;
def : InstAlias<"wfe", (HINT 0b010)>; def : InstAlias<"wfe", (HINT 0b010)>;
def : InstAlias<"wfi", (HINT 0b011)>; def : InstAlias<"wfi", (HINT 0b011)>;
def : InstAlias<"sev", (HINT 0b100)>; def : InstAlias<"sev", (HINT 0b100)>;
def : InstAlias<"sevl", (HINT 0b101)>; def : InstAlias<"sevl", (HINT 0b101)>;
def : InstAlias<"dgh", (HINT 0b110)>;
def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>; def : InstAlias<"esb", (HINT 0b10000)>, Requires<[HasRAS]>;
def : InstAlias<"csdb", (HINT 20)>; def : InstAlias<"csdb", (HINT 20)>;
def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>; def : InstAlias<"bti", (HINT 32)>, Requires<[HasBTI]>;
def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>; def : InstAlias<"bti $op", (HINT btihint_op:$op)>, Requires<[HasBTI]>;
// v8.2a Statistical Profiling extension // v8.2a Statistical Profiling extension
def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>; def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
▲ Show 20 Lines • Show All 6,645 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/basic-a64-instructions.s

Show First 20 Lines • Show All 3,459 Lines • ▼ Show 20 Lines
// CHECK: hint #{{127|0x7f}} // encoding: [0xff,0x2f,0x03,0xd5] // CHECK: hint #{{127|0x7f}} // encoding: [0xff,0x2f,0x03,0xd5]
nop nop
yield yield
wfe wfe
wfi wfi
sev sev
sevl sevl
dgh
// CHECK: nop // encoding: [0x1f,0x20,0x03,0xd5] // CHECK: nop // encoding: [0x1f,0x20,0x03,0xd5]
// CHECK: yield // encoding: [0x3f,0x20,0x03,0xd5] // CHECK: yield // encoding: [0x3f,0x20,0x03,0xd5]
// CHECK: wfe // encoding: [0x5f,0x20,0x03,0xd5] // CHECK: wfe // encoding: [0x5f,0x20,0x03,0xd5]
// CHECK: wfi // encoding: [0x7f,0x20,0x03,0xd5] // CHECK: wfi // encoding: [0x7f,0x20,0x03,0xd5]
// CHECK: sev // encoding: [0x9f,0x20,0x03,0xd5] // CHECK: sev // encoding: [0x9f,0x20,0x03,0xd5]
// CHECK: sevl // encoding: [0xbf,0x20,0x03,0xd5] // CHECK: sevl // encoding: [0xbf,0x20,0x03,0xd5]
// CHECK: dgh // encoding: [0xdf,0x20,0x03,0xd5]
clrex clrex
clrex #0 clrex #0
clrex #7 clrex #7
clrex #15 clrex #15
// CHECK: clrex // encoding: [0x5f,0x3f,0x03,0xd5] // CHECK: clrex // encoding: [0x5f,0x3f,0x03,0xd5]
// CHECK: clrex #0 // encoding: [0x5f,0x30,0x03,0xd5] // CHECK: clrex #0 // encoding: [0x5f,0x30,0x03,0xd5]
// CHECK: clrex #7 // encoding: [0x5f,0x37,0x03,0xd5] // CHECK: clrex #7 // encoding: [0x5f,0x37,0x03,0xd5]
▲ Show 20 Lines • Show All 1,396 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

Show First 20 Lines • Show All 3,027 Lines • ▼ Show 20 Lines
# CHECK: nop # CHECK: nop
# CHECK: hint #{{127|0x7f}} # CHECK: hint #{{127|0x7f}}
# CHECK: nop # CHECK: nop
# CHECK: yield # CHECK: yield
# CHECK: wfe # CHECK: wfe
# CHECK: wfi # CHECK: wfi
# CHECK: sev # CHECK: sev
# CHECK: sevl # CHECK: sevl
# CHECK: dgh
0x1f 0x20 0x3 0xd5 0x1f 0x20 0x3 0xd5
0xff 0x2f 0x3 0xd5 0xff 0x2f 0x3 0xd5
0x1f 0x20 0x3 0xd5 0x1f 0x20 0x3 0xd5
0x3f 0x20 0x3 0xd5 0x3f 0x20 0x3 0xd5
0x5f 0x20 0x3 0xd5 0x5f 0x20 0x3 0xd5
0x7f 0x20 0x3 0xd5 0x7f 0x20 0x3 0xd5
0x9f 0x20 0x3 0xd5 0x9f 0x20 0x3 0xd5
0xbf 0x20 0x3 0xd5 0xbf 0x20 0x3 0xd5
0xdf,0x20,0x3,0xd5
# CHECK: clrex # CHECK: clrex
# CHECK: clrex #0 # CHECK: clrex #0
# CHECK: clrex #7 # CHECK: clrex #7
# CHECK: clrex # CHECK: clrex
0x5f 0x3f 0x3 0xd5 0x5f 0x3f 0x3 0xd5
0x5f 0x30 0x3 0xd5 0x5f 0x30 0x3 0xd5
0x5f 0x37 0x3 0xd5 0x5f 0x37 0x3 0xd5
▲ Show 20 Lines • Show All 1,277 Lines • Show Last 20 Lines